SU677085A1 - Delay device - Google Patents

Description

The invention relates to a pulse technique and is intended for use in pulsed wireless devices for various purposes, in particular in correlation receivers of pseudo-random signals, where it is necessary to delay the pulse sequences for a time much longer than the pulse duration.

Delay devices are known that contain control and work counters, a multi-digit number comparison unit, a clock generator, a match element, switches 1.

These devices have insufficient accuracy in the delay of pulses, much longer than their duration.

Also known delay device containing a generator, driver clock pulses, the main delay unit, an additional delay unit, a memory device, the code sensor {2.

A disadvantage of the known devices is their complexity.

The purpose of the invention is to simplify the device.

The proposed device comprises a generator, a clock pulse shaper, a main delay unit including a control element connected in series, a counter and a shift register, an additional delay block including a control element connected in series and a counter, a memory device whose information inputs are connected to the discharge outputs of the counter of the main block delays, and the outputs - to the inputs of the bits of the counter of the additional delay unit. The input to the write control of the storage device is connected to the first output of the clock generator, and the input to the control of the readout of the storage device to the output of the shift register. The generator output is connected to the first inputs of the control elements of the main and additional delay units and to the first input of the clock pulse generator, the second input of which is connected to the sensor input

code and with the second input of the control unit of the main delay unit, and the third with the output of the counter of the main delay unit connected to the input of the register, the second input of which is connected to the second

the output of the clock pulse. The information outputs of the code sensor are connected to the input of the shift register, the third input of the control element of the main delay unit is connected to the first

the output of the clock pulse generator, the second input of the control element of the additional delay unit to the register output, and the third to the output of the counter of this delay unit.

A feature of the proposed device is that the second input of the counter of the main delay unit is connected to the second output of the clock pulse generator.

The drawing shows a block diagram of the device.

The device comprises a generator 1, a clock driver 2, a main delay unit 3 consisting of control element 4, counter 5, a shift register 6, an additional delay block 7 consisting of control element 8 and counter 9, a memory 10 consisting of from input device 11, memory block 12 and output device 13, sensor 14, code.

In known devices, the code sensor contains information about the amount of delay in the form of Tz (fi + l), where (+1) is an integer number of periods of the clock frequency, which decreases on the interval Tz, ATz- (k +) T. The code sensor contains two memories. The first memory block has the number a, equal to the number of generator pulses that fit on the time interval, i.e. a -, and the second memory block TI is the number k.

The information from the first memory block of the code sensor is entered into the counter of the main delay block, and from the second memory block into the shift register. Since the value of A varies from O to T, it is necessary to have at least 100 bits in the code sensor to measure this value, and as accuracy requirements increase, the number of bits increases. With a pulse duration of 2 MKS, for their combination it is necessary to carry out a delay with an accuracy of I MKS, since with and a delay of 2000 µs, then 200 bits.

In the proposed device, the function of storing information about the magnitude of A performs a memory device without increasing the memory size of the memory device. Thus, only the number k is stored in the code sensor, and the information output of the code sensor is connected to the information input of the shift register of the main delay device. The second input of the counter of the main delay device is connected to the second output of the clock pulse generator, which is the command to stop counting. At this moment, at the output of the counter of the main delay unit connected to the first input of the shift register of the main delay unit and to the input of the clock frequency generator, a pulse appears that introduces a unit to the first digit

register shift. The signal from the first output of the clock pulse generator, connected to the second input of the control element of the main delay unit and to the input of the input device of the memory block, closes the counting counter input to pass the generator pulses and reads information from the counter to the memory block.

The memory cells are written.

numbers A-AIZM. where Ashm. - temporary

the interval measured by the main counter

block delay.

With the advent of (fe + l) -ro pulse clock

the frequency after writing the unit to the shift register, at the output of the shift register connected to the input of the memory output device, a pulse appears, reading in order of priority from the memory cells of the number A-At. to the counter of the additional delay device, leaving the number A in the memory unit slots. The output of the shift register of the main delay device is also connected to the second control input of the control element of the additional delay unit, the first control input of the control element is connected to the output of the counter of the additional block

additional block delays. Consequently, after entering the A-AIZM number from the memory block into the counter, the control element opens and the counting of the generator pulses in the counter of the additional delay unit begins, when the GT + number (A-Aiiz) is reached, an overflow pulse appears at the output, which is the output pulse which closes the control and the count is terminated.

Claims (2)

1. Vazhenina 3. P. et al. Methods and schemes for the time delay of pulsed signals. M., “Owls. radio, 1971. 2. USSR author's certificate number 441642, cl. H 03 H 7/30, 1972.