SU573888A1 - Device for on-lwe monitoring of communication channels - Google Patents

Description

The invention relates to communication technology and can be used in the measurement; accuracy of discrete information transmission.

A device for the operational control of communication channels is known, comprising a serially connected input matching block, an analyzer of input pulses, and a counter for errors. .

However, it has insufficient accuracy of monitoring of communication channels.

In order to eliminate this drawback, an account resolving unit, a clock counter and an error ratio determination unit are introduced into the device for operative control of communication channels according to the invention. The control output of the error counter is connected to the input of the error rate determination unit, allowing the output through the serially connected counting resolution unit and the pulse counter, to another input of which clock pulses are fed, to the information inputs of the scribe factor determining unit, the output of which is connected to the error counter reset outputs and block the resolution of the account, and allowing the output of the error counter under

Connected to the enable input of the error ratio determination unit.

The block for determining the error rate contains a block of memory

the control unit, whose outputs are connected to the inputs of the display unit, controls the outputs of the memory unit connected to the control inputs of the control unit, the prohibiting inputs of which, the prohibiting outputs of the unit are connected, and the memory unit contains triggers impulses and Sbrfs unit, with the inputs Installation of the triggers combined and connected to the output of the first OR element, to one of the inputs of which the input Installation 1 of the corresponding trigger is connected to which the first is connected

the input of the second element OR, to the second input of which and to the second input of the first element OR the output of the reset unit is connected, to the third input of the second element OR the connection

the output of the pulse edge selection unit, and the third input of the first element OR is a reset input, a memory unit.

FIG. 1 is a block diagram

Claims (3)

the proposed device for the operational control of communication channels; Fig. 2 is a structural electrical circuit for determining the coefficient of compression. The device for operational control of communication channels contains serially connected input matching unit 1, analyzer 2 input pulses, 3 error counter, serially connected counting resolution unit 4 and counter 5 clock pulses, as well as block 6 for determining the error rate. The control output of the error counter 3 is connected to the input of the block for determining the coefficient of the error sideways, and the allowing output through sequentially connected block / resolution of the circuit 4 and the counter of 5 clock pulses, to the other input of which clock pulses are fed, to the information inputs of the coefficient determining unit 6 error, the output of which is connected to the inputs x; throw counter 3 errors and block 4 resolution resolution. The permissive output of the error counter 3. is also connected to the permissive input of the block 6 for determining the error coefficient on the side. The error ratio determination unit (Fig. 2) contains a memory unit 7 and a control unit 8, the outputs of which are connected to the inputs of the display unit 9. The control and inhibit outputs of the memory block 7 are connected respectively to the control and inhibit inputs of the control block 8. The memory block 7 contains the triggers 10, the elements OR 11, -12, the block 13 of the pulse edge selection and the block reset 14. Inputs Install About the trigger 10 are combined and connected to the output of the first element OR 11, one of the inputs of which is connected to input 1 corresponding trigger 10, K which is connected to the first input of the second element OR 12, the output of the reset unit 14 is connected to the second input of the second element OR 11 and the output of the pulse edge selector 13 is connected to the third input of the second element OR 12, and the third input of the first element OR 11 is the Reset input of the storage unit 7. The device works as follows. The received information sequence is fed through the input matching unit 1 to analyzer 2, which detects erroneously received signal elements and generates error pulses that arrive at the input of counter 3. When the first error impulse arrives at the input of the counter 3, Sial O comes to the control entry of block 4 account resolution. When a pulse arrives from the output of the counter 3, informing about the occurrence of the first error / unit 4, the allowed count allows clock counting by counter 5 and the pulses begin to advance along counter 5. Simultaneously with the resolution of the count, the control pulse arrives at the reset input of the error rate determination unit b, transfer through the element OR 1G triggers 10 to the state O. When a pulse appears at the output of the counter 5, the triggers 10 are set to from state 1 and to the first input of the element OR 11, 12 a potential 1 is applied, and the second input of each element OR 11, 12 receives the potential 1 from the inverse output of the corresponding trigger 10. The elements OR 11, 12 are sequentially prepared for issuing a signal to the display unit 9. IF a second pulse appears at the output of the analyzer 2, it rewrites O from the output of the counter 3 through the memory block 7 to the corresponding input of the control unit 8, allowing appearance of impulse on so The corresponding input of the display unit 9. The potential transfer from 1 to O, which arrives when a second error signal is issued from the output of counter 3 to the enabling input of the error rate determination unit b, also goes to the pulse edge extractor 13. The impulse impulse passes through the OR 12 element to the output of the error coefficient determination unit 6 and transfers the counting permission unit 4 to the state prohibiting the counting of pulses by the counter 5. At the same time, this signal resets the counter 3 to its original state, preparing it to receive the new error impulse. The described device allows continuous monitoring of the state of the communication channel in discrete information transmission systems in systems having different transmission rates, as well as remembering the lowest error rate in the communication channel. Claims. 1. A device for the operative control of communication channels, containing successively connected input coaxial unit, input pulse analyzer and error counter, that, in order to improve the control accuracy, an account resolution unit, an impulse counter, are introduced into it and an error rate determination unit, the control output of the error counter is connected to the error determination unit, allowing the output through a sequentially connected counting resolution unit and a clock counter, to another input orogo filed clock pulses, - to the information input error rate determining unit, an output of which is connected to the inputs and reset error counter plaque ka authorization account and authorizing the error counter output is also connected to the enabling input sshibok coefficient determining unit, 2. The device according to claim 1, characterized in that the error rate determination unit comprises a memory unit, a control unit, the outputs of which are connected to the inputs of the display unit, the control and prohibitory outputs of the memory unit are connected respectively to the control and inhibit inputs of the unit management 3. The device according to claim 2, characterized in that the memory block contains triggers, OR elements, a pulse edge selection block and a reset unit, inputs of installation O, triggers are combined and connected to the code of the first OR element, to one of the inputs of which the input is connected Installation 1 of the corresponding trigger, to which the first input of the second OR element is connected, to the second input of which and to the second input of the first element OR the output of the Reset Unit is connected, to the third input of the second element OR the output of the pulse edge selector is connected, and This input of the first element OR is the input of the Memory Block Reset. Tpktnohie