SU1148116A1 - Polyinput counting device - Google Patents

Abstract

1. A MULTI-INPUTED ACCOUNT DEVICE containing a counter, the discharge outputs of which are connected to the device outputs, and the zero input is connected to the device zero input, so that, in order to improve speed, entered the register and code comparison block, the output of which is connected to the counting input of the counter, the output is equal to the code comparison block connected to the register input, the zeroing echo of which is connected to the input of the device street, the register outputs are connected to the corresponding first m inputs of blocks of comparison of codes, the second inputs of which bitwise connected to respective data inputs of the register and the counting inputs of multi-input counting device. 2. The device according to claim 1, wherein the counter is made decimal.

Description

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The invention relates to a pulse technique and can be used in measuring, computing, and control devices for counting the total number of pulses from several channels.

A multi-input counting device is known, comprising a channel polling unit and a counter, the bit outputs of which are outputs of a multiple input counting device 1J.

However, this counting device is characterized by great complexity and insufficient speed. To ensure the normal functioning of such a counter, a sequential polling of channels is conducted, which reduces the speed. In addition, the change in the state of this counter does not occur at the moment when the signals at the inputs appear, but when there is a polling signal.

It is also known to have a multi-input counting device containing a counter, the discharge outputs of which are connected to the outputs of the counting device, and the zero input is connected to the zero input of the multi-input counting device C23.

However, this device is also characterized by a lack of speed due to the successive polling of the counting channels.

The purpose of the invention is to increase the speed of action.

The goal is achieved by the fact that in a multi-input counting device containing a counter, the bit outputs of which are connected to the device outputs, and the zeroing input is connected to the device zeroing input, a register is entered and a code comparison unit, the Output More connected to the counter counting input, is Equal to the code comparison unit is connected to the register clock input, the zero input of which is connected to the device zero input, register outputs are bitwise connected to the corresponding first inputs of the code comparison block, The second inputs of which are bitwise connected to the corresponding information inputs of the register and the counting inputs of the multi-input counting device.

Moreover, the counter is made decimal.

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The drawing shows a schematic diagram of a multi-input counting device.

A multi-input counting device 5 contains a counter 1, the bit outputs of which are connected to outputs 2 of a counting device, and the zero input is connected to the device zero input 3, register 4 and code comparison block 5, the Output More than which is connected to the clock input of register 4, whose reset input connected to the input 3 reset multiple input from the counting device. The outputs of register 15 P are connected to the corresponding first inputs of the comparison unit 5, the second inputs of which are connected to the corresponding information inputs of the register 4 and the inputs 6 of the multi-input counting device. As a code comparison block, an element is provided that compares two multi-bit words (A

5 and B).

Multi-input counting device operates as follows.

If it is necessary to set the zero state at the output 2 to 0, the input 3 of the zeroing of the Counting device serves a single pulse. At the initial moment of time, the codes of the numbers A and B are equal. At output A B of block 5, the comparison of co5 Dov is high logic level, and at output A B of block 5 comparison of codes a low logic level. Upon receipt of input pulses on the counting, 6 entered, block 5 of the code comparison compares the codes of two numbers A and B, the code of the number A corresponds to a combination of the input pulses, and the code of the number B at the initial moment of time is 0. Since the numbers A and B are not equal between myself, i.e. , then a high logic level appears at the output of code comparison block 5, and at the output of AB code comparison code block

0 a low logic level appears and the code of the number A is written to the register 4. The codes of the numbers A and B become equal and at the output A of the block 5 of the code comparison appears

5 low logic level, and the output AB of the block 5 comparison codes. high logic level is set again. Single impulse

from the output A of block 5, the comparison of the codes enters the counting input of the counter 1 and increases its content by +1. If the code at input 6 of block 5 comparison codes becomes less than the previous value, i.e. the code at the output of register 4, then the logic level at the output A of block 5 comparing codes from high becomes low and the new code value is written to register 4. The codes of numbers A and B are compared and the logic level at output b of block 5 comparing codes compare again high. The logic level at the output A of block 5 of the code comparison of its state does not change, i.e. a single pulse arrives at the counting input of the counter t only if the code at counting input 6 becomes greater than its previous value, which corresponds to a change in state No counter on the leading edge of the input pulses. In the future, the operation of the counting device is similar.

Thus, the counter of a multi-input counting device accumulates a CmMarnar number equal to the number of C-pulses arriving at the counting inputs, and the response of the ttrois counter is at the moment when the next input has a pulse.

The simultaneous presence of pulses at several counting inputs of the device does not interfere with its operation. It only needs that (&) 1 leading edges of pulses at different counting inputs were separated by a time equal to or greater than the double delay time in the code comparison unit and the delay in the register.

The technical and economic effect of using the invention is to increase the speed of the device, which is achieved by the possibility of the counter to be triggered directly at the moment of receipt of the next input pulse.

Claims (2)

1. MULTI-OUTPUT ACCOUNT DEVICE containing a counter, the discharge outputs of which are connected to the outputs of the device, and the zeroing input is connected to the zeroing input of the device, characterized in that, in order to improve performance, a register and a code comparison unit are entered into it, output More which is connected to the counter counter input, the output is equal to the code comparison unit connected to the register clock input, the zeroing input of which is connected to the device zeroing input, the register outputs are bitwise connected to the corresponding first inputs b a code comparison lock, the second inputs of which are bitwise connected to the corresponding information inputs of the register and the counting inputs of a multi-input counting device. 2. The device according to π. 1, the difference is that the counter is in decimal. 1 1148116