SU1723656A1 - Programmed delay line - Google Patents

Abstract

The invention relates to radio engineering and can be used to simulate the signals of multichannel systems for the exchange of discrete information. The goal is to expand the field of application by providing a change in the voltage levels of the programmable elements of the binary coding delayed signal. The goal in a programmable delay line is achieved by the fact that, in parallel with a delayed signal, additional noise pulses are generated with a duration equal to. The invention relates to a pulse technique and is intended to construct devices for simulating signals of multi-channel discrete information exchange systems. The aim of the invention is to expand the scope by providing changes in the voltage levels of the programmable elements of the binary signal coding. the duration of the individual elements of the delayed signal, and the phase determined by the input bit delay code and the zero current word read address are divided by the pulse frequency with the controlled coefficient specified by the input pulse duty cycle code, after which the modulo noise pulses are summed delayed signal, for which two shift recorders, a multiplexer, two D-flip-flops, an EXCLUSIVE OR element and a multiplexer control unit 4, a D-flip-flop, two code-time interval and de pulse frequency converter. In addition, the programmable delay line contains input and output buses, an operational storage unit, two buffer registers, and the control unit contains a clock pulse generator, a pulse distributor, a driver for controlling pulses, a multiplexer, a counter for current write addresses, a counter for current read addresses . 2 Il. CO with FIG. 1 is a block diagram of a programmable delay line; in fig. 2 - time diagrams that show her work. The programmable delay line contains the first shift register 1, the first input bus 2, the first buffer register 3, the control unit 4, the operational storage unit 5 (RAM), the second buffer register 6, the shift register 7, multiplexer 8, VJ o with Os sl Os

Description

the first and second D-flip-flops 9, 10, the EXCLUSIVE OR 11 element, the first and second output buses 12, 13, the second input - discharge bus 14, the third synchronization input bus 15, the clock generator 16, the pulse distributor 17, the control driver 18 pulses, first multiplexer 19 of control unit 4, counter 20 current write addresses, counter 21 current readout addresses, D-flip-flop 22 of control block 4, first and second converters 23, 24 time-code interval, frequency divider 25, fourth input a- discharge bus 26, fifth in the discharge w At 27, the sixth input d-bit bus 28, the seventh input g-bit bus 29, and the control unit 4 has eight inputs 29-36 and the second multiplexer 37. In this case, the control unit 4 includes a series connected clock generator 16 clock pulses, the distributor 17 pulses and a control pulse shaper 18 and the first output 29 are connected to the first input of the first buffer register 3, the first input bus 2 is connected to the input of the first shift register 1, whose outputs are through the second buffer register 6, the operational storage unit 5, the first buffer th register 3, the second shift register 7 is connected to the input of multiplexer 8. A group of b-inputs of multiplexer 8 is connected to the second input b-bit bus 14, and the output is connected to the D-input of the first D-flip-flop 9, the output of which is connected with the first output bus 12 and the first input of the EXCLUSIVE OR element 11. The output of the element 11 is connected to the D input of the second D-flip-flop 10 connected to the second output bus 13. The output of the generator 16 clock pulses, a group of m outputs of the first multiplexer 19 and an output frequency divider 25 are outputs 30-36 with the second th to eighth control unit 4, respectively. The second input of the pulse distributor 17 is connected to the third synchronization input bus 15 and the first inputs of counters 21, 22 of the current write and read addresses, the second group from the b inputs of the second multiplexer 37 is connected to the second input b-bit 37, and its gate input is D-input of D-flip-flop 22. The second input of D-flip-flop 22 is connected to the output of multiplexer 37 and the first input of the first converter 23 is a code time interval, and the C input is connected to the output of counter 20 of the current read address. The group of A-inputs of counter 20 is connected to a-bit d-th fourth input bus 26, counting

the inputs of counters 20, 21 of the current write and read addresses are connected to the third output of control unit 4 and the control input of the first multiplexer 19, the first

and the second group of m inputs of which are connected to the output groups of the counter 20,21 current write and read addresses, respectively, and the group of m outputs of the multiplexer is the seventh output 35

0 block 4 controls. The second input of the first and the first input of the second converter 23, 24 of the code-time interval is connected to the second input 30 of the control unit 4, and the output of the first converter 23

5 code-time interval is connected directly to the first input of the frequency divider 25, the second input of which is connected to the output of the second code-time converter 24, the second input of which

0 is connected to the first input of frequency divider 25.

Ng FIG. 2, a-e, the time t is plotted on the abscissa axis, and the voltage on the outputs 30, 31, 34, 33, 29, 32 of the control unit 4, respectively, is plotted on the ordinate axis.

The operation of the programmable delay line is as follows.

Information input 2 receives an input discrete binary signal, for example, in the form of periodic coded parcels, each of which contains K elements of equal duration, taking one of two logical values O or 1, which correspond to low and

5 high voltage levels of 0-0.5 and 2.5-5.0 V. The elements of each parcel take values, for example, in accordance with the M-sequence. The beginning of each parcel is set, i.e. coincides with

0 by the front of the sync pulse entering the sync input bus 15, and the duration information by a coded control signal of the duration of the parcel fed to the input bus 27.

5 To the control input buses 26 and 14, an encoded binary delay signal is applied, having (a + b) the number of bits, where b is the number of lower bits; a is the number of high order delay codes that

0 encode in binary code the number of bits and delay words ..

This (a +. B) -digit delay code sets the time for which the input information signal should be delayed,

5 issued to the output from the first information output 12, and without changing its structure. The signal appearing on the output bus 13 must be delayed by the same amount, but its structure is changed so that certain elements of each code message have opposite values of the input signal on the input bus 2 and the delayed signal on the output bus 12 i.e. inverted. This operation simulates the effect of noise in the reception and transmission of discrete information. It can be used, for example, when checking frame alignment devices in discrete information exchange systems under conditions that are as close as possible to real ones when there are interferences in the transmission-reception channel that distort the transmitted codes. In these devices, the detection (convolution) of the received code is performed using a discrete filter (DF) containing a shift register for K bits of the input information, and a comparing device counting the number of matches (mismatches) each bit 0 and 1 of the shift register and reference M-sequence. In the absence of a useful signal, when one noise is received, the comparing device registers about 50% of matches, and when the M-sequence is fully moved in the DF, 100% matches, i.e. the detection threshold is 50%. Practically taking into account the possible distortion of individual elements of this threshold is reduced and may even be variable. The possibility of distorting a certain number of elements of the input delayed signal at the independent output provides verification of the specified detection threshold and allows comparing it with the reference output.

The inversion of certain elements of the input sequence is carried out by summing them modulo 2 with additional pulses, also called to reflect the physical nature of the noise pulses generated by the newly introduced blocks. In this case, the duration of the noise pulses is specified by the duration codes on the input bus 28 with the cost of the lower bit equal to the period of repetition of the clock pulses, as well as the control codes. The elements of the package, the values of which must be reversed, are determined by the control code of the duty cycle of the noise pulses on the input bus 29. As a result, for example, the duty cycle of the noise pulses is 2, i.e. the code on the input bus 29 is equal to this value, every second element changes its value to the opposite, with the convolution of the M-sequence, 50% of matches (mismatches) are recorded in the DF, i.e. sequence

any species is completely destroyed. Using the shift register 1, the information signal coming from the input bus 2 is quantized to obtain information bits and a delay by the time it takes to form words containing n bits. The information shift in the shift register 1 is carried out using clock pulses generated by the generator 16 clock

0 pulses of control unit 4 (Fig. 2, a). The repetition period T of the pulse generator of the 16 clock pulses is selected from the condition of providing the necessary precision of quantization of the input signal and, as a minimum, must be less than the length of the individual code element of the input burst. At times when the shift register 1 is in steady state, the signal from its information outputs

0 in the form of n-bit words is rewritten into buffer register 6, from the outputs of which is fed to the information input DO of writing information into the RAM 5. RAM 5 is intended for recording, storing, and reading

5 information in the form of n-bits. Accordingly, RAM 5 contains a certain number, for example, M, n-bit memory cells, each of which has its own m-bit address. The value of t is

0 as a logarithm modulo 2 of the input cell duration or the repetition period of the clock pulses on the input bus 15 divided by T. The RAM 5 is operated by write-read cycles with a period of 5 repetitions of T. in accordance with the control signals generated by the driver 18 control pulses. The repetition period of these pulses, as well as their temporary position during

0 of each operation cycle of RAM 5 are set by the output pulses of the distributor 17 pulses, having a repetition period T, a duration of 0.5 T and shifted relative to each other by the value T. On

The 5 inputs of the distributor 17 are supplied with the clock pulses of the generator 16, the information D-inputs are given a zero code (O power), and the input of the information input is short, with a duration of about T pulses from the input

0 bus 15 sync. When a synchronization pulse arrives, the time code corresponding to the beginning of the input information package on the input bus 2 is entered into the distributor 17, the zero code

5 installed on its information outlets; at the first output of the distributor 17 pulses, for example, a low level corresponding to the output pulse will be set, and on the other n-1 outputs there will be a high level, which corresponds to the absence

pulses. As a result, the operation of the pulse distributor 17 will be synchronized, and then the entire control unit 4, which will form information words with the start of each informational message on the input bus 2. The output pulses of the distributor 17 are used to generate pulses using the control pulse generator 18 with different time arrangements during each word.

FIG. 2 b shows the timing diagrams of the pulses at the output 31 of the control unit 4 used to read information from the shift register 1 into the buffer register 5. The front of these pulses corresponds to the middle of the 8th bit when the information word is formed and the shift register 1 is in steady state , and the decline - the beginning of the 4th bit. Such pulses can be generated using a D-flip-flop, to the R-input of which a 4-bit pulse is fed from the output of the distributor 17, to the C-input - an 8th bit pulse, the D-input is connected to a high voltage level, and the output is the direct output of the D-flip-flop. FIG. 2, the diagrams of the chip selection pulses are presented (output 34 of the control unit 4), which are used to protect the information of the RAM 5 from destruction when overwriting information.

During the operation of these pulses, the signals at address inputs A of RAM 5 should not change. These pulses can also be generated using a D-flip-flop, to the R-input of which a 5th pulse is applied, to the S-input - the 7th pulse, and to the C-input via element 2 OR - the 1st and 2nd impulses. In this case, the D-input of the trigger must be connected to the Q-output, i.e. the trigger must be enabled in counting mode.

FIG. 2, d, the diagrams of the read-write control pulses are shown (output 35 of the control unit 4), and the low level corresponds to the write mode. These pulses, as well as other pulses: reading information from RAM 5 to buffer register 3 (output 29) and parallel writing information to shift register 7 (output 32) - are formed by the same principle using D-flip-flops and OR elements, the number of which with the imaging unit 18 must be equal to 5 - according to the number of outputs.

The current m-bit write and read addresses, the difference in the codes of which the delay value depends, is a multiple of the duration of the word Tn, are formed using counters 20 and 21 pulses, respectively. The counting pulses are pulses from the output 31 of control unit 4, which are also used to switch the write and read addresses using a multiplexer 19. The write address counter 20 is reset to the zero initial state by synchronization pulses from the input bus 15 received at the R input of the counter . Therefore, writing the first word with the information package with the input

0 tires 2 in RAM 5 is always implemented in a cell with a zero address. At the same time, the synchronization pulses from the input bus 15 are fed to the V input of the information input of the counter 21, in which the code is written

5 word delays with a-bit input bus 26. The information Q-outputs of counters 20 and 21 form periodic m-bit codes of the write and read addresses, which are switched by

0 multiplexer 19 and are received (group of outputs 8 of control unit 4) to address inputs A of RAM 5. As a result, after a certain number of periods after the input sequence is received, equal to the code

5 on the input bus 26, a zero code is set in the counter 21, and from RAM 5 to the buffer register 3 the first word for the information bus with the information input sequence on the input bus 2 is read from the RAM clock 15 on the input bus 15. with RAM 5 provides a delay with a discrete word duration, i.e. value p. For

5 of obtaining input information delay in real time, i.e. with a discrete equal to the quantization period on the input bus 2, each word read into the shift register 3 is required, which is carried out using the shift register 7. This register has the number of bits equal to 2.p. The information in the first n bits of register 7 from buffer register 3 is rewritten in parallel using

5 pulses from output 32 of control unit 4 (Fig. 2, e) and pulses from output 30 of control unit 4 at time points corresponding to the front of quantization pulses at the input, advances to the next n bits connected to the x information inputs of the multiplexer 8, to the control V-inputs of which an input, in this case a 3-bit, bit delay code from the input bus 14 is applied, which provides

5, the D-input of D-flip-flop 9 of any of the n most significant bits of register 7 can be connected. By using D-flip-flop 9, whose information output is the first output 12 of the device, the delayed signal is additionally shifted by one T to the delay was equal to the delay of the signal on the output bus 13. From the output of multiplexer 8, the delayed signal in parallel arrives at the first input of the EXCLUSIVE OR element 11, to another input of which noise pulses are generated, generated by the newly introduced elements. These noise pulses are generated in duration using a second code-time interval converter 24, however, operating only during the formation of a single pulse, i.e. during the operation of the first code-time interval converter 35, which is the driver of single pulses with an external trigger. The duration of the pulses generated by the converter 23 is controlled by the discharge code of the duration of the input package on the output bus 27, the price of which the lower bit is T, since the output pulses of the generator 16 are used as the counting pulses. The starting or starting pulse of the converter 23 is generated multiplexer 37 output as follows.

The information X-inputs of multiplexer 37 are supplied with all n number of pulses, the control V-input - the delay bit code from the input bus 14, which selects one of the n bit pulses, and the S-input of the gating - the pulse generated by D- Trigger 22, which selects the first delayed word with the input message.

Since the first information word corresponding to the beginning of the input parcel on the input bus 2 is stored in RAM 5 at the zero address, this is the first word on the output after generating at the output of the counter 21 the current read address of the transfer loan signal when the counter 21 is set to zero code. The negative polarity transfer loan signal is generated at the beginning of the 4th pulse and ends at the front of the 8th pulse (Fig. 2, b), i.e. just before the start of the right word. The D-flip-flop 22 is switched by a positive differential of the pulse and the multiplexer 37 is turned on. In the next word, in accordance with the bit delay code on the input bus 14, the output of the multiplexer 37 passes one of the output pulses of the pulse distributor 17, which returns the R-input D-reset the trigger 22 returns to the initial state, switching off the multiplexer 37, and starts the converter 23, generating a pulse, the duration of which is 2 V.

where is the code on the input bus 27, which determines the duration of the information package (sequence) on the input bus 2. The signal from the output of the converter

23 during the generation of the conversion pulse enables the operation of the controlled converter 24 and the frequency divider 25 with a controlled division factor. Converter output pulses

24 are supplied to the counting input of the pulse frequency divider 25. In this case, the duty cycle code of noise pulses from the input bus must be fed to the information inputs of the frequency divider 25,

and the U1 input of the counting resolution is the output signal of the converter 23, while the output pulse of the frequency divider 25 must be fed to the U2 input of the input of information. As a result, the output pulses of the frequency divider 25 are equal in duration and phase-linked to the sequence elements arriving at the first input of the EXCLUSIVE OR 11 element, to the other input of which

The output pulses of frequency divider 25 are given. Element 11 is a controllable inverter that transmits a signal unchanged at a low level at the second input and inverts a signal at a high

level Therefore, setting one or another code on the input bus 29. It is possible to change the values of the well-defined elements of the input sequence on the output bus 13, on which the signal from the output of element 11 is fed through a D-flip-flop 10, used to equalize the waveform on the output bus 13.

The technical advantage of the proposed programmable delay line

the application area is wider due to providing, in contrast to the known delay devices, an operative change in the values of certain elements of the delayed information signal on the output bus 13, which is necessary for testing multi-channel devices for the exchange of discrete information in real time and conditions simulating the effect noises with different

level in the channels of information exchange.

Ф о рм ул а and з о б р r ete ni and

A programmable delay line containing input and output buses, an operational storage unit, a buffer register, and a control unit, including a series-connected clock generator, a pulse distributor, and a driver

pulses, the first output of which is the first output of the control unit connected to the first register input, and the counter of the current write address, characterized in that, in order to expand the scope of application by providing a change in the voltage levels of the programmable elements of the delayed binary coded signal, second buffer register, two shift registers, a multiplexer, an EXCLUSIVE OR element, two D-flip-flops, the input of the sequential input of information of the first shift register connected to the first input bus, and the group of p outputs of the first shift register through the second buffer register, operational storage unit, the first buffer register, the second shift register is connected to the group of n multiplexer inputs, the second group of which inputs are connected to the second input b-bit bus and the output is connected to the D-input of the first D-flip-flop, the output of which is connected to the first output bus and the first input of the EXCLUSIVE OR element, the output of which is connected to the D-input of the second D-flip-flop connected by the output to the second output bus, The volume of the synchronization inputs of the shift registers and D-flip-flops is connected to the second output of the control unit, the remaining six outputs of which are from the third to the eighth, respectively, are connected to the input of the second buffer register, the first and second inputs and the group and m inputs of the random access memory, and the control unit includes a counter of the current readout address, two multiplexers, a D-flip-flop, two code-time slots and a frequency divider, the output of the clock generator, the outputs from the second to the fifth form the control pulse block, the group of m outputs of the first multiplexer and the output of the frequency divider are outputs from the second to

the eighth control unit, respectively, the second input of the pulse distributor is connected to the third synchronization input bus and the first inputs of the current write and read address counters, the group of n outputs of the pulse distributor is connected to the group of n inputs of the second multiplexer, the second group of b inputs of which are connected to the second the input b-bit bus, and its gate input is connected to the D-trigger of the D-flip-flop, the second input of which is connected to the output of the second multiplexer and the first input of the first converter Code-time

the interval, and the C input is connected to the output of the counter of the current readout address, a group of a inputs of which is connected to the a-fourth fourth input bus, the counting inputs of the counters of the current write addresses and

the reads are connected to the third output of the control unit and the control input of the first multiplexer, the first and second groups of which m inputs are connected to groups of m outputs of current counters

the write and read addresses, respectively, and the group of m outputs is the seventh output of the control unit, the second input of the first and the first input of the second code-time interval are connected to the second output of the control unit, and the group from the first inputs and the group from the d inputs of the second converter the code-time interval is connected to the V-bit fifth and d-bit sixth sixth input buses, respectively, while the output of the first code-time converter is connected directly to the first input of the frequency divider s, the group of g inputs of which is connected to the r-bit seventh input bus, and the second input of the frequency divider is connected to the output of the second converter, the code-time interval, the second input of which is connected to the first input of the frequency divider.

Vw.f

FIG. 2

Claims (1)

Claims A programmable delay line containing input and output buses, a memory block, a buffer register and a control unit including a clock pulse generator, a pulse distributor and a control pulse shaper, the first output of which is the first output of the control unit connected to the first input of the register, and a counter of the current recording address, characterized in that, in order to expand the scope by providing a change in voltage levels of the programmable element of the delayed binary encoded signal, a second buffer register, two shift registers, a multiplexer, an EXCLUSIVE OR element, two D-flip-flops are introduced, while the input of the serial input of the first shift register information is connected to the first input bus, and the group of η outputs of the first shift register is the second buffer register, operational memory unit, the first buffer register, the second shift register is connected to the group of η inputs of the multiplexer, the second group of b inputs of which is connected to the second input b-bit bus, and the output is connected to the D-input of the first D-flip-flop, the output of which is connected to the first output bus and the first input of the EXCLUSIVE OR element, the output of which is connected to the D-input of the second D-flip-flop, connected by the output to the second output bus, the synchronization inputs of the shift registers and D-flip-flops are connected to the second output of the control unit, the remaining six outputs of which, from third to eighth, respectively, are connected to the input of the second buffer register, the first and second inputs and the group and m inputs of RAM about the block, and the counter of the current read address, two multiplexers, a D-flip-flop, two code-time interval converters and a frequency divider, the output of the clock generator, outputs from the second to fifth control pulse shapers, a group of m outputs of the first the multiplexer and the output of the frequency divider are outputs from the second to eighth, respectively, of the control unit, and the second input of the pulse distributor is connected to the third input synchronization bus and the first inputs of the counters the current write and read addresses, a group of η outputs of the pulse distributor is connected to a group of η inputs of the second multiplexer, the second group of b inputs of which is connected to the second input b-bit bus, and its gating input is connected to the D-input of the D-trigger, second the input of which is connected to the output of the second multiplexer and the first input of the first converter is a code-time interval, and the C-input is connected to the output of the counter of the current read address, a group of a inputs of which are connected to the a-bit fourth input bus, the counting inputs of the counters of the current write and read addresses are connected to the third output of the control unit and the control input of the first multiplexer, the first and second groups of m inputs of which are connected to the groups of m outputs of the counters of the current write and read addresses, respectively, and the group of m outputs is the seventh output control unit, the second input of the first and the first input of the second code-time interval converters are connected to the second output of the control unit, and the group of the inputs of the first and the group of d inputs of the second code-time interval of the educators are connected to the in-bit fifth and d-bit sixth input buses, respectively, while the output of the first code-time interval converter is connected directly to the first input of the frequency divider, a group of g inputs of which are connected to the g-bit seventh input bus and the second input of the frequency divider is connected to the output of the second converter code-time interval, the second input of which is connected to the first input of the frequency divider. Figure 1 υυ a / g / 3 4 5 s 7 8 t 0 8-T t 7 0 t g about t .0 d t e 0 i 0 figure 2