SU1597875A1 - Programmable power source - Google Patents

Abstract

The invention relates to secondary power sources of radio equipment. The aim of the invention is to provide a software-time simulation of the voltage fluctuations of the power source, the effects of impulse noise and the accuracy of the installation of a stabilized constant voltage. In comparator 24, the codes are compared with the output of a random access memory (RAM) and counter 23. The signal obtained as a result of the comparison transfers the counter 25 to a new state, which determines the new bus status of the address of the RAM block. The comparison node receives signals from the output of the mixer and the pulse-width modulator (PWM). As a result of the comparison, a code is generated which changes the code at the output of the reversible PWM counter. This results in a change in the division ratio of the frequency divider on the other PWM counter. Ultimately, the voltage at the output of the device changes until it compares with the value specified in the program step stored in RAM. 5 il.

Description

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The invention relates to electrical engineering and can be used to simulate various kinds of interference acting on circuits of stabilized voltage sources during the operation of electronic equipment (REE).

The aim of the invention is to provide a software and time simulation of the MQ voltage source voltage fluctuations, the effects of impulse noise, the accuracy of the installation of a stabilized constant voltage.

Fig, 1 shows a block diagram of the device; in fig. 2 is a block diagram of a display and switching unit (BIC); in fig. 3 - block diagram of the choice of programs (GDP); in fig. 4 is a block diagram

15

In round 14, the value of the bits of the quantities that are first written into the buffer register 16 and then written into RAM 2 is successively typed. When you press any key 14, the debouncing circuit 15 produces a number and pulse code for recording and shifting information in the buffer register 16. Switch 11 in the programming mode (the first inputs and the codes of the switch 22 are closed) passes signals from the output of the buffer register 16 to the inputs of the decoder 12 and the RAM block 2, From the output of the decoder 12, the signals go to the inputs of the indicator 13, what. provides visualization of signal parameters in the current program step (in both modes of operation).

pulse width modulator (PWM); JQ After filling the buffer register

in fig. 5 - block diagram block zgarav- | Leni (BU).

The programmable power supply consists of a BIC 1, an operational memory block (RAM) 2, a digital-to-analog converter (DAC) 3, a comparison node 4, .BVP 5, a low-frequency noise generator 6,; PWM 7, BU 8, 9 high-frequency generator interference, mixer 10 signals.

BIC 1 includes a switch 11, a decoder 12 and an indicator 13.

BVP 5 includes a keyboard 14, a chattering and shaking circuit 15, a buffer register 16, a time interval generator 17.

PWM 7 includes a reversible counter 18, a counter 19 of a frequency divider, an integrator 20.

The control unit 8 includes a pulse generator 21, a switch 22, a time counter 23, a comparator 24 timeslots.

The device operates in two modes: Programming and Operation, the choice of which is determined by the position of the key switch 22 and the signal level at the W / R input of the RAM block 2. In the programming mode, information typed on the keyboard is entered into the cell of the RAM 2, and each cell stores codes of the amplitude of the stabilized direct voltage, the time of its output, the amplitudes and frequencies of the signals of low-frequency and high-frequency interference superimposed on the constant voltage. To write the codes of these quantities on the keyboard

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when the control key of the keyboard 14 is pressed, a signal is received from it to the input of the time delay generator 17 BBC. The write strobe from the output of the latter rewrites information from buffer register 16 to input 1 in RAM cell 2 with the address typed in buffer register 16 or the address counter 25. According to the signal from the third output of the keyboard 14, the address code from the output of the register 16 records C in the counter 25 of the address BU 8.

All device counters are reset by a signal from the Reset line.

In the Operation mode, the circuit opens the pair of contacts and closes the second pair of contacts of the switch 22. The generator 21 is connected to the counting inputs of counters 18, 19, 23. The pulses from the output of the generator 21 change the state of these counters. The code from the output of the counter 23 is fed to the first information inputs of the comparator 24, on the second information inputs of which there is a code of bits from the output D, the cell of the 2 RAM unit. These bits define the duration of the task for the output of a stabilized DC voltage device with low and high frequency interference imposed on it, i.e. time intervals t.

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etc. - the duration of the program execution step is determined by the combination of signals C. Output D, RAM 2, coinciding with the content of the corresponding bits of the cell of RAM 2, whose address coincides with the interval number

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In round 14, the value of the bits of the values that are first written into the buffer register 16 and then written into RAM 2 is sequentially entered. When you press any key 14, the debouncing circuit 15 generates a code for the number and pulse for recording and shifting information in the buffer register 16. Switch 11 the programming mode (the first inputs and the codes of the switch 22 are closed) passes the signals from the output of the buffer register 16 to the inputs of the decoder 12 and the RAM unit 2. From the output of the decoder 12, the signals arrive at the inputs of the indicator 13, which. provides visualization of signal parameters in the current program step (in both modes of operation).

Q After filling the buffer register

Q After filling the buffer register

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when the control key of the keyboard 14 is pressed, it receives a write signal to the input of the time delay generator 17 BVC. The write strobe from the output of the latter rewrites information from buffer register 16 to input 1 in RAM cell 2 with the address typed in buffer register 16 or the address counter 25. By the signal from the third output of the keyboard 14, the code of the address from the output of the register 16 is recorded in the counter 25 of the address of the control unit 8.

All device counters are reset by a signal from the Reset line.

In Operation mode, the first pair of contacts is opened and the second pair of contacts of the switch 22 is closed. The generator 21 is connected to the counting inputs of counters 18, 19, 23. The pulses from the output of the generator 21 change the state of these counters. The code from the output of the counter 23 is fed to the first information inputs of the comparator 24, on the second information inputs of which there is a code of bits from the output D, the cell of the 2 RAM unit. These bits define the duration of the task for the output of a stabilized DC voltage device with low and high frequency interference imposed on it, i.e. time intervals t.

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etc. - the duration of the program execution step is determined by the combination of signals C. Output D, RAM 2, coinciding with the content of the corresponding bits of the cell of RAM 2, whose address coincides with the slot number. The amplitude of the signal U is controlled by the bits of the same cell, connected to the second output (DJ) of the RAM block 2.

The signals at the third and fourth outputs (DJ and D) set the amplitude and frequency of the low and high frequency noise superimposed on the main stabilized voltage. For example, for the time interval t- - t, the amplitude of the main signal L. The signal interference from the generator 6 low-frequency interference has an amplitude and frequency Um, f, respectively. The effect of high-frequency interference from the generator 9 in the interval - t. The combined effect of low and high frequency interference on the main signal is illustrated in the interval t d - t.

To provide a predetermined time diagram, comparator 24 compares time slot codes stored in RAM unit 2 and counted in counter 23. When they coincide, a voltage drop is generated at the output of the comparator 24 (from logic level 1 to logical O level). This difference enters the input of the counter 23 of the address and transfers it to a new state. The code at the output of the counter 25 determines the new bus status of the address (L) of the RAM 2 unit, and therefore, at the input of the comparator 24, a new code value of the next voltage duration at the device output appears. From the second outputs of the RAM block 2, the value of the voltage-stabilized code is fed to the input of the DAC 3. The analog voltage from the output of the DAC 3 is fed to the first input of the mixer 10. At its second and third inputs there are signals of low and high frequency interference. The signal from the output of the mixer 10 is fed to the first input of the comparison node 4, the second input of which receives the voltage from the output of PWM 7. At the comparison node 4, the relationship between the voltages from the outputs of the mixer 10 and the output of PWM 7 is analyzed. Depending on the comparison results the output of node 4 produces a two-bit code having the following meanings: 00 — saves the unchanged code of the counter 18, blocks the pulse count from the generator of 21 pulses, and the combinations 01 and 10 result in the summation or subtraction of pulses in a reversible

the estimator 18. A change in the code at the output of the counter 18 changes the division ratio of the frequency divider at the counter 19, thereby changing the severity of the pulses fed to the input of the integrator 20, therefore, the voltage at the output of the device changes until it compares with specified in the program step stored in - RAM 2.

The frequency and amplitude of the interference are determined by digital codes at the inputs of the generators 6 and 9, coming from the outputs 2 and 3 of the RAM block 2. The device operates cyclically. After the addresses are exhausted from the output of the counter of 25 addresses of the cells of the RAM block 2, recalculation starts from zero address, etc. The parameters of the signals of each step of the program are displayed in display unit 1.

Starting the circuit and setting it in the initial state is performed by applying an external signal via the Reset line.

Claims (1)

Invention Formula A programmable power supply containing a voltage regulator connected between the input and output pins, a comparison node, one input of which is connected to the output pins and the other to the output of the reference voltage source, the output of the comparison node is connected to the control input of the voltage regulator characterized by the fact that, in order to provide a software-time simulation fluctuations in the voltage of the power source, the effects of impulse noise, the accuracy of the installation of a stabilized constant voltage, the indication and switching unit has been introduced into it, random access memory and control unit, and the voltage source is made in the form of a mixer, a digital-to-analog converter, a low-frequency noise generator and a high-frequency interference generator, the control unit consisting of a clock generator, a switch, a time counter, a time interval comparator and an address counter, the output of the clock frequency generator is connected to the counting input of the time counter through the first contacts of the switch, the setup input of which is connected to the bus. , output the time counter is connected to the first input of the time interval comparator, another input of which is connected to the output of time slot codes of the operational memory, and the output of the specified comparator is connected to the C input of the address counter, whose R input is connected to the Reset bus; the first output of the input block of programs; and the installation D-input of the address counter is connected to the corresponding information output of the program input unit, the indication and switching unit consists of a switch, a decoder and an indicator, the first, second and third information inputs of the switch are connected respectively to the information output of the random access memory, the output of the address counter the control unit and the information output of the program input unit; the control input of the switch is connected to the second contacts of the control unit switch; through the descrambler connected to the input of the indicator and directly to the information inputs of the operative storage device, the control input of which is connected to the output of the time delay of the program input block 0 five Jq 25 thirty the memory devices, respectively, of the amplitude and frequency frequencies of high-frequency and low-frequency interference, are connected to the inputs of the high-frequency and low-frequency interference generators, the information outputs of the stabilized constant voltage code are connected to the inputs of the digital-to-analog converter, the output of the latter is connected to the first input of the mixer, the second and third inputs of which connected to the outputs of the generators of high-frequency and low-frequency interference, respectively, the output of the mixer is the output of the reference source n april, voltage regulator is made in the form of connected reversible counter, frequency divider counter and integrator, the output of which is connected to output pins, counter input of frequency divider is connected to counter input of time counter of control unit, control input - with output of frequency counter counter and the counting input of the reversible counter, the setup input of the counter of the frequency divider is connected to the Reset bus, the clock inputs of the increase and decrease of the counting of the reversible counter are connected to the corresponding outputs Dami node comparison. u to vmdu v address counter jtefr At the hunting ground of 7vAvam cvfmw / ta AA 5Ug517 KSxot / KSffOKu osat FIG. 3