SU1529402A1 - Digital frequency synthesizer - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to expand the range of output frequencies. The digital frequency synthesizer contains a clock Mr. 1, two registers 2.3 frequency codes, a cumulative adder 4, a combination adder 5, a code converter (PC) 7, a DAC 8, a low pass filter 12. To achieve the goal, memory register 6, PC 9, DAC 10 and analog multiplexer 11 are entered, while the output code of the register 2 K ₁ and the output code of the register 3 K ₂ are in the ratio K ₁ / K ₂ = 2. The content in adder 4 and in register 6 is interpreted as codes of two phases of the synthesized signal, which are converted by PC 7, 9 and DAC 8, 10 into two discrete values of the synthesized signal. When a frequency code of 2 K is set in register 2 and the number of bits of adder 4 and register 6 is equal to N, the signal is generated by 2 ^N / K discrete values, which allows to double the range of synthesized frequencies at a constant frequency. 1 il.

Description

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The invention relates to radio engineering and can be used in radio transmitting and receiving devices.

The purpose of the invention is to expand the range of output frequencies.

The drawing shows an electrical structural diagram of a digital frequency synthesizer.

The digital frequency synthesizer contains a clock generator 1, the first 2 and second 3 registers of the frequency code, a cumulative adder (NS) 4, a combinational adder (CS) 5, a memory register 6, the first converter 7 codes, the first digital-to-digital converter (DAC) 8, the second converter has 9 codes, the second DAC 10, the analog multiplexer 11 and the low pass filter 12.

Digital frequency synthesizer works as follows.

The code of the synthesized frequency is simultaneously recorded in the first 2 and second 3 registers, while in the first register 2 the value 2K is recorded, which determines the frequency of the synthesized signal, and in the second register 3 - the CNS 4 by the value K. Content in HC 4 and in register The 6 memories are interpreted as codes of the two values of the phases of the synthesized signal, which are converted by means of the appropriate converters 7 and 9 of the codes and the DAC 8 and 10 into two discrete values of the synthesized signal.

The input of the filter 12 via analog multiplexer 11 is periodically alternately connected to the outputs of the D / A converters 8 and 10.

When specifying a frequency code of 2K in the first register 2 and the number of bits A and register 6 of memory equal to n, the signal is generated by 2 / K discrete values, which doubles the range of synthesized frequencies at a constant clock frequency .

Claims (1)

Invention Formula A digital frequency synthesizer containing serially connected first frequency code register, cumulative adder, first transform 40 guise less than (k). The clock generator of codes and the first digital-analogue generator 1 form at its output a periodic sequence of square pulses of FO frequency with a duty cycle equal to two. With the arrival of the front of each clock pulse, the content of HC 4 is increased by the value of 2K, and the register 6 through CS 5 records the number that is the sum of the content of the HC. 4 in the previous summation cycle with the value K. If at the initial moment in the register 6 of memory and in the NA there were arbitrary numbers и and р, then with the arrival of the first clock pulse the contents of the NA 4 are equal to p + K, and in the register of memory 6 - + TO. The arrival of the second clock pulse increases the content of HC 4 by .2K, forming the value of ft + K, and the number i + LC, etc., is recorded in memory register b. Thus, the accumulation rate in NA 4 and in memory register 6 is the same. and is 2K Fg. At the same time, at any time the contents of memory register 6 are less than A second converter, serially connected second frequency code register and combinational adder, the second input of which is connected to the output of a cumulative adder, a low-pass filter and a clock oscillator, the output of which is connected to the clock input of a cumulative adder, which is designed to extend the output frequencies, between the output of the combinational adder and the input of the low-pass filter, the serially connected memory register is entered, the second predator is 5 the code generator, the second digital-analogue terminal the equalizer and analog multiplexer, the second input of which is connected to the output of the first digital-analog converter, the control input of the analog multiplexer and the clock input of the memory register are connected to the output of the clock generator, and the output code of the first register of frequency codes K, and the output code of the second register frequency code 50 55 Kj is a ratio of 2. code reader and first digital analog A second converter, serially connected to the second frequency code register and combinational adder, the second input of which is connected to the output of the accumulative adder, a low-pass filter and a clock oscillator, the output of which is connected to the clock input of the accumulative adder, which is output frequencies, between the output of the combinational adder and the input of the low-pass filter, the serially connected memory register, the second code converter, the second digital-analog converter are entered The former and the analog multiplexer, the second input of which is connected to the output of the first digital-analog converter, the control input of the analog multiplexer and the clock input of the memory register are connected to the output of the clock generator, and the output code of the first register of frequency codes K, and the output code of the second register code frequencies Kj is a ratio of 2.