SU1425863A1 - Device for receiving relative bi-pulsed signal - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to increase the reliability of reception and reduce the time of entry into synchronism. The device contains a latch of 1 transitions, an allocator of 2 clock frequency, a driver (F) 3 pulses, a divider 4 frequencies, el-And 5-7 and 17, triggers 8-10, F 11 threshold level, a decoder 12 and 16 signals, an NOT 13, F 14 signal ;, a shift register 15, a diode 18 and a resistor 19. To eliminate cases of false synchronization, an analysis is made of the frequency of occurrence of responses from the output of the decoder 16 using triggers 8 and 9, F 11, and El 17 and a series-connected diode 18 and resistor 19. 2 Il.

Description

4 N9 SP

00

about

00

The invention relates to telecommunications and can be used in the receiving equipment of the main digital 1 analog channel.

The purpose of the invention is to increase the reliability of reception and reduce the time of entry into synchronism.

Figure 1 shows a structural electrical circuit of the proposed device; figure 2 - timing diagram.

The device for receiving the relative bi-pulse signal contains latch 1 transitions, a selector 2 clocks, shaper 3 pulses, divider 4 frequencies, first 5 and second 6, third 7 elements And, first 8, second 9 and third 10 triggers, shaper 11 threshold level, the first signal decoder 12, the element NOT 13, the signal conditioner 14, the shift register 15, the second signal decoder 16, the fourth element AND 17, the diode 18 and the resistor 19.

A threshold level driver 11 comprises first 20 and second 21 resistors, a diode 22 and a capacitor 23,

The device works as follows.

The input of latch 1 of the transitions receives a relative bi-pulse signal (Fig. 2a), which is a composition of three signals: informational, clock, and octet, the transmission of which eliminates clock transitions (indicated by arrows in Fig. 2a). At the output of the latch 1 of the transitions, narrow pulses are generated at the site of all transitions of the input signal (Fig. 26). A clock frequency splitter 2 generates a harmonic oscillation, synchronous and in-phase with the instants of signal transitions, the amplitude of this oscillation coinciding in time with the instants of signal transitions, and the frequencies of this oscillation are equal to twice the frequency of the received signal. The pulse shaper 3 generates from a harmonic oscillation a sequence of square pulses with a duty cycle 2, the fronts of which coincide with the zero crossing of the harmonic oscillation (Fig. 2c). The signal conditioner 14 serves to expand the short pulses received at the output of latch 1 of the transitions. Ras0

five

0

five

0

five

0

five

0

five

The wide pulses from the output of the form 1 of the signal 14 (FIG. 2d) are fed to the shift register 15, in which the serial code is converted into parallel, i.e. A number of signals are generated according to the diagrams (Figure 2d). In these signals, the information symbols and the clock signal alternate bit by bit, which is the preceding sequence of units in which the octet signal replaces the single bit by zero, i.e. the clock signal is a sequence of the form 11 ... 11011 ... 110.

The second signal decoder 16 is designed to generate responses that appear every time as a combination of 11 ... 110 appears in its input signal. At the same time, the number of cells of the shift register 16 must be twice the length (number of bits) of the combination to be decoded, since the inputs of the signal decoder 16 must be connected to the outputs of the shift register cells 16 with only even (or only odd) numbers.

In these diagrams, the sequence of responses from the output of the second signal decoder 16 is shown in Figure 2e. The moments of occurrence of these responses coincide with the moments of transmission of the octet signal.

At the same time, a sequence of pulses from the output of the imaging unit of 3 pulses passes through the second element I 6 to the input of the 4 frequency divider, the division factor of which is equal to twice the number of bits of the combination to be decoded. For the case of deciphering an eight-bit combination of the type 11111110, the division factor of the divider 4 frequency is equal to 16 and the sequence of diagrams at its outputs is shown in FIG. 2g, h. The first signal decoder 12 injects narrow pulses (Fig; 2i), the repetition period of such signals coincides with the period of the decrypted combination. In the synchronization mode or when the true synchronization signal is detected (the combination to be decoded), the positive edge (Fig. 2i) is located inside the pulse in the diagram (Fig. 2e).

When entering synchronism, this condition is not met.

The process of the occurrence of n with nhr1. -1ncism is illustrated in the left part (Fig. 2b-1). To the first {and the first response from the output of the second depp-grater of 16 cis, the 4 frequency divider is inhibited by the blocking voltage t: the output of the third element And 7, since in this case there is a single level on all three inputs. With this, the pulses from the output of the pulse shaper 3 do not pass through the second element AND 6. With the appearance of the first response from the output of the second signal decoder 16, the blocking voltage from the output of the third element And 7 is removed and a pulse sequence begins to arrive at the input of the 4th frequency divider. At the end of the division, a negative pulse occurs at the output of the first decoder 12 of the signal, which, having passed through the element NOT 13, causes the appearance of a blocking voltage at the output of the third element I 7, which, however, after a short time (1/4 of the clock frequency) removed by the rise of the next regular response from the output of the second signal decoder 16 (FIG. 2L). With this, the clock sequence passes through the second element AND 6 and the divider 4 frequencies and the next cycle starts counting. Thus, when a synchronizing signal is detected, the moments of the appearance of pulses from both signal decoders coincide.

To eliminate cases of false synchronization, an analysis is made of the frequency of occurrence of responses from the output of the second signal decoder 16 using the first 8 and second 9 triggers, the threshold level generating unit 11, the fourth And 17 terminal and the series-connected diode 18 and resistor 19.

At the initial moment, the voltage at the output of the shaper 11 of the threshold level is close to zero, at the inverse output of the second flip-flop 9 a single level is maintained, and through a resistor 19, a diode 18 and an open fourth element And 17 the discharge of the capacitor 23 of the shaper 11 occurs. horny level The time constant of this bit chain is small. Upon receipt of the first response from the output of the second signal decoder 16, the first trigger 8 is converted to one

0

five

0

five

0

five

0

five

four

; )

H (n: state (fit.2m), the fourth element, And 17 closes. In this case, the capacitor 23 of the fortiroel 11 threshold voltage is charged from the voltage source with a relatively high time constant (fig.2n). The narrow and pulses (Fig. 2i) voltage on the capacitor 23 decreases slightly, and in the next cycle, due to the unchanged state of the first trigger 8, the voltage on the capacitor 23 continues to increase, approaching the threshold level, and after crossing the oriental level with another pulse from the output of the first descrambler of signal torus 12, the second trigger 9 changes its state, in which the unit voltage is set to its direct output. From this point in time, synchronism is considered to be established and the third element And 7 is blocked by a low level from the inverse arm of the second trigger 9 and 1 The 4 frequency divider does not depend on the presence or absence of responses at the output of the second signal decoder 16. In the synchronization state, the quarter-frequency element AND 17 is closed, the capacitor 23 is charged to supply voltages and the discharge of the capacitor 23 is possible only via an open first trigger; ep 8, to the output of which a chain is connected, made up of a diode and a resistor of the driver 11 threshold levels. The time constant of this chain is chosen so that the voltage change on the capacitor 23 from the voltage of the power source to the threshold level occurs after the disappearance of several synchronizing responses (almost 2-5) from the output of the second decoder 16 signal.

After the synchronization is established, the first element I 5 opens and on, the synchronizing output of the device begins to receive an octet (synchronizing) signal, and the blocking voltage is removed from the input of the installation of the third trigger Yu, and an information connection appears at its output (Fig. ). Dp from the delay of the information component in relation to the position of the octet signal during the entire cycle to the information input of the third trigger 10 is enough to connect the signal from

I

Corresponding to the mouth of the island of Istra 15 CSPP a.

Claims (1)

Invention Formula A device for receiving a relative bi-pulse signal, containing a junction latch, the output of which is connected to the pulse generator input through the time frequency selector; the first trigger, the output of which is connected to the form input; the threshold level generator, the output of which is connected to the first input of the second trigger, whose single output connected to the first input of the first element And, the second and third; elements And, a frequency divider, the first output of which is connected to the first input of the third trigger, characterized in that, with the purpose Accepting the reliability of reception and reduction of the acquisition time, the fourth AND element, diode, resistor, the first and second signal depixters, the shift register, the Slider C1 drove, and the NOT element, whose output is connected to the first input of the third AND element, are entered with the second input the first element And with the first input of the fourth element And, the output of which is connected to the cathode of the diode, the anode of which through 36 The resistor is connected to the first input of the second trigger, the second input is connected to the first input of the first trigger, to the input of the NOT element and to the output of the first depfrater signal, the first and second inputs of which are connected to the first and second outputs of the frequency divider , the input of which is connected to B1 of the second element I, whose first input is connected to the output of the pulse former, with the first input of the former and with the first input the shift register, the first output of which is connected to the first input of the second signal decoder and to the second input of the third trigger, the third input of which is connected to the inverse output of the second trigger, to the second input of the fourth element And to the second input of the third element And, the third input of which is connected to the second input of the first trigger and to the output of the second signal decoder, the second input of which is connected to the second output of the shift register, the second input of which is connected to the output of the signal generator, the second the input of which is connected to the output of the fixture of transitions, the output of the third element I is connected to the second input of the second element I. 0 1 1 0 0 1 0 1 1 1 1 1 1 1 1 1 0 I .J tv w I 11 11 I 111 III111 111 I 11111 IlllLJlmgplJIJlllnl “JrJlL-ll.-L-JG ln-Jl hey of JLJ Lll-GL. Lj lt LI X u u JofoioBbiu day and u u