SU1100728A1 - Multichannel number-to-time interval converter - Google Patents

Abstract

A MULTI-CHANNEL CODE DURING TEMPORARY INTERVAL, containing a pulse generator, the input of which is connected to the Start bus, a memory device, the first, second, third and fourth elements AND, characterized in that, in order to increase the speed of the converter, a synchronization trigger, pulse shaper are entered into it shift, shift register, the first and second elements OR, the element NOT, the register of time intervals and the controlled frequency divider whose input is connected to the output of the pulse generator and the input of the a shear pulse shifter whose output is connected to the first input of the first element I, the output of which is connected to the input of the element NOT and c. the first input of the shift register, the second input of which is connected to the output of the controlled frequency divider and the first input of the synchronization trigger, the second input of which is connected to the first input of the first OR element, and the output is connected to the second input of the first OR element, the output of which is connected to the second input of the first element And, while the outputs of the shift register, respectively, are connected to the first and the inputs of the second and third elements AND, the first input of the second OR element and the first input of the first OR element, the second input of which W is connected to the control input of the time interval register, the outputs of which are connected to the corresponding output buses, information inputs C of the output - with the corresponding outputs of the storage device, and installer: primary input - with the input of the storage device and output of the fourth element I, first input which is connected to the output of the element NOT, and the second input - to the output of the second element OR, the second and third inputs are connected to the outputs of the second and third elements respectively. And the second inputs of which are combined. and connected to the bus mode.

Description

The invention relates to a pulsed technique and can be used in particular to form time intervals for the transmission of electric current through electrochemical paper in the output of discrete information by devices with a raster principle of operation. Such devices usually have a comb of electrodes, to which pulses are applied in accordance with the duration of the formed time intervals, as a result of which a trace is left on the paper reflecting the recorded information. A multichannel code converter is known in a time interval containing a pulse generator, pulse counter, switch, AND and OR elements, comparison blocks and number registers by the number of channels, as well as registers of the controlled channel number, time intervals, and control. The counter value common to all channels is compared with the contents of the register in each channel and, if it is equal, the comparison circuit of the corresponding channel generates them: a pulse that changes the state of the corresponding trigger in the time register, thereby fixing the interval m. However, the known converter is characterized by high hardware costs in its implementation. The closest to the invention to the technical essence is a multichannel code converter in a time interval, comprising a pulse generator, whose input is connected to the Start bus, a memory device, a comparator unit, a channel distributor, a reversible counter, And elements and triggers by the number of channels, while the outputs memory devices are connected to the corresponding first inputs of the unit. Comparison, the second inputs of which are connected to the corresponding discharge outputs of the reversible counter, the counting input of which It is connected to (P + O output of the channel distributor, whose input is connected to the output of the pulse generator, and P outputs, respectively, are connected to the address inputs of the storage device and the first inputs of the elements And the second inputs are combined and connected to the output of the comparison unit, and the outputs are respectively connected to the counting inputs of the triggers.The converter forms time intervals | ЛЫ, symmetrical in time with respect to the moment of switching the forward and reverse counting modes of the reversible counter. The disadvantage of this device is low speed, since when the counter is N, the channel distributor must perform a full poll of channels 2 times. The purpose of the invention is to increase the speed of the converter. The goal is achieved by the fact that a multichannel code converter in a time interval that contains a pulse generator, whose input is connected to the Start bus, a memory device, the first, second, third and fourth elements AND, a trigger trigger, a pulse shifter, a shift register, the first and the second element OR, the element NOT, the time interval register and the controlled frequency divider, whose input is connected to the output of the pulse generator and the input of the shift pulse generator, you One of which is connected to the first input of the first element I, the output of which is connected to the input of the element NOT and with the first input of the shift register, the second input of which is connected to the output of the controlled frequency divider and the first input of the synchronization trigger, the second input of which is connected to the first input of the first element OR and the output is connected to the second input of the first OR element, the output of which is connected to the second input of the first element AND, while the outputs of the shift register are respectively connected to the first inputs of the second and third ele And, the first input of the second element OR and the first input of the first element SH, the second input of which is connected to the control & kitsu input of the register of time intervals, the outputs of which are connected to the corresponding output buses, information inputs to the corresponding outputs of the storage device, and the installation input - with the memory input and the output of the fourth element AND, the first input of which is connected to the output of the element NOT, and the second input to the output of the second element OR, the second and third inputs of which correspond GOVERNMENTAL vyhoda- 5 are connected to said second and third AND gates, the second inputs of which are combined and connected to the bus operation. FIG. Figure 1 shows the structured electrical circuit of a multichannel code converter in a time interval; in fig. 2 - diagrams explaining his work. The multichannel code-to-time converter contains a pulse generator 1, the output of which is connected to the input of a controlled frequency divider 2, whose input is connected to the first input of synchronization trigger 3, a pulse shifter 4, the input of which is connected to the output of the pulse generator and the output through the first element 5 is connected to the input of the element 6 and the ne input of the shift register 7, to the second input of which the output of the controlled frequency divider is connected and the outputs of the register through the second and third elements 8 and 9 and not one of the outputs of the shift register 7 is connected to one of the inputs of synchronization trigger 3 and one of the inputs of the second element OR 11, the other input of which is connected to the output of synchronization trigger 3, and the output to the second input of the element AND 5. The output of the second element OR 10 is connected to one of the inputs of the fourth element AND 12, the other input of which is connected to the output of the HE 6 element, and the output to the setup input of the register of time intervals 13 and the memory input (memory) 14, which outputs Go, respectively, are connected to the information inputs of the time interval register, the control input of which is connected to the synchronization trigger 3 output, and the outputs are connected to the corresponding output buses, the second inputs of the second and third elements AND are connected and connected to the bus 13 of the operation mode and the Start-up bus 16 is connected to the input of the pulse generator 1. Positions 17–24 denote the shift register codes 7 in ||

Multichannel code converter in the time interval works as follows.

In the initial state, the synchronization trigger 3 is at zero zero, registers 7 and 13 are zero. The Start signal on bus 16 causes the generator 1 to generate pulses that are fed to a controlled frequency divider 2 and a shift pulse shaper t. The division ratio in the controllable divider 2 is determined by the speed at which the paper is pulled. The speed code is fed to the control inputs of the divider 2, from the output of which the signals (plot a, fig. 2) are fed to the input of synchronization trigger 3 and the first (informational) input D of the shift register 7. The period of these signals corresponds to the advance time of the paper on one line On the leading edge of the signal from the controlled frequency divider 2, the synchronization trigger 3 is set to one: a state whose pulse from the output (plot o, Fig. 2) goes through one of the W 11 11 elements to one of the inputs of the And 5 element, thereby resolving the passage the shift signals from the output of the imaging device 4 to the input of the element NOT 6 "the shift register 7. The first shift pulse in the zero register register 7 is entered into the unit that is fed to the input.). The period of signals from the generator 4 output (plot & Fig. 2) is one conversion quantum, and the fBC duration is 2 times shorter than the length of signals from the code of the controlled divider 2. The converter can operate in two modes: output of binary information (mode TON) and output of half a “discrete information” (HALF-TONE mode). when signal t appears in a zero register de reg register 7, the latter through the element OR 10 is fed to one of the inputs of the element 12, to the other input of which a signal is output from the output of the element 6. The element 12 does form an information reception pulse (plot g, fig 2), which enters the memory 14 and into the time slot register 13, allowing the entry of the lower

bits of brightness codes from the memory 14.

When signal 1 appears at output 18 of register 7, the latter arrives at one of the inputs of the second element I8, to the other input of which 1 flows through the bus of operation mode 15 (corresponding to the HALF-TONE mode). The impulse from the output of the element I8 through the element IL 10 arrives at the element I 12, which forms the impulse to receive information, which is used to write to the register of time intervals 13 average bits of the channel codes.

Similarly, at occurrence of signal 1 at output 20, 13 higher bits of the codes are written into the register.

Thus, the lower bits of the codes will be in register 13 during one shift cycle, the middle ones will be two clocks, the older ones will be four clocks, which is equivalent to the realization of weighting code bits.

Upon the appearance of signal 1 and output 24 (plot a, fig. 2) of register 7, the last input to the input of synchronization trigger 3 sets it to the state O. The potential from the output of the trigger sets to state O all bits of the register of time slots 13. From this moment until the arrival of the next impulse from the output of frequency divider 2, a paper is thrown.

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The unit potential from output 24 of register 7 enters, also, the element OR 11, thereby allowing another shift in register 7, after which the register is zeroed. The device returns to its original state and the formation of a string of half-tone information is completed. The form of time signals generated in channels in this mode for all combinations of a three-digit luminance code is shown on & FIG. 2. When the signal O is received through the mode 15 bus (which corresponds to the TON mode), the information in register 13 will be entered only once by the signal from the output 17 of the shift register 7 and all seven clock cycles stored in register 13 will achieve fixation of units with maximum strength ( plot H, fig. 2).

The technical and economic effect of using a multi-channel code-to-time converter is that, due to the parallel operation of the channels, it has a higher speed. This allows forming time intervals for 300 channels at the same time. At the same time, the converter is implemented through rather small hardware costs, and due to the tight synchronization of operation of all units, the converter also has high reliability of operation.

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Claims (1)

MULTI-CHANNEL CODE CONVERTER IN THE TIME INTERVAL, containing a pulse generator, the input of which is connected to the Start bus '', a storage device, first, second, third and fourth elements And, characterized in that, in order to increase the speed of the converter, a synchronization trigger is introduced into it, shear pulse shaper, shift register, first and second elements OR, NOT element, register of time intervals and controlled frequency divider, the input of which is connected to the output of the pulse generator and the input of the form I shift pulse, the output of which is connected to the first input of the first AND gate whose output is connected to ^one input of the NOR and c. the first input of the shift register, the second input of which is connected to the output of the controlled frequency divider and the first input of the synchronization trigger, the second input of which is connected to the first input of the first OR element, and the output is connected to the second input of the first OR element, the output of which is connected to the second input of the first AND element wherein the outputs of the shift register are respectively connected to the first inputs of the second and third AND elements, the first input of the second OR element and the first input of the first § OR element, the second input of which is connected chen to the control D Valid • Giustra timeslots outputs «δζϋοι t ^on F which are connected to respective vyhodnmi tires, data inputs - with the respective outputs of the memory device, and ustanog: paid-input - to the input memory and the output of the fourth AND gate, a first input which is connected to the output of the element NOT, and the second input to the output of the second OR element, the second and third inputs of which are respectively connected to the outputs of the second and third elements AND, the second inputs of which are combined. enes with the bus operation. 1100728