SU1418903A1 - A-d converter - Google Patents

Abstract

The invention relates to computing and can be used in communication systems with pulse-code modulation. The invention makes it possible to increase the accuracy of the conversion. This is achieved in that an analog-to-digital converter containing a matching amplifier 2, To limiting amplifiers 3, a source 5 of a limiting voltage, a source 6 of a reference bias voltage, To parallel analog-to-digital converters 4, a register 10, a block 16 of delays, introduced (K-1) error correction blocks 7, shift registers 13 and 14, decoders 8 and 12, switch 9. 1 c.p. f-ly, 2 ill.

Description

;;

CX)

About 00

The invention relates to computing and can be used in communication systems with pulse code modulation.

The aim of the invention is to improve the accuracy of the conversion.

FIG. I shows the functional diagram of the converter; Fig.2 functional diagram of the correction unit.

Analog-to-digital converter (Fig. 1) contains an input bus 1, a matching amplifier 2, K amplify

limiters 3, To parallel analog-to-digital converters (ADC) 4, limiting voltage source 5, bias reference voltage source 6, K-1 echo correction blocks 7, decoder 8, switch 9, register 10, output bus 11, decoder 12, shift register 13, shift register 14, clock signal bus 15, block 16 delays.

Each of the K-1 blocks 7 (FIG. 2) contains a shift register 17, a subtraction block 18, a register 19, an addition block 20, a decoder 21, an OR element 22, a shift register 23, an OR element 24, a HE element 25, a decoder 26, register 27 shift.

The device works as follows.

A wideband information signal is sent to the input bus 1 and further to the matching amplifier 2, for example, a television signal. In a matching amplifier, the television signal is amplified, limited to the n spectrum, amplified again and linked to a certain level (for example, at the tops of the clock pulses). the line frequencies necessary for operation can be fed from outside or can be extracted from the television signal at one of the nodes of the matching amplifier 2, from the output of which the television signal goes to the combined first inputs K of the limiting amplifier units 3, in which the signal is amplified, limited on both sides and offset. Gain and offset are needed to match the sweep of the converted signal with the dynamic range of each parallel analog-to-digital converter (ADC) 4. In this case, the range of variation

ten

five

0

five

0

5 about 5

0

five

the converted signal is divided into K equal parts by the number of used parallel ADCs 4. The limiting voltage is generated by source 5. From the outputs To the limiting amplifiers 3, after amplifying, dividing and shifting and limiting, the first inputs of the corresponding parallel ADCs are received by 1 / K of the analog signal span and offset matched with the dynamic range of each parallel ADC 4.

The operation of the parallel A / D converters 4 controls the clock signal. Sampling is performed (comparators are gated) at a certain time interval after the leading edge of the clock pulse. This time interval may be different for different parallel A / D converters 4, which leads to dynamic conversion errors. These differences are compensated by block 16. The voltage from source 6 flows in parallel to second inputs of parallel A / D converters 4, where it is used to form amplitude quantization ranges. At the outputs of each parallel ADC 4, a P-bit parallel binary code is generated.

The pairing of quantization scales of parallel A / D converters 4 is performed by shifting the dynamic ranges of the limiter amplifiers 3.

The device does not have strict requirements for matching the quantization scales of parallel A / D converters 4. When pairing, it is necessary to ensure that the boundary regions of the neighboring quantization scales overlap into several (for example, 3-5) quantization steps. The size of the overlap zone must be large enough so that the effect of various destabilizing factors (for example, climatic conditions) does not lead to the appearance of a gap in the resulting quantizing characteristic of the ADC, due to the disappearance of the overlap zone and the divergence of the quantization keys. On the other hand, an excessive increase in the overlap area will lead to a corresponding decrease in the number of amplitude quantization levels in the resulting quantizing characteristic of the ADC.

The overlap zone is used in the device for the correction of conversion errors.

3.4

From the output of the i-ro parallel ADC, the P-bit code groups arrive at the fourth inputs of the corresponding block 7, the first inputs of which receive the code from the output (il) -ro of block 7. In the iM block 7, the binary code combination is output and stored (i + l) -ro parallel ADC 4 corresponding to the position on its quantization scale the lower limit of the quantization scale i-ro parallel ADC 4 (i.e., the lower limit of the conjugation area of quantization scales i and (i + l) -ro parallel A / D converters 4). This operation is carried out without interrupting the processing of the information signal at times corresponding to an insignificant rate of change of its values, for example, when at least two consecutive samples of the information signal fall into the interface. In this, a signal arriving at the second input of i-ro block 7 from the third output (i + l) -ro of block 7 is used. Logic 1 corresponds to the appearance of the code of the upper limit of the quantization scale (for example, at 8: 11111111) (i + l ) -ro parallel ADC 4, logical O - the absence of such a code. This eliminates the influence of the dynamic component of the conversion error on the accuracy of the correction.

The above binary code combination is then summed with each code combination received from the output of the i-ro parallel ADC 4. The result goes to the first input of the (i- -1) -th block 7 and to the corresponding information input of the switch 9. At the second output i- The ro block 7 generates a logical I signal in the case of the output at the output of the corresponding parallel A1Sh 4 code of the upper limit of its quantization scale and logical O in the absence of the specified above code. The signals from the second outputs of all blocks 7 are fed to the first control inputs of the decoder 8.

From the output of the K-th parallel ADC 4, the P-bit code groups are fed through register 13 to the first input of (K-1) -th block 7 and to the second control input of the switch 9. In (K-1) -m block 7, the code Groups are used to calculate and store a code pattern at the output of the K-th parallel3.

4 ADC, corresponding to the position on its quantization scale, the lower limit of the quantization scale (K-1) -th

parallel ADC 4.

From the output of the K-th parallel ADC 4, the P-bit code groups arrive at the decoder 12, which forms a logical 1 when the code appears

the upper limit of the quantization scale

K-th parallel ADC 4, logical

About - in the absence of such a code.

From the output of the decoder 12 signal

enters the second entrance (K-1) -th

block 7, where it is used to determine the division of the moment when the values of the information signal get into the junction zone of the quantization quantization of the K-th and (K-1) -th parallel ADC 4. This same signal

through register 14 enters the second control input of the decoder 8. This signal is similar in assignment to the signals arriving at the first control inputs of the decoder 8. Registers 13

and 14 are designed to delay the signal, for example, by one clock interval, similar to the signal delay in each block 7, associated with the analysis in blocks 7 of two consecutive

in time signal samples.

The decoder 8 essentially converts the K-bit input unitary code into a binary control code of the switch 9. The unitary code characterizes

the position of the information signal samples relative to the quantization scales of parallel ADCs 4. Depending on this, the switch 9 provides connection of code combinations to the input

register 10 from the output of block 7 corresponding to the parallel ADC 4, in the amplitude quantization range of which an information signal was received.

The code bit at the first information inputs of the switch 9 is a function of i, for example, when the corresponding information input of the switch 9 receives the U-bit code from the output of the register 13, and when the corresponding input of the switch 9 receives (n + log K) -pa3 - sequential code from the first output of the first block 7. All information inputs are

switch 9 is considered as (n + 1or,) - bit. The missing high-order bits for the (2-K) -information entries are assumed to be zero.

514

The generated (n + logj, K) -disk code is written to register 10 and fed to the output bus 11. Clocking of all registers and blocks 7 is effected by a clock frequency signal taken from the second block 16.

Block 7 works as follows.

On its fourth input from the output of the i-ro parallel ADC 4, the P-bit of the code group enters the bottom. In the ith block 7, it goes to the input of the decoder; a torus 21, at the output of which logical 1 is formed, when at its input a lower limit of the quantization scale of the i-ro parallel ADC 4 and a logical O in the absence of this code are detected.

From the output of the decoder 21, the signal goes to the first input of element 22 to the second input of which a transfer signal is received from the output of the decoder 26 (i + l) -ro of block 7. The decoder 26 forms r logical 1 when the upper bound code appears at its input { i + l) -ro parallel ADC A.

Thus, at the output of element 22, a logical O is formed only when the reference of the information signal hits the interface of the quantization scales i-ro and (i + l) -ro parallel ADC 4. Then this signal goes to the second input of element 24 through register 23, and at the first entrance - directly.

Register 23 delays a signal, for example, by one clock interval.

At the output of element 24, logical O is formed only when, for example, two consecutive samples of the signal are in the interface of the quantization scales i-ro and (i + O-ro parallel A / D converters 4. After inversion in element 25, the signal goes to the control input of register 19 in which, in the presence of a logical 1, a code value on the scale of (i + l) -ro parallel ADC 4 is written on its control input. This value is calculated in block I8j, the first input of which receives the code from the output of i-ro parallel ADC 4 via the third register 17, which performs the same signal delay and as the register 23. Thus, the calculation is taken for the second of two successive time samples entering the interface area. -first code arrives on input block of the first 1st

189036

output (i-bl) -ro of block 7, corresponding to the same count.

After calculation, the code value is written in register 19 and stored there until conditions appear (two consecutive signals in the reference time — in the interface area) for the next correction.

10 Further, a digital code corresponding to the reading of the information signal falling within the quantization scale of the (K-1) th parallel ADC 4 is generated at the output of the block

15-20 by adding to the P-bit code from the output (K-1) of the parallel ADC 4, which is sent to the first input of block 20 through register 17, the code contained in register 19. The code formed at the output of block 20 is fed through switch 9 to the information input of register 10, as well as to the first input of block 18 (K-2) -th block 7, where it is used in the corresponding

25

times dp compute and

writing code in the register 19 5k-2) -th block 7. Next, the work (K-2) -th and the remaining blocks 7 is similar.

30 Signal from the output of the decoder 26

The i-ro of block 7 through register 27 is fed to the i-th first control input of the decoder 8. Register 27 provides- the supply of a control signal to the i-th

35 the first control input of the decoder 8 and further to the first control inputs of the switch 9 simultaneously with the receipt of the corresponding digital code from the output of block 20 of the i-ro block 7 to the i-th first information input of the switch 9.

The second input of the register 17, the first inputs of the registers 23 and 27 of each block 7 is given the signal of frequency with c

45 second output unit 16.

Thus, in the proposed device, the conversion accuracy is improved due to digital correction.

50 conversion errors. Correction is carried out by introducing the junction zones of the quantization scales of individual integral transducers and analyzing the samples of the information signal,

55 falling into these zones. At the same time, in order to eliminate the effect of dynamic errors on the results of the correction, only those samples are analyzed that correspond to small rates of change in the values of the information signal.

Claims (2)

Invention Formula error responses are connected to the corresponding outputs of each i-ro parallel analog-to-digital converter, the outputs of which are connected respectively to the second inputs of the first shift register and the inputs of the second decoder, and the output of the second shift register is connected to 10 second control inputs of the second decoder, the outputs of which are connected to corresponding control inputs of the switch. 2. Converter according to claim. 1, p1. An analog-to-digital converter containing a matching amp, whose input is the input thickness, and the output is connected to the first inputs K of the limiting amplifiers, the second inputs of which are combined and connected to the output of the source of the limiting voltage, and -, 5 distinguished by the fact that each with the first inputs K to the parallel error correction block is executed on-line analog-digital conversions - two decoders, three registers of telephones, the second outputs of which are unified shift, register, block The subtraction is unpaired and connected to the output of the source of the addition unit, two OR elements and the reference bias voltage, and the third element NOT, the output of which is connected to the inputs connected to the corresponding first outputs of the delay unit, whose input is the clock signal bus, and the second exit with a control input of the register, the information inputs of which are connected respectively to the outputs of the subtraction unit, the first inputs of which are error correction connected to the corresponding outputs of each i-ro parallel analog-digital converter, the outputs of which are connected respectively to the second inputs of the first shift register and the inputs of the decoder, and the output of the second shift register is connected to the second control input of the second decoder, the outputs of which are connected to the corresponding control inputs to mmutatora. 2. The converter according to claim 1, differing in that each error correction block is executed on two decoders, three shift registers, a register, a subtraction block, an addition block, two OR elements and an NOT element whose output is connected characterized in that each error correction block is performed on two decoders, three shift registers, a register, a subtraction block, an addition block, two OR elements, and an NOT element whose output is connected with a control input of the register, the information inputs of which are connected respectively to the outputs of the subtraction unit, the first inputs of which are connected to the control input of the register 25 with the first inputs of the correction unit Pa, the output of which is output, characterized in that, in order to increase the conversion accuracy, K-1 error correction blocks, two shift registers, two decoders and a switch, the output of which is connected to the information input of the register, the first information inputs are entered into it the switch is connected to the corresponding first output- “shift hub” and the first inputs of the second error correction blocks, the second and third shift registers; the second information input of the switch is combined with the first input of the (K-1) -th correction block shibok and connected to the output of the first shift register, the second outputs of the error correction blocks soedivhod latter of which is connected to the output of the first decoder, and is output to third error correction unit 40 except the first error correction block, the third register output with the corresponding first upshifts, the second output of the block is the equal inputs of the first decryption error correction, the second input of the second pa, the first and third outputs of the (1 + 1) -th shift register is combined with the first error correction block, where, 2, ... the input of the first element OR and the connection K-2, is connected respectively to the input of the second element OR, the output and the second inputs of the i-ro block output of the second register of the shift of the error response, the second input (K-1) of the second with the second input of the first element of the error correction block is combined with OR, the output of which is connected to the input the first input of the second register is the shift-gg element NOT, the first input of the second and connected to the output of the second debris OR is connected to the output of the encoder, the third inputs of the blocks of the second and second decoder, the second input of the error response are combined with the second the second input of the correction unit is the input of the second and the first input of the first error, the first output of which is the shift registers and is connected to the output of the addition unit, the second second output of the delay unit whose even input is connected to the output of the last inputs of each i-ro block register but. error, the second input of the subtraction unit is combined with the first input of the addition unit and connected to the output of the first shift register, the first input of which is combined with the inputs of the first and second decoders and is the fourth input of the error correction unit, the third input of which is the combined second input of the first shift register and the first inputs of the second and third shift registers, the second the input of the last of which is connected to the output of the first decoder and is the third output of the error correction block, except for the first error correction block, the output of the third register