SU1481828A1 - Telemetering data transmitter - Google Patents

Abstract

The invention relates to the processing and transmission of information and can be used in telemetry systems for requesting and issuing telemetry data. The aim of the invention is to reduce the transmission time of information. To achieve this goal, a pilot-bit inverter is introduced into the device, which, in combination with the encoder and decoder, allows detecting errors in the transmission and reception of signals without the use of additional bits in the transmitted codes, which allows the use of shorter code sequences. 1 il.

Description

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The invention relates to processing. information transmission and can be used in telemetry systems for requesting and transmitting telemetry data.

The purpose of the invention is to reduce the time of information transfer,

FIG. 1 shows the scheme of the proposed device; in fig. 2 - detector failure.

A device for transmitting and receiving telemetry information contains on the transmitter side a first register

Shift, encoder 2, transmitter 3 addresses, receiver 4 (data), second shift register 5, decoder 6 errors, fault detector 7, 8 clock pulses, control block 9, clock transmitter 10, block

II data request, communication channel 12, containing three communication lines on the receiving side, address receiver 13, data transmitter 14, clock signal receiver 15, second error decoder 16, second encoder 17, check bit inverter 18, second control block 19, which data output block 20, address register 21 and data register 22, addresses 23 and readiness addresses 24, data readiness outputs 25, data 26, addresses 27, first 28 and second 29 sync pulses, data readiness inputs 30 and data 31 , de-detector 7 failure contains a timer 32, an element OR 33 and a trigger ger 34.

The device works as follows.

The address code of the required parameter from the computer enters through the input 23 of the device address to the input of the address register 21 and is written to it. One4

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temporarily from readiness input 24, the readiness impulse starts control block 9 and allows writing the parallel address code to shift register 1. When applying clock pulses from the first output of control block 9 to the shift control input of register 1, the parallel address code is converted into a serial one at the output of register 1. The first kodgr 2 adds one parity check bit to the input serial address code for the subsequent detection of a single error transmission over the communication channel. The address code is transmitted from the data request unit 11 via the address transmitter 3 to the data output unit 20. The control pulse from the output of the control unit 9 starts the failure detector 7. In the information issuing unit 20, the address code is received in the address receiver 13. The first impulse of the address code, which is the starting impulse, starts the second control unit 19, with the result that clock pulses appear on its first output. The clock pulses from the first output of the block 19 are fed to the first output 28 of the clock of the device. These sync pulses receive the serial address code. At the same time, by means of the decoder 16, an error is checked whether a single error has occurred when transmitting the address code. For this, a 16 error decoder checks the received parity code. If the sum of all bits is odd, the error trigger included in the error decoder is set to one and then 1m signal appears at the output of the 16 decoder error. i

After a control pulse arrives at the readiness input 30, a control block 19 is started to output data from block 20 to block 11. Data (parameter code) at input 31 of data is encoded for transmission in a second encoder 17, which adds one parity check bit to the serial code at its input. The check bit inverter 18, depending on the output of the error decoder 16, changes the last check bit.

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parity bit at the output of the second encoder 17.

If an error occurred while transmitting the address, i.e. if there is a single signal at the output of the decoder 16 errors, the value of the check bit is inverted, otherwise it does not change. Thus, information on the presence of an error during the transmission of the address code is transmitted back to block 11. This information is incorrectly transmitted in the case when a single error simultaneously occurs during the transmission of the address and data. However, this case is practically excluded due to the small value of the probability of error. The data code from the data transmitter 14 through the communication channel 12 is fed to the input of the data receiver 4 in block 11. The first data code pulse is the starting pulse, which from the output of data receiver 4 is fed to the reset input of the detector 7 crash. resetting the timer 32 to the zero state, and at the same time this starting impulse is -1 at the second input of the element OR 33. As a result, at the second output of the detector 7 there is a single signal that starts the control unit 9 to receive the data code. Then register 5 is written to the k-bit data code. At the same time, the received parity code is checked by the error decoder 6 for detecting an error. When an error is detected, the output trigger in the decoder 6 errors is set to one.

After the arrival of the control pulse at the input of the data register 22, the output of the detector is written to the first bit of the last bit, and the second bit to the output value of the error decoder 6, which indicates the presence of an error when transmitting information over the communication channel. At the same time, the contents of the shift register 5, i.e. data code. The control pulse from the fourth output of the first control unit also arrives at the output 25 of the device’s data readiness, thereby signaling the computer that the next telemetry value is ready.

parameter. In the event of computer failure, the computer receives information about the presence of a failure, and the specified process of requesting and transmitting the failed parameter is repeated.

Claims (1)

Invention Formula A device for transmitting and receiving telemetry information, comprising, on the transmitting side, an address register, a data register, an encoder, an address transmitter, a control unit, a clock pulse generator, the output of which is connected to the first input of the error decoder, on the receiving side an address receiver and an error decoder, an encoder, the input of which is connected to the first output of the control unit, a data transmitter, characterized in that, in order to reduce the information transmission time, the shift registers are entered into the device, g The cue ticker, the sync signal transmitter, the address register input is the first input of the device, the first input of the control unit is combined with the first input of the first shift register and is the second input of the Device, the first output of the control unit is connected to the second input of the first shift register and to the first input of the encoder the output of which is connected to the input of the address transmitter, the output of the first shift register is connected to the second input of the encoder, the output of the clock generator is connected to the second input of the control unit, to the first inputs of the detector pa SRB and to the input of the transmitter clock, the second output of the control unit is connected to the second input of SRB detector, a first output of which is connected to the third input ten 15 20 25 4818286 the control unit, the receiver output is connected to the third detector input failure, the second output of which is connected to the blocking input of the data register, the output of which is the information output of the device, the third output of the control unit is connected to the control input of the data register and the control output of the device, the fourth output the control unit is connected to the second input of the error decoder and the first input of the second shift register, the receiver output is connected to the second input of the second shift register, the output of which is connected to inf A data register input, the control input of which is connected to the output of the error decoder, a receiver of synchronization signals is inputted to the receiving side, a test bit inverter whose output is connected to the input of the data transmitter, the output of the address receiver is connected to the first inputs of the control unit and the error decoder and is the first the output of the device, the output of the clock signal receiver is connected to the second input of the control unit, the first and second outputs of which are respectively the second and third outputs of the device, the third output the control unit is connected to the first input of the check-bit inverter, the output of the error decoder is connected to the second input of the check-bit inverter, the output of the encoder is connected to the third input of the check-bit inverter, the third input of the control unit is the first input of the device, the second input of the encoder is the second the input of the device, the second output of the control unit is connected to the second by the input of the error decoder. thirty 35 40 45 H I B reset Fie.2