SU1284007A1 - Multifrequency signal receiver - Google Patents

Abstract

The invention of otisit to telecommunications. The purpose of the invention is to increase the noise immunity of the reception. The device contains an input amplifier 1, a shaper 2 recording pulses, a block of 3 electronic keys, a block 4 for selecting a maximum signal, a block 5 of filter integrators and a block 6 of amplitude detectors, and also contains analog element 7 OR and a band-pass filter 8. Shaper 2 contains a clock generator pulses, reference voltage source, D / A converter, large-scale accelerator, voltage comparator, three shift registers, two NOT elements, inverter unit, two adders and a signal conditioner, 2 Il.

Description

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The invention relates to telecommunications and can be used in multi-frequency systems for the transmission of discrete information.

The purpose of the invention is to increase the reception tolerance.

FIG. Figure 1 shows the structural electrical circuit of the M1 receiver of frequency signals; in fig. 2 is a structural electrical circuit of a recording pulse generator included in the receiver of multi-frequency signals.

The multi-frequency signal receiver contains an input amplifier 1, a shaper of 2 recording pulses, a block of 3 electronic switches, a block 4 for selecting the maximum signal, a block of filter integrators 5 and a block of 6 amplitude detectors, as well as an analog element 7 OR and band i filter 8.

A shaper 2 of recording pulses contains a generator of 9 clock pulses, 25 voltage sources, a reference voltage source 10, a digital-to-analog converter 11, a large-scale amplifier 12, a voltage comparator 13, the first shift register 14, the second 15, and the third. 16 shift registers, the first 17 and second 18 elements are NOT, the inverter unit 19, the first 20 and the second 21 adders and the driver 22 of the signal.

The receiver multi-frequency signals as follows.

The signals from the communication channel are fed to the input of the input amplifier G with an automatic gain control, in which they are normalized by level .Q is connected to the output of the input amplifier 1 a band-pass filter 8 that separates this frequency group, and only one can be transmitted at a time frequency from the group, as a result of which, at the output of the band-pass filter 8, single-frequency signals appear, which are then fed to the inputs of the integrator filter unit 5, matched with the received signals. The signals allocated by individual filter integrators are detected in block 6 of amplitude detectors and processed by block 4 for selecting the maximum signal, the signal at one of the outputs of which appears only if it exceeds all other signals of this frequency group. Signatures from the Blo35 outputs

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4 maximums of the maximum signal are sent to the signal inputs of the electronic key block 3 and through the analog element 7 OR to the input of the imager 2 recording pulses, generating recording pulses at the moments of the change of multi-frequency premises. The recording pulses from the output of the imaging unit 2 of the recording pulses go to the control inputs of the filter integrator block 5, transfer them to the initial state, and to the control inputs of the electronic key block 3, allowing registration of the received signal at times when the signal is / interference as much as possible. The recording of the received signals at the moments of changing the multi-frequency bursts is provided by the shaper 2 of the recording pulses (Fig. 2). Here, a set of voltage comparator 13, reference voltage source 10, clock pulse generator 9, digital-analog converter 11, scale amplifier 12 and first shift register 14 is a digital-analog converter cyclically measuring the envelope value of the integrated frequency signal c output of the analog element 7 OR, arriving at the second input of a 13 voltage generator, an 8-bit pulse is formed in each measurement cycle for ten clocks of the frequency of the generator of 9 clocks one written to the first shift register 14, the ninth clock overwrites the code from the second shift register 15 to the third shift register 16, and the tenth clock overwrites the information from the first shift register 14 to the second shift register 15 and resets it to its original state the first shift register 14 is shifted. Managing the writing of codes to registers 15

. and 16 is performed at the clock inputs through the first 17 and second 18 elements, respectively. In the first 20 and second 21 adders, connected in series, the 8-bit codes recorded in the second 15 and third 16 shift registers are compared, the code of this measurement cycle acts in the second shift register 15, and the preceding cycle code in the third shift register 16 measurements arriving at the appropriate inputs

31284007

adders 20 and 21 in the inverse code due to the inclusion of a block of 19 inverters. If the value of the number recorded in the third shift register 16 exceeds the value of the number recorded in the second shift register 15, the transfer output of the second adder 21 is a signal from whose negative differential using a form-ragger, the outputs of the maximum signal selector unit through the analog element 1-SHI, the home of the recording pulse generator is connected to the BXOI, the output of which is connected to the control inputs of the filter integrator unit.

2. The receiver according to claim 1, about t l and h a - y y and with the fact that the driver

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The signal slot 22 is formed. A pulse of recording pulses contains ge- registrations of the required duration. clock pulse source

reference voltage, serially connected digital-to-analog converter, large-scale amplifier, voltage comparator, first, second and third shift registers, first and second elements NOT, inverter unit, first and second adders and signal conditioner, the output of which is the output of the recording pulse generator, the input of which is the second input of the voltage comparator, the output of the voltage source being connected to the reference input of the digital-to-analog converter, the output of the clock impu generator All are connected to the clock input of the first shift register, the first and second outputs of which are connected via the first and second elements to the clock inputs of the second and third shift registers, the output of the first adder is connected to the transfer input of the second adder, 35 inputs of the inverter unit are connected to the outputs of the third register shift, informational inputs of which and informational inputs of the second shift register and the digital-analogue converter in the converter are connected to the sockets in the first shift register outputs, the first od which is connected to its adjusting input, and the data inputs of the first and second

The indicated condition of the formation of the registration pulse is fulfilled only when the multi-frequency signal is changed. The required accuracy of determining this Time is achieved by varying the number of measurement cycles during the duration of one burst of a multi-frequency signal.

Invention Formula

1, Multi-frequency signal receiver, containing an input amplifier, a recording pulse driver, an electronic switch unit, a maximum signal selector unit, an integrator filter unit and a detector unit, the outputs of which are connected to the signal inputs of the electronic switch unit through the maximum signal selector unit, control inputs which are combined with the output of the registration pulse generator, and the integrator filter block inputs are combined, and the input amplifier, whose input is the input of the receiver Nick, the outputs of which are the outputs of the electronic key unit, while the outputs of the filter integrator unit are connected to the inputs of the amplitude detector unit, characterized in that.

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in order to improve the noise immunity, adders are connected to the corresponding method, an analog element OR and a band-pass filter are inserted into it through the output of the input amplifier connected to the inputs of the filter integrator unit, while the outputs of the maximum signal selector unit are connected via an analog element 1-ШИ The BXO house of the registration pulse generator, the output of which is connected to the control inputs of the filter integrator unit.

2. The receiver according to claim 1, about t l and h a - y y and with the fact that the driver

recording pulses contains a clock pulse generator, the source

the second shift register outputs and the inverter block outputs, and the second adder output is connected to the input of the signal shaper.

Claims (2)

1. A multi-frequency signal receiver comprising an input amplifier, a recording pulse generator, an electronic key block, a maximum signal selection unit, an integrator filter unit and an amplitude detector unit, the outputs of which are connected through the maximum signal selection unit to the signal inputs of the electronic key unit, the control inputs of which combined with the output of the shaper of the recording pulses, and the inputs of the filter-integrator block are combined, and the input amplifier, the input of which is the input the nickname, the outputs of which are the outputs of the electronic key block, while the outputs of the filter-integrator block are connected to the inputs of the amplitude detectors block, characterized in that, in order to increase the noise immunity of the reception, an analog OR element and a bandpass filter are inserted into it, which is through the output of the input amplifier connected to the inputs of the filter-integrator • 5 integrator unit, while the outputs of the maximum signal selection unit through an analog · OR element are connected to the input of the recording pulse generator, the output of which connected to the control inputs of the filter integrator block. 2. The receiver by π. 1, with the fact that the shaper 10 recording pulses contains a clock pulse generator, a reference voltage source, a digital-to-analog converter, a scale amplifier, a voltage comparator, the first, second and third shift registers, the first and second elements of NOT, the inverter unit, the first and second adders and the signal shaper, the output of which is output is the output of the recording pulse generator, the input of which is the second input of the voltage comparator, and the output of the reference voltage source is connected to the reference during the digital-to-analog converter, the output of the clock generator is connected to the clock input of the first shift register, the first and second outputs of which through the first and second elements are NOT respectively connected to the clock inputs of the second and third shift registers, the output of the first adder is connected to the transfer input of the second adder, block inputs the inverters are connected to the outputs of the third shift register, the information inputs of which and the information inputs of the second shift register and digital-to-analog converter are connected with the corresponding outputs of the first shift register, the first output of which is connected to its installation input, while the information inputs of the first and second adders are connected to the corresponding outputs of the second shift register and the outputs of the inverter block, and the output of the second adder is connected to the input of the signal conditioner.