RU2024198C1 - Digital data transmission system using complex waveform signals - Google Patents

Abstract

FIELD: digital data transmission. SUBSTANCE: sending end has encoding unit, two modulating units, complex signal generator, clock frequency generator, frequency divider, multiplier, bell-shaped pulse shaper, carrier frequency generator, power amplifier. Receiving end has multiplier, band filter, standard signal generator, synchronizing unit, amplitude detector, analog-to-digital converter, storage device, demodulating unit, least-distorted complex signal element selector unit, decoding unit. Least-distorted complex-signal element selector unit has three switches, two storage registers, comparison circuit. EFFECT: improved noise immunity due to self-selection of most distorted complex-signal element in receiver each time complex signal bit arrives. 3 dwg

Description

 The invention relates to techniques for transmitting discrete information by complex waveforms used in broadband communication systems operating in multipath channels, in asynchronous address-based communication systems with free access, and in other communication systems with excessive noise-resistant coding of signals.

 In FIG. 1 and 2 show a structural diagram of a system for transmitting discrete information by signals of complex shape; in FIG. 3 is a block diagram of a block for selecting the least distorted element of a complex signal.

 The transmitting side of the system for transmitting discrete information by signals of complex shape contains a coding unit 1, a first modulation unit 2, a complex signal generator 3, a clock frequency generator 4, a frequency divider 5, a multiplier 6, a bell pulse shaper 7, a second modulation unit 7, a carrier frequency generator 9 power amplifier 10.

 The receiving side includes a multiplier 11, a band-pass filter 12, a reference signal generator 13, a synchronization unit 14, an amplitude detector (AD) 15, an analog-to-digital converter (ADC) 16, a storage device (memory) 17, a demodulation unit 18, the least selector 19 distorted element of the complex signal, block 20 decoding.

 Block 19 contains a first key 21, a first memory register 22, a comparison circuit 23, a second key 24, a second register 25, and a third key 26.

 The system for transmitting discrete information by signals of complex shape works as follows.

On the transmitting side, the transmitted discrete information is fed to the information input of block 1, in which it is encoded in accordance with the encoding method used, after which it is transmitted to the first input of the first modulation block 2, which carries out information phase modulation of a complex signal consisting of N rectangular elements and generated by a generator 3, the operation of which controls the generator 4 with a divider 5, forming the clock f _m and f _n the cyclic frequency, the latter also controls the operation of block 1. The output of the first block Modulation 2, a complex FM signal with rectangular elements is fed to the second input of the multiplier 6, the first input of which receives pulses of a bell shape from the output of the driver 7 controlled by the generator 4. Using the additionally introduced multiplier 6 and the driver 7, the bell amplitudes are given the amplitudes of the elements of the complex FM signal with its equality to zero at the boundaries of the elements of a complex signal. From the output of the multiplier 6, a complex FM signal with bell-shaped elements is fed to the second input of the second modulation unit 8, which performs balanced oscillation modulation with a carrier frequency supplied to its first input from the output of the generator 9, with a complex FM signal. The amplifier 10 at the output of the second modulation unit 8 produces the necessary amplification of the transmitted complex FM signal.

 The receiver of complex signals operates as follows.

The received complex FM signal, consisting of N bell-shaped elements, is fed to the second input of the multiplier 11, to the input of block 14 and to the input of HELL 15. Block 14 generates clock f _t and cyclic f _c clock pulses necessary for synchronization of the reference complex signal generated by the generator 13 receiver, with the received complex signal, as well as to synchronize the operation of all other nodes of the receiver of complex signals. The generator 13 of the receiver is similar to the generator 3 of the transmitter. The reference complex signal of the receiver from the output of the generator 13 is supplied to the first input of the multiplier 11, the output voltage of which is supplied to the input of the band-pass filter 12. The multiplier 11 and the band-pass filter 12 form a correlator, at the output of which signal elements are formed at an intermediate frequency, in the change of which parameters (amplitudes , the initial phase or frequency, depending on the modulation method used), the transmitted information is laid down. These signals are fed to the input of the corresponding demodulator 18, which independently demodulates the information parameters of all elements of the complex signal. At the same time, clock pulses that coincide with the boundaries of the elements of the complex signal are received at the control input of the demodulator 18 from the clock output f _{t of} block 14.

In this case, information is read from the demodulator and the demodulator is reset by clock pulses f _t from the output of block 14. As a result, binary symbols "1" or "0" are formed at the output of demodulator 18 (during a single manipulation) corresponding to the transmitted information symbol for all elements of a complex signal .

To automatically select the least complex distorted signal element, it is necessary to generate digital samples of the fluctuation noise amplitude for each element of the complex signal. This is done using the ADC 16 connected to the output of the AD 15, according to the commands of the control clock pulses coming from the clock output f _{t of} block 14 at the moments corresponding to the boundaries of the elements of the complex signal, i.e. at moments when the amplitudes of the elements of a complex signal having a bell shape are equal to zero. As a result, at the ADC output 16, digital values of the fluctuation noise amplitudes for each element of the complex signal are generated. Moreover, on each interval equal to the duration of the signal element, the amplitude of the interference with a high degree of probability is equal to its value at the boundary of the corresponding signal element at the time of its digitization, since the correlation interval at the output of the correlator is equal to the duration of the signal element. The generated digital interference samples from the output of the ADC 16 go to the input of the memory 17, which is a memory register controlled by pulses of the clock frequency f _t , in which the complex signal of the digital signal of the interference amplitude generated at the element boundary is stored and stored for the duration of the element, which is necessary for the correct operation of block 19. The signals from the output of the memory 17 are fed to the first input of block 19, to the second input (Input 2) of which the output signals of demodulator 18 are received. In block 19, the values of the interference amplitude arrive at the second input of the comparison circuit 23 directly and at its first input through the first key 21 and the first memory register 22 connected in series.

At the beginning of each sending of a complex signal from the cyclic output f _c block 14, a cyclic pulse is applied to the control input of block 19 and writes the maximum value to the first register 22 at the input (set 1) of the memory register. If the value at the output of the ADC 16 is less than the maximum recorded at the initial moment in the second register 22, then, according to the corresponding command of the comparison circuit 23, the first and second keys 21-24 are opened and the value of the interference amplitude smaller than the maximum possible value is written instead to the first register 22 by information inputs, i.e. the previous value from this register is erased, and the corresponding demodulated binary signal element is recorded in the second register 25. In the process of sequentially comparing all the values of the interference amplitudes in the comparison circuit 23 on the interval of the duration of the complex signal, the noise with the minimum amplitude is obviously automatically selected and recorded in the second register 25 ( with erasing the previous information) of the corresponding demodulated element of the complex signal, the least distorted by interference. Then, at the end of the complex signal, at the command of the cyclic pulse f _c , the third key 26 opens from the output of block 14 and the automatically selected least distorted element of the complex signal from the output of the second register 25 enters the input of block 20.

In block 20, according to the selected least distorted elements of the complex signal under the control of cyclic clock pulses from the cyclic output f _{c of} block 14, the transmitted information is decoded in accordance with the encoding method used, for example, difference coding of the first or higher orders.

Claims (2)

 1. A DISCRETE INFORMATION TRANSMISSION SYSTEM OF COMPLEX FORM, comprising on the transmitting side a complex signal generator, a serially connected clock generator, a frequency divider, a coding unit and a first modulation unit, series-connected a carrier frequency generator, a second modulation unit and a power amplifier, while and the clock inputs of the complex signal generator are connected respectively to the outputs of the frequency divider and the clock generator, and the output of the complex signal generator is connected to the second input of the first modulation block, the second input of the coding block is the information input of the transmitting side, and the output of the power amplifier is the output of the transmitter, and on the receiving side is the decoding unit and serially connected synchronization block, reference signal generator, multiplier, bandpass filter, and demodulation block, the cyclic output of the synchronization unit is connected to interconnected cyclic inputs of the reference signal generator and the decoding unit, interconnected input of the synchronization unit The output and the second input of the multiplier are the information input of the receiving side, the output of which is the output of the decoding unit, characterized in that on the transmitting side, serially connected bell pulse former and multiplier are introduced, the second input and output of which are connected respectively to the output of the first modulation unit and the second input of the second modulation unit, the clock input of the bell pulse shaper is connected to the output of the clock generator, and on the receiving side, in series connected amplitude detector, analog-to-digital converter (ADC), a storage device and a unit for selecting the least distorted element of the complex signal, the output of which is connected to the second input of the decoding unit, the output of the demodulation unit is connected to the second input of the unit for choosing the least distorted element of the complex signal, the control input of which connected to the cyclic output of the synchronization unit, the clock output of which is connected to the interconnected clock inputs of the ADC, the storage device and the demodulation unit, in the course of the amplitude detector is connected to the input of the synchronization block.  2. The system according to claim 1, characterized in that the unit for selecting the least distorted element of the complex signal comprises a first key, a first memory register, a comparison circuit, a second key, a second memory register and a third key, the output of which is the output of the least distorted select block element of the complex signal, the second input of the second key is the second input of the block selection of the least distorted element of the complex signal, the first input of the first key is connected to the second input of the comparison circuit and is the first input of the block boron element least distorted composite signal, the first switch control input connected to the output of the comparison circuit, a complex control unit selecting the least distorted input signal of the element connected to the input "Set 1" of the first memory register and the third switch control input.

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