SU1116434A1 - Arithmetic unit for fast fourier transform processors - Google Patents

Abstract

ARITHMETIC DEVICE FOR FURRY'S FAST TRANSFORMATION PROCESSORS, containing eight input registers, informational inputs of which are the first informational inputs of the device, the i-th converter (i 1,4). the output of which is connected to the i -th input of the multiplier of complex numbers in the non-positional code, the fifth input of which is the second information input of the device (i st., modulo P p. subtractor modulo, (i 1,4), eight output registers The information outputs of which are information codes of the device, characterized in that, in order to increase accuracy, eight order registers, eight blocks of permanent memory, twelve registers, subtractor, adder, the first group of registers of four subgroups of five registers in the order, the second group of registers of four subgroups of six registers in each, the third group of registers of four subgroups of three registers in each, with the information outputs of the first and second registers of the order connected to the address input of the first block of permanent memory, the information output of which is connected to the information input of the first register, the information output of which is combined with the information output of the third register of the order and connected to the address input of the second block of permanent memory The information output of which is connected to the information inputs of the second and third registers, (/) the information outputs of which are connected to the information output of the fourth order register and connected to the address input of the third permanent memory unit, the information output of which is connected to the information inputs of the fourth, fifth and the sixth registers, the information outputs of the fourth and fifth Od registers are connected to the informational 4 00 4th output of the fifth register of the order and connected to the address input of the third block AM, information outputs of the sixth and seventh registers of the order are connected to the address input of the fourth block of permanent memory, whose information output is connected to the information input of the seventh register, information output of which is connected to the information output of the eighth register of the order and connected to the address input of the second block memory, information output of the sixth register

Description

connected to the first input of the subtractor and informat ion input of the eighth register, information output of which is connected to the information input of the ninth register, information output of which is connected to the first input of the adder, the output of which is connected to information input of the tenth register, information output of which is connected to information inputs eight register outputs, the low-order bits of the eight input registers are bit-wise connected to the second input of the subtractor, the output of which is connected to the information input One eleventh register, whose information output is connected to the first input of a binary-to-modular converter, which i- and (-1 1.4) input is connected to the information input of the first register of the first subgroup of the first group, whose information output is connected to information outputs of the second and third registers of the i -th subgroup of the first group, information outputs of the first, second, third and fourth registers of the i-th subgroup of the second group and connected to the first inputs of the subtractor modulo R. and the adder modulo p. The outputs of which are connected to the information; the ion inputs of the registers are respectively with odd and even numbers of the i-th subgroup of the second group and are connected respectively 6434

but with the information entry first. and information inputs of the second, third registers of the i and subgroups of the third group, the information outputs of which are connected to the i-th input of the modular-to-binary code converter, the first and second outputs of which are connected respectively. with the second input of the adder and the information input of the tenth register, the outputs of the higher bits of the eight input registers are respectively connected to the inputs of the bits of the twelfth register, the information output of which is connected to the second input of the converter of the binary code to the modular, 1st (i 1, 4) the output of the multiplier of complex numbers in the non-positional code is connected to the information inputs of the second, third, fourth and fifth registers - and subgroups of the first group, information outputs of the fourth and fifth registers of the i-th subgroup The first group is connected to the information outputs of the fifth and sixth registers of the i and subgroups of the second group and connected to the second inputs of the subtractor modulo R. and the adder modulo R., the information inputs of eight order registers are connected respectively to the information inputs of eight input registers and These are the third information inputs of the device.

The invention relates to computing and is intended for use in high-speed fast Fourier transform processors with a mixed base 2 and 4 of a conveyor type, focused on processing low-order signals (12-24 bits).

A device is known for calculating a fast Fourier transform with a base 4, which contains input and output registers, multipliers, adders and allows to reduce the total number of multiplications in comparison with the algorithms for base 2.

In addition, algorithms with a base of 4 are more accurate than 1. The disadvantage of the known fast Fourier transform processors,

with base 4 operating in a positional number system, is the complexity of their arithmetic units.

The closest in essence and technical solution to the invention is an arithmetic unit for a fast Fourier transform processor, containing input and output buses of the device, connected respectively to the input registers and decoders 3

device, block, adders, modules m.P1, P2, P3, P4 of the used nonpositional number system, multiplier of complex numbers in the nonpositional code two-bit shift constant register, driver of the shift constant, two auxiliary two-bit registers, converter of binary code into modular the code connected to the input of the multiplier of complex numbers, the three input registers of the modular adders-subtractors block, the output registers of the modular adders-subtractors block registers and the converter of the module Nogo code into binary code. This arithmetic unit is implemented on the basis of modular arithmetic and performs a sequence of four-point transformations in a conveyor mode 12.

A disadvantage of the known devices is the impossibility of its use for executing fast Fourier transform algorithms with mixed bases 2 and 4. In addition, the accuracy of the device is reduced because all samples of the output signals of each stage of the algorithm have the same ( maximum order

The purpose of the invention is to increase the accuracy of the device.

This goal is achieved by the fact that the arithmetic unit for fast Fourier transform processors, containing eight input registers, the information inputs of which are the first information inputs of the device, the binary to code converter, i and (i 1,4) are connected to i - to the input of the multiplier of complex numbers in the nonpositional code, the fifth input of which is the second information input of the device, modulo-P adders (i 1,4), modulo-R subtractors (i 1,4,), eight output registers, infor whose output outputs are informational outputs of the device, eight order registers are entered, eight fixed memory blocks, twelve registers, a subtractor, an adder, the first group of registers of four subgroups of five 164

344

There are two groups of registers from each of the subgroups, six registers each, and a third a group of registers from four subgroups of three registers to each, with information outputs of the first and second registers. - And the second register of the order is connected to the address input of the first block of the permanent memory, the information output of which is connected to the information input of the first register, the information output of which is combined with the information output of the third register of the order and connected to the address input of the second block of the permanent memory , information, the output of which is connected to the information inputs of the second and third registers, information outputs of which are connected to the information output of the fourth order register and connected to the address input of the third block of permanent memory, the information output of which is co-. Informational inputs of the fourth, fifth and sixth registers, information outputs of the fourth and fifth registers are connected to the information output of the fifth register of the order and connected to the address input of the third memory block, information outputs of the sixth and seventh registers are connected to the address the input of the fourth block of permanent memory, the information output of which is connected to the information output of the seventh register, the information output of which is connected to the information output of the eighth register then It is connected to the address input of the second memory block, the information output of the sixth register is connected to the first input of the subtractor and the information input of the eighth. the register, the information output of which is connected to the information input of the ninth register, the information output of which is connected to the first input of the adder, the output of which is connected to the information input of the tenth register, whose information output is connected to the information inputs of the eight output registers, the outputs of the lower eight bits of the input registers bits are connected to the second input of the subtractor, the output of which is connected to the information input of the eleventh register, the information output of which is connected to the first input of the binary code converter to the module rn,. (i TT) the output of which is connected to the informational input of the first register (the i-th subgroup of the first group, the information output of which is connected to the information outputs of the second and third register - and the subgroups of the first group, information outputs of the first, second third and fourth registers / i subgroups of the second group and connected to the first inputs of the output module for module P and the modulo modulator P ;, - whose outputs are connected to the information inputs of registers with odd and even numbers, respectively, of the i -th subgroup of the second group and Ina, respectively, with the information input of the first and information inputs of the second, third registers of the i- and subgroups of the third group, the information outputs of which are connected to the i-th input of the modular-to-binary code converter, the first and second outputs of which are connected respectively to the second input of the adder and- the information input of the tenth register, the outputs of the high bits of the eight input registers, respectively, are connected to the inputs of the bits of the twelfth x gistr, whose information output is connected to the second input the binary code converter to modular, i-th (,, 4) output of the multiplier of complex numbers in the non-positional code is connected to the information inputs of the second, third, fourth and fifth registers of the i-th subgroup of the first group, information outputs of the fourth and fifth the registers of the i-th subgroup of the first group are connected to the information outputs of the fifth and sixth registers of the t-th subgroup of the second group and connected to the second inputs of the subtractor modulo p. and an adder modulo P., the information inputs of the eight registers of the order are connected respectively to the information inputs of the eight input registers and are the third information inputs of the device. The drawing shows structures on the scheme of arithmetic devices 1, 6 for fast Fourier transform processors. The device contains the information inputs of the device li, 2., 3- (i 1,2,.,., 8), the information outputs of the device 4. i (1 1,2, ..., 8), the order registers (input from -, accounts) 5.1. (i 1,2, ..., 8), input registers 6. i (i 1,2, ..., 8), registers 7-17, registers 18.-31.Р ( C 1,2,3,4), register 32, output registers 33.1 (1 1,2,..., 8), fixed memory blocks 34-37, order incrementor 38, subtractor 39.R and adders 40 by the th module Pg of the used nonpositional number system (C 1,2,3,4), the adder of the order 4t, the binary code to modular converter 42, the multiplier 43 of the complex numbers in the non positional code and the inverter module 44 rnogo.koda in binary. Register number indices 18.131. and adders and subtractors 39.8, 40.e (g 1,2,3,4) coincide with the sequence numbers of the modules associated with these blocks. The bits of the registers whose numbers are supplied with the index C (f 1, 2, 3, 4) are fg og bits, where x denotes the smallest integer not less than the real number X. Register input 5.i (l 1,2 ,. .., 8) is connected to the corresponding input bus li (.1 1, 2,. .., 8), through which the value of the reference value of the input signal is received. In addition, the order value from the bus 1.i is fed to the first input of the register 6.i (1,2, ..., 8), to the second input of which via the bus 2, i the input mantissa value arrives - and the output of the converter 42 connected by the input of the multiplier 43 and the input of the register 18.e (K 1,2,3,4). Bus 3, connected to the input of the multiplier. 43 complex numbers, is used to transmit to the multiplier addresses, which are recorded in a special block of memory contained in the multiplier, the information about the required turntable. The inputs of registers 19.e-22.e (e. 1,2,3,4) are connected to the K-th outputs of the multiplier, 43. The outputs of registers 18.C, 19.t, 20.e, 23.e-26.e (e 1,2,3,4) are combined and connected to the first inputs of the adder 40.t and the subtractor 39.1

7-1

(E 1,2,3,4), the second inputs of which are connected to the outputs of the registers 21.f, 22J, 27.e, 28.e se se 1,2,3,4). The output of the modular subtractor 39. And / connected with the inputs of registers 23., 25. (27.e, 29.e (e 1,2,3,4), and the output of the Modular adder 40. connected to the inputs of the registers 24., 26.,

28.e, 30.e, 31.e (e 1,2,3,4).

The outputs of registers 29., 30., 31. (1,2,3,4) are combined and connected to the corresponding inputs of the converter 44.

The first output of the converter 44 is connected to the second input of the adder of orders 41, the output of which is connected to the first input of the register 32. Buto34

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A swarm input of register 32 is connected to the second output of converter 44. The output of register 32 is connected to the inputs of output registers 33.i, the outputs 5 of which go to the output buses of device 4. t (-i 1,2, ..., 8).

A multiplier 43 multiplies a complex number by a complex constant in 10 cycles with an output capacity of one complex number in four cycles.

Table 1 shows the parameters of the used blocks of the permanent memory, and Table 2 lists the rules for for5 forming their contents. Arithmetic unit operates as follows.

Table

table 2

91

The device implements a discrete four-point Fourier transform of the input sequence y (n) y (n) + jy (n) (n 0,1,2,3) or a pair of two-point Fourier transforms of the input sequence y (n) y (n) + jy (n ), where p 0.2 for the first sequence and p 1.3 for the second sequence, wherein the following operations are carried out:

scaling and converting input numbers from the binary system, numbering into modular one according to the rule y (n) fy (n) 2- and uCn) (n). where 2 is the scaling factor and the magnitude

x if 1/2

tx h X; if x -) - 1/2 X x} multiplication by the corresponding turn of the 1st factor W. (k O, 1,2,3) sequences y (n) y (n) + jy (n), with the result that we get the sequences x (n) x (n) -n jx (n) (n 0.1, 2,3) four-point Fourier transform of the sequence x (n) x. (N) + jx (n) (n 0,1,2,3) or a pair of two-point Fourier transforms of the sequences x (n) x (n) + jx (n ), where p 0.2 for the first sequence and p 1.3 for the second sequence-, resulting from the Fourier transforms of the sequence x (p) X (p) + jx (n) are transferred from the modular number system to the binary one, by restoring however, the order of elements The four-point Fourier transform performed by the device is defined by the following relations: x (0) x (0) + x (1) + x (g) -I - x (3) -, x (1) x (0) - jx (1) - x (2) + jx (3) x (2) x (0) - x (1) + x (g) - x (3) i x (3) x (0) + jx (1) - x (2) - jx (3) Dividing the real and imaginary parts, we get x (0) x (0) + x (1) - x (2) + x (3), x (1) x (0) + x (1) x (2) x (3).

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x (2) x (0) -k (1) -bx (2) -x (3),

x (3) x (0) -x (1) -x (2) + x (3)

x (0) x (0) -x (1) + x (2) -x (3),

x (1) x (0) -x (1) -x (2) -xxx).

x (2) x (0) -x (1) -x (2) -x (3),

 x (3) x (0) + x (1) -x (2) -xChZ),

The pair of point-to-point Fourier transforms is determined from the following relationships:

The first

The second

20 x (0) x (0) -1-x (2) x (1) x (1) nx (3) x (2) x (0) -x (2) x (3) x (1 ) -x (3) From here, dividing the real and imaginary parts, we get x (0) x (0) -1-x (2) x (1) x (1) -t-x43), x (2) x ( 0) -x1 (2) x (3) x (1) -x (3), x (0) x (0) -x (2) x (1) x (1) -x (3), x ( 2) x (0) -x (2) x (3) x4l) -x (3), V Consider first the operation of the arithmetic unit when performing the four-point Fourier transform. At the zero cycle of the arithmetic unit, an entry is made to the input registers. On tires 2.1. (i 1.28) mantisses of counts enter the device, and the mantissa of the real parts of the counts y (n) (n 0,1,2,3) go to the registers 6 .i (n p-I), and the mantissa of the imaginary parts of the counts y (p) (, 1,2,3) - to registers 6.1, where i p - (- 5. At the same time, on tires 1.i, orders of real and imaginary parts of counts y (p) are entered into registers 5.1 and 6.1 С 1 1,2, ..., 8) under the indicated law. In the first, second, and third takgs, the maximum order of samples of input signals is determined, for eto, the outputs of registers 5 are opened in the first cycle and the values of the orders from these registers are received in pairs at the inputs of the fixed memory blocks 34-37, where

11 11

VII with lines 1-4 (zab ..) selects a larger From each pair of pores ok and is entered into the corresponding register 7-10. On the second cycle of operation of the device, the outputs of registers 7-10 are opened and the order values from these registers are received in blocks 36.37, and the result of the selection is entered into registers 11, 12. At the third cycle, the outputs of registers 11, 12 are opened, the order values are transferred from them to the inputs of the fixed memory block 37 and the found maximum order of the Mantissa of the number extracted from the input register 6.i is entered in the same cycle in the register p 17, and the order is fed to the input of the subtractor of orders 38, implemented on a permanent storage device, where, in accordance with line 5 (Table 2), a large-scale order of tishj Q, -h- is determined, which is entered in register 16 In the next clock cycle (the fifth clock cycle for the number y (2), the seventh clock cycle for the number y (2), etc.) the number from the registers 16,17 goes to the input of the converter 42, which scales the number by the formula y ( p) y (n) and the translation of a number from a binary number system to a modular one with bases P g (.1 1, 2, 3, 4). Thus, on the fifteenth clock cycle, the input registers 5.m, 6.i (.1 1,2, ..., 8) are released and at the sixteenth clock cycle they are written to the next Fourier transform. The number passes the converter 42 in three clock cycles, thus on the seventh clock cycle of the arithmetic

3A12

In the zero cycle, the previous contents of register 13 are moved to register 14, and the contents of register 14 are moved to register 15. Thus, the value of the maximum order bf .., frit is determined in the third cycle, where b is dock counts input signals.

Starting from the fourth clock cycle, opening alternately the outputs of one of the registers 6. i (.1 1,2,3, ..., 8),; extract the contents of these registers in the order given by Table 3.

Table 3 of the device, the number y (2) appears at the output of the converter and goes to the input register of the multiplier 43. Similarly, the numbers y (2), y (1), y (1), y (3), y ( 3) on the ninth, eleventh, thirteenth, fifteenth and seventeenth cycles, respectively. The numbers y (0) and y (0) do not pass through the multiplier, and from the output of the converter on the sixteenth and eighteenth clock cycles, respectively, are entered in register 18. (1, 2, 3, 4). The multiplier 43 multiplies the number by the complex constant W. for ten cycles, with the real and imaginary parts of the number x (n) y (n) W / (LECO, 1,2,3, k O, 1,2,3) arrive at the output of the multiplier in two adjacent bars. Thus, at the output of the multiplier of complex numbers 43, the products obtained by him appear in the order shown in Table 4. From the output of the multiplier 43, the numbers go to one of the registers 19., ..., 22.Р (f 1, 2 , 3.4). At the seventeenth cycle, the outputs of registers 18.8 and 22 are opened, the modular codes of the numbers y (0) x (0) and x (2) are fed to the subtractors 39.C and the adders 40.C and the results of the modular subtraction j X CC) - x ( 2) / P and additions IX (0) + x (2) / Pg are entered in registers 23., 24. (1, 2, 3, 4), respectively. On the eighteenth clock cycle, kai was indicated, register 18 receives the modular code of the number) (0). On the nineteenth clock cycle, the outputs of registers 18.f and 21.8 adders and subtractors 40 are flipped. F 39. determine the values (x (0) + x (2) / P and (x (0) - x (2) / Pj and send They are in registers 26L, 25.6 (1, 2, 3, 4), respectively. At the twenty-fifth cycle, the registers 22., 20.6 are opened. The numbers x (1), x (3) arrive at the outputs of the subtractors 39.K, adders 40 and the calculated values (hCh - hChZ) / Pr, / x (1) + x (3) / Pe write to registers 27., 28. (1,2,3,4), respectively. At the sixth cycle to the inputs of the subtractors 39. and adders 40.t enters the contents of registers 24. 28.e (E 1,2,3,4) and the results of calculation x (2) / x (0) - x (1) + x (2) - x (3) / P | and x (0) (x (0) + x (1) + x (2) + x ( 3) / Pg is entered into registers 29.8 and 30. Respectively. At the twenty-seventh clock cycle, the outputs of the registers 29.G (1,2,3,4) are removed and the modular codes of the number x (2) come from them to the inputs of the converter 44, which translates the modular code of a number into a binary code. On the twenty-eighth clock cycle, the registers 25., 27. open to the tactile outputs. The subtractors 39. and adders 40.8 receive the numbers (xCh2) / P, and fx (1) - x (3) / R {and

Table 4 the generated modular codes of the numbers x (1), x (3) are entered in the registers 29.К, 31. respectively. In the same clock cycle, the contents of the registers 30. (and 1,2,3,4) are fed to the inputs of the converter 44. On the twenty-ninth clock cycle, the contents of the registers 19. and 2, G. E arrives at the inputs of the subtractors 39.E and adders 40.c and the values of x (1) -x43) / Pg and the x (1) + x (3) / Pn that they receive are entered in registers 27.e, 28. e (E 1,2,3,4), respectively. On the thirtieth clock cycle, adders 40.C and subtractors 39. based on the contents of registers 23. and 27. arriving at their inputs, calculate the values of x (3), x (1) and put them into registers 29., 30. respectively. At the thirty-second clock cycle, the outputs of registers 26.E and 28.C are opened, the subtractors 39.6 and adders 40. receive the values I x (O) + x (2) / Pg, / x (1) + x (3) / Pb and the computed modular codes of the numbers x (2), x (0) are written to registers 29.b and 31.2 (1: 2,3,4), respectively. As was noted, the outputs of registers 29.e, zo.e, 31.d (g 1,2,3,4) are connected to the inputs of the converter 44 and, by opening in turn, these registers feed the numbers to the input of the converter 44 in the order indicated in table.5. At the output of converter 44, numbers converted from a modular code to a binary code appear with a delay of seven clock cycles. At the same time, the first output of the converter 44 is corrected to the maximum order of the current Fourier transform stored in register 15. This correction, together with the maximum order, is fed to the inputs of the adder of orders 41, performed on a permanent storage device, which, in accordance with line 8 (Table 2) calculates the order of output samples and places it in register 32. Simultaneously. with the order of the register 32 entered I I 28 28 I 29 | 30 | Thus, after seven clock cycles, the number arriving in modular form at the input of converter 44 is already recorded in binary code in register 32, and after one clock cycle from register 32 is rewritten into one of output registers 33.i (i 1,2, ...,eight). At the same time, the real parts of the output samples (h 0,1,2,3) are entered into registers 33.1, where .i п + 1, and the imaginary parts х (п) (п 0,1,2,3) - into registers 33.1 where, i p + 5. The last number of the Fourier transform is recorded in the output registers at the forty-second clock cycle, and this is the end of the input signal processing y (n). At the forty-third clock cycle, the result of the conversion is extracted from the output registers via the buses 4.1 (i 1,2, ..., 8) If two-point Fourier transforms are performed on the zero cycle of the arithmetic unit, the counters for the pair of conversions are entered into the input registers. one cycle the device performs two point-to-point Fourier transforms. From the zero to the eighteenth clock cycle inclusively and from the thirty-third to forty-third clock cycles the arithmetic unit operates in the same way as in the case of four-point transformation The operation of the arithmetic unit for two point transformations differs from the operation in the four-point Fur transform by the difference in transfers between the registers 18.e-31.e (g 1,2, 3, 4). On the seventeenth clock the outputs of registers 18 and 22 ,; modular codes of the numbers x (0) and x (2) are fed to the subtractors 39.1 and sums 40.6 (1 1,2,3,4) and the mantissa of the output number is received,

34 running from the second output of the converter 44. Table 3 31 1 32 | 33 1 tats of modular subtraction / x (0) x42) / Pg and addition / x (0) + X; (2) / Pg enter registers 23., 24.8, respectively. On the eighteenth clock cycle, the number x (0) is postgaged to register 18.6. On the nineteenth clock cycle, the outputs of registers 22. and 23.P are opened, and the register 25.t records the result of the subtractions (0) 7 2xH2) / P, and c. register 26. is the result of modular addition / fx (O) - x (2) / PP + x (2) x (0). At the twentieth cycle, the outputs of the registers 22.t and 23.f are opened and in registers 27.8 and 28. the same numbers are entered as in registers 25.P 26.e. . . At the twenty-first clock cycle, the outputs of registers 26 and 27 are opened. Their contents go to the subtractors 39. and adders 40.1 and the difference / 2x (2) / Pg goes to register 23.E and the sum is 2x / (0) 2x (2) / Pg enters the register 24. e (e 1,2,3,4). On the twenty-second clock cycle, the outputs of the registers are opened. 22.6 and 32.8 as a result of the subtraction we get the number / 2x42) - x (2) / Pg x (2), which goes to register 27, (and the result of adding / 3x (2) / Pg / goes to register 28.t (е 1 , 2,3,4). At the twenty-third clock cycle, the outputs of registers 18. and 21. are opened, the inputs of subtractors 39.C and adders 40. receive the numbers xCO) and x (2) and the calculated values (0) and x ( 2) enter registers 30. and 29.f (r 1, 2, 3.4), respectively. At the twenty-eighth clock cycle from registers 26. and 27.P, the numbers x (0) and) are calculated and

17

values (0), x (2) are entered in the registers 31. she 29.e (1, 2,3,4), respectively.

On the thirtieth clock cycle, the numbers xС1) and x (3) are extracted from registers 20. and 22.E and calculated in adders 40. and subtractors x39.xid), x (3) go to registers 30.Jf, 29. e ( P 1,2,3,4) respectively. I 27 G 28 I 29 T 30 Takt,

The end of the cycle is the same as with the four-point Fourier transform.

Thus, starting from the sixteenth cycle, the proposed arithmetic unit can begin processing a new four-point or a pair of two-point Fourier transforms. The capacity of the proposed arithmetic unit is one four-point or two point-to-point Fourier transforms per sixteen cycles. The time taken to complete a four-point or two-point Fourier transform with this device takes forty-three cycles.

For the technical implementation of the proposed arithmetic device 18

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On the thirty-second clock cycle, the numbers) from the register 19.f and hchZ) from the register 21. ; arrive at the entrances. adder 40.i and subtractor 39. and the obtained values (1), x (3) are recorded in registers 31. 29. P, respectively.

From registers 29.C, 30, t, 31. the numbers are fed to the input of the converter codes 44 in the sequence shown in table.6.

Table 6

34

I. . .. In the case when a modular number system with bases P. 11, P 13, P 15, 4 is used, it is possible to work with numbers whose mantissas vary in the range -2, except for the input and output code converters and the multiplier of complex numbers are needed There are 14 blocks of constant memory with a capacity of 256 chip-pattern layers each, 74 quad-bits, one 12 bits and 17 sixteen-bit registers with three output states (controlled outputs). Thus, this device allows to achieve greater accuracy of calculations in comparison with the prototype. T 31 T 32 I 33 1

h 1 te.

Claims (1)

Arithmetic device for fast Fourier transform processors, containing eight input registers, the information inputs of which are the first information inputs of the device, the binary to modular converter, ί – ((ί = 1.4). the output of which is connected to the ί-th input of the complex number multiplier in a non-position code, the fifth input of which is the second information input of the device, adders modulo P ^ (ί = 1,4), subtracters modulo P ^ (i = 1,4) , eight output registers, the information outputs of which are information outputs of the device, characterized in that, in order to improve accuracy, eight order registers, eight read-only memory blocks, twelve registers, a subtractor, adder, the first group of registers of four subgroups are entered into it l registers in each, the second group of registers of four subgroups of six registers in each, the third group of registers of four subgroups of three registers in each, and the information outputs of the first and second registers of the order are connected to the address input of the first block of read-only memory, the information output of which is connected to the information input of the first register, the information output of which is combined with the information output of the third order register and is connected to the address input of the second block of read-only memory, information the output of which is connected to the information inputs of the second and third registers, the information outputs of which are connected to the information output of the fourth order register and are connected to the address input of the third permanent memory block, the information output of which is connected to the information inputs of the fourth, fifth and sixth registers, information outputs of the fourth and fifth registers are connected to the information output of the fifth register of order and are connected to the address input of the third memory block, information outputs The sixth and seventh order registers are connected to the address input of the fourth block of read-only memory, the information output of which is connected to the information input of the seventh register, the information output of which is connected to the information output of the eighth order register and connected to the address input of the second memory block, information output of the sixth register SU ... 1116434 is connected to the first input of the subtractor and the information input of the eighth register, the information output of which is connected to the information input of the ninth register, the information output of which is connected to the first input of the adder, the output of which is connected to the information input of the tenth register, the information output of which is connected to the information the inputs of eight output registers, the outputs of the least significant bits of eight input registers are bitwise connected to the second input of the subtractor, the output of which is connected to the information the eleventh / register input, the information output of which is connected to the first input of the binary to the modular converter, the ϊth ((= 1,4) output of which is connected to the information input of the first register of the i-th subgroup of the first group, the information output of which is connected to the information the outputs of the second and third registers of the ίth subgroup of the first group, the information outputs of the first, second, third and fourth registers of the i-th subgroup of the second group and connected to the first inputs of the subtractor modulo P- and adder modulo R., the outputs of which are connected to the information inputs of the registers with odd and even numbers of the i-th subgroup of the second group and are connected respectively with the information input of the first · and the information inputs of the second, third registers of the i-th subgroup of the third group, the information outputs of which are connected to ΐ-th input of the modular code to binary converter, the first and second outputs of which are connected respectively to the second input of the adder and the information input of the tenth register, the outputs of the senior bits of eight the input registers are respectively connected to the inputs of the digits of the twelfth register, the information output of which is connected to the second input of the binary code to modular converter, the ith (ί = 1.4) output of the complex number multiplier in the non-position code is connected to the information inputs of the second, third, fourth and fifth registers of the i-th subgroup of the first group, information outputs of the fourth and fifth registers of the j-th subgroup of the first group are connected to information outputs of the fifth and sixth registers of the i-th subgroup of the second group and connected to the second inputs of the subtractor modulo and the adder modulo P ·, the information inputs of eight order registers are connected respectively to the information inputs of eight input registers and are the third information inputs of the device. .1