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SG10201807923YA - Exploiting frame to frame coherency in a sort-middle architecture - Google Patents

Exploiting frame to frame coherency in a sort-middle architecture

Info

Publication number
SG10201807923YA
SG10201807923YA SG10201807923YA SG10201807923YA SG10201807923YA SG 10201807923Y A SG10201807923Y A SG 10201807923YA SG 10201807923Y A SG10201807923Y A SG 10201807923YA SG 10201807923Y A SG10201807923Y A SG 10201807923YA SG 10201807923Y A SG10201807923Y A SG 10201807923YA
Authority
SG
Singapore
Prior art keywords
frame
tile
sort
computed
compact representation
Prior art date
Application number
SG10201807923YA
Inventor
Juan Fernandez
Casado Javier Carretero
Pedro Marcuello
Tomas G Akenine-Möller
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of SG10201807923YA publication Critical patent/SG10201807923YA/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T11/00—2D [Two Dimensional] image generation
    • G06T11/40—Filling a planar surface by adding surface attributes, e.g. colour or texture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—3D [Three Dimensional] image rendering
    • G06T15/005—General purpose rendering architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—3D [Three Dimensional] image rendering
    • G06T15/04—Texture mapping
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T17/00—Three dimensional [3D] modelling, e.g. data description of 3D objects
    • G06T17/10—Constructive solid geometry [CSG] using solid primitives, e.g. cylinders, cubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2200/00—Indexing scheme for image data processing or generation, in general
    • G06T2200/28—Indexing scheme for image data processing or generation, in general involving image processing hardware
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/122—Tiling

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Graphics (AREA)
  • Geometry (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • Image Generation (AREA)
  • Processing Or Creating Images (AREA)

Abstract

EXPLOITING FRAME TO FRAME COHERENCY IN A SORT-MIDDLE ARCHITECTURE Pixel values that were computed in a previous frame may be reused for the current frame, operating in a sort-middle architecture. A hash or some other compact representation of all the data used in a tile, including all triangles, uniforms, textures, shaders, etc. is computed and stored for each tile. When rendering the next frame, that compact representation is once again computed for each tile. In a sort-middle architecture, there is a natural break point just before rasterization. At this break point, the compact representation may be compared to the compact representation computed in the previous frame for the same tile. If those compact representations are the same, then there is no need to render anything for this tile. Instead, the contents of the color buffer or other buffers of the previous frame of the tile may be moved to the same buffer of the tile for the current frame. Fig. 2
SG10201807923YA 2014-05-14 2015-04-30 Exploiting frame to frame coherency in a sort-middle architecture SG10201807923YA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14/277,239 US9940686B2 (en) 2014-05-14 2014-05-14 Exploiting frame to frame coherency in a sort-middle architecture

Publications (1)

Publication Number Publication Date
SG10201807923YA true SG10201807923YA (en) 2018-10-30

Family

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SG10201706498SA SG10201706498SA (en) 2014-05-14 2015-04-30 Exploiting Frame To Frame Coherency In A Sort-Middle Architecture
SG11201608884PA SG11201608884PA (en) 2014-05-14 2015-04-30 Exploiting frame to frame coherency in a sort-middle architecture
SG10201807923YA SG10201807923YA (en) 2014-05-14 2015-04-30 Exploiting frame to frame coherency in a sort-middle architecture

Family Applications Before (2)

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SG10201706498SA SG10201706498SA (en) 2014-05-14 2015-04-30 Exploiting Frame To Frame Coherency In A Sort-Middle Architecture
SG11201608884PA SG11201608884PA (en) 2014-05-14 2015-04-30 Exploiting frame to frame coherency in a sort-middle architecture

Country Status (9)

Country Link
US (3) US9940686B2 (en)
EP (1) EP3143594B1 (en)
JP (2) JP6337322B2 (en)
KR (3) KR102154456B1 (en)
CN (3) CN106233337B (en)
RU (2) RU2677584C1 (en)
SG (3) SG10201706498SA (en)
TW (3) TWI550548B (en)
WO (1) WO2015175231A1 (en)

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Also Published As

Publication number Publication date
EP3143594A4 (en) 2017-12-27
JP6337322B2 (en) 2018-06-06
EP3143594A1 (en) 2017-03-22
KR102154456B1 (en) 2020-09-10
KR20190020197A (en) 2019-02-27
TW201545118A (en) 2015-12-01
RU2677584C1 (en) 2019-01-17
SG10201706498SA (en) 2017-09-28
TWI550548B (en) 2016-09-21
TW201608521A (en) 2016-03-01
KR20160134778A (en) 2016-11-23
RU2016140574A (en) 2018-04-17
KR101952922B1 (en) 2019-02-27
KR101980990B1 (en) 2019-05-21
JP2017215997A (en) 2017-12-07
CN110544289B (en) 2023-09-19
EP3143594B1 (en) 2020-12-02
WO2015175231A1 (en) 2015-11-19
JP6504212B2 (en) 2019-04-24
US9940686B2 (en) 2018-04-10
TWI596571B (en) 2017-08-21
RU2661763C2 (en) 2018-07-19
US9904977B2 (en) 2018-02-27
JP2017517799A (en) 2017-06-29
CN110555895B (en) 2023-09-29
US20150332429A1 (en) 2015-11-19
CN110544289A (en) 2019-12-06
US20160027144A1 (en) 2016-01-28
CN106233337B (en) 2019-09-24
US9922393B2 (en) 2018-03-20
CN106233337A (en) 2016-12-14
TWI566202B (en) 2017-01-11
US20160328820A1 (en) 2016-11-10
SG11201608884PA (en) 2016-11-29
CN110555895A (en) 2019-12-10
KR20170094464A (en) 2017-08-17
TW201706957A (en) 2017-02-16

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