SG10201400672TA - Semiconductor devices having through-contacts and related fabrication methods - Google Patents
Semiconductor devices having through-contacts and related fabrication methodsInfo
- Publication number
- SG10201400672TA SG10201400672TA SG10201400672TA SG10201400672TA SG10201400672TA SG 10201400672T A SG10201400672T A SG 10201400672TA SG 10201400672T A SG10201400672T A SG 10201400672TA SG 10201400672T A SG10201400672T A SG 10201400672TA SG 10201400672T A SG10201400672T A SG 10201400672TA
- Authority
- SG
- Singapore
- Prior art keywords
- contacts
- semiconductor devices
- fabrication methods
- related fabrication
- methods
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes) consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
- H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/968,068 US8951907B2 (en) | 2010-12-14 | 2010-12-14 | Semiconductor devices having through-contacts and related fabrication methods |
Publications (1)
Publication Number | Publication Date |
---|---|
SG10201400672TA true SG10201400672TA (en) | 2014-05-29 |
Family
ID=46144822
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG10201400672TA SG10201400672TA (en) | 2010-12-14 | 2011-09-14 | Semiconductor devices having through-contacts and related fabrication methods |
SG2011066073A SG182041A1 (en) | 2010-12-14 | 2011-09-14 | Semiconductor devices having through-contacts and related fabrication methods |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG2011066073A SG182041A1 (en) | 2010-12-14 | 2011-09-14 | Semiconductor devices having through-contacts and related fabrication methods |
Country Status (6)
Country | Link |
---|---|
US (1) | US8951907B2 (en) |
KR (1) | KR101331250B1 (en) |
CN (2) | CN102543848A (en) |
DE (1) | DE102011085203B4 (en) |
SG (2) | SG10201400672TA (en) |
TW (1) | TWI462188B (en) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8507375B1 (en) * | 2012-02-02 | 2013-08-13 | GlobalFoundries, Inc. | Alignment tolerant semiconductor contact and method |
US9153483B2 (en) | 2013-10-30 | 2015-10-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of semiconductor integrated circuit fabrication |
US9397004B2 (en) * | 2014-01-27 | 2016-07-19 | GlobalFoundries, Inc. | Methods for fabricating FinFET integrated circuits with simultaneous formation of local contact openings |
US9640444B2 (en) | 2014-07-23 | 2017-05-02 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
US9412659B1 (en) * | 2015-01-29 | 2016-08-09 | Globalfoundries Inc. | Semiconductor structure having source/drain gouging immunity |
US10153351B2 (en) | 2016-01-29 | 2018-12-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and a method for fabricating the same |
US10510851B2 (en) * | 2016-11-29 | 2019-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Low resistance contact method and structure |
US10867842B2 (en) * | 2018-10-31 | 2020-12-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for shrinking openings in forming integrated circuits |
US11482495B2 (en) * | 2018-11-30 | 2022-10-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor arrangement and method for making |
KR20210111396A (en) | 2020-03-02 | 2021-09-13 | 삼성전자주식회사 | Semiconductor device and method for manufacturing the same |
CN113555437B (en) * | 2020-04-26 | 2024-08-23 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
Family Cites Families (37)
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JP3500308B2 (en) | 1997-08-13 | 2004-02-23 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Integrated circuit |
TW374946B (en) * | 1997-12-03 | 1999-11-21 | United Microelectronics Corp | Definition of structure of dielectric layer patterns and the manufacturing method |
US6080661A (en) * | 1998-05-29 | 2000-06-27 | Philips Electronics North America Corp. | Methods for fabricating gate and diffusion contacts in self-aligned contact processes |
US6287961B1 (en) * | 1999-01-04 | 2001-09-11 | Taiwan Semiconductor Manufacturing Company | Dual damascene patterned conductor layer formation method without etch stop layer |
JP2000286254A (en) * | 1999-03-31 | 2000-10-13 | Hitachi Ltd | Semiconductor integrated circuit device and method of manufacturing the same |
JP2001077212A (en) * | 1999-08-31 | 2001-03-23 | Toshiba Corp | Semiconductor device and its manufacture |
KR100341663B1 (en) * | 1999-09-27 | 2002-06-24 | 윤종용 | Method of forming bit line contact holes in a semiconductor device with reduced photolithography process |
US6300201B1 (en) * | 2000-03-13 | 2001-10-09 | Chartered Semiconductor Manufacturing Ltd. | Method to form a high K dielectric gate insulator layer, a metal gate structure, and self-aligned channel regions, post source/drain formation |
JP2001338978A (en) * | 2000-05-25 | 2001-12-07 | Hitachi Ltd | Semiconductor device and manufacturing method thereof |
US6465294B1 (en) * | 2001-03-16 | 2002-10-15 | Taiwan Semiconductor Manufacturing Company | Self-aligned process for a stacked gate RF MOSFET device |
US20030060037A1 (en) * | 2001-09-27 | 2003-03-27 | Joseph Wu | Method of manufacturing trench conductor line |
KR100444306B1 (en) * | 2001-12-31 | 2004-08-16 | 주식회사 하이닉스반도체 | Manufacturing method for semiconductor device |
US6743712B2 (en) * | 2002-07-12 | 2004-06-01 | Intel Corporation | Method of making a semiconductor device by forming a masking layer with a tapered etch profile |
JP2004095611A (en) * | 2002-08-29 | 2004-03-25 | Fujitsu Ltd | Semiconductor device and method of manufacturing the same |
US6673718B1 (en) | 2002-11-27 | 2004-01-06 | Samsung Electronics Co., Ltd. | Methods for forming aluminum metal wirings |
TWI250558B (en) * | 2003-10-23 | 2006-03-01 | Hynix Semiconductor Inc | Method for fabricating semiconductor device with fine patterns |
KR100562675B1 (en) * | 2003-11-04 | 2006-03-20 | 주식회사 하이닉스반도체 | Manufacturing method of semiconductor device |
TWI242797B (en) * | 2004-06-01 | 2005-11-01 | Nanya Technology Corp | Method for forming self-aligned contact of semiconductor device |
JP2006019480A (en) * | 2004-07-01 | 2006-01-19 | Nec Electronics Corp | Method for manufacturing semiconductor apparatus |
KR100621630B1 (en) * | 2004-08-25 | 2006-09-19 | 삼성전자주식회사 | Damascene process using dissimilar metals |
KR100630749B1 (en) * | 2005-05-20 | 2006-10-02 | 삼성전자주식회사 | Manufacturing method of semiconductor device |
DE102005052000B3 (en) * | 2005-10-31 | 2007-07-05 | Advanced Micro Devices, Inc., Sunnyvale | Semiconductor device having a contact structure based on copper and tungsten |
US20070099360A1 (en) * | 2005-11-03 | 2007-05-03 | International Business Machines Corporation | Integrated circuits having strained channel field effect transistors and methods of making |
US7960838B2 (en) * | 2005-11-18 | 2011-06-14 | United Microelectronics Corp. | Interconnect structure |
KR100741882B1 (en) * | 2005-12-29 | 2007-07-23 | 동부일렉트로닉스 주식회사 | High voltage device and manufacturing method |
US7365009B2 (en) * | 2006-01-04 | 2008-04-29 | United Microelectronics Corp. | Structure of metal interconnect and fabrication method thereof |
US20070257323A1 (en) * | 2006-05-05 | 2007-11-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Stacked contact structure and method of fabricating the same |
KR100763514B1 (en) | 2006-06-30 | 2007-10-04 | 삼성전자주식회사 | A method of forming an opening in a semiconductor device and a method of manufacturing a semiconductor device using the same |
JP4575400B2 (en) * | 2007-05-08 | 2010-11-04 | 株式会社東芝 | Manufacturing method of semiconductor device |
KR100830591B1 (en) * | 2007-06-07 | 2008-05-22 | 삼성전자주식회사 | Method of Forming Semiconductor Device Including Openings |
DE102007057682A1 (en) * | 2007-11-30 | 2009-06-04 | Advanced Micro Devices, Inc., Sunnyvale | A hybrid contact structure with a small aspect ratio contact in a semiconductor device |
JP2009158591A (en) * | 2007-12-25 | 2009-07-16 | Nec Electronics Corp | Semiconductor device and manufacturing method thereof |
JP2010021295A (en) | 2008-07-09 | 2010-01-28 | Nec Electronics Corp | Semiconductor device and its manufacturing method |
US8058137B1 (en) * | 2009-04-14 | 2011-11-15 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
US20100308380A1 (en) * | 2009-06-05 | 2010-12-09 | International Business Machines Corporation | Dual damascene processing for gate conductor and active area to first metal level interconnect structures |
JP5671220B2 (en) * | 2009-08-25 | 2015-02-18 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
US8277674B2 (en) * | 2009-12-15 | 2012-10-02 | United Microelectronics Corp. | Method of removing post-etch residues |
-
2010
- 2010-12-14 US US12/968,068 patent/US8951907B2/en not_active Expired - Fee Related
-
2011
- 2011-09-14 SG SG10201400672TA patent/SG10201400672TA/en unknown
- 2011-09-14 SG SG2011066073A patent/SG182041A1/en unknown
- 2011-10-13 CN CN201110309959XA patent/CN102543848A/en active Pending
- 2011-10-13 CN CN201510683289.6A patent/CN105374672A/en active Pending
- 2011-10-26 DE DE102011085203.4A patent/DE102011085203B4/en not_active Expired - Fee Related
- 2011-11-16 TW TW100141769A patent/TWI462188B/en not_active IP Right Cessation
- 2011-11-24 KR KR1020110123809A patent/KR101331250B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
TWI462188B (en) | 2014-11-21 |
TW201225183A (en) | 2012-06-16 |
US20120146106A1 (en) | 2012-06-14 |
DE102011085203B4 (en) | 2018-08-23 |
CN105374672A (en) | 2016-03-02 |
CN102543848A (en) | 2012-07-04 |
KR101331250B1 (en) | 2013-11-20 |
KR20120066584A (en) | 2012-06-22 |
DE102011085203A1 (en) | 2012-06-14 |
SG182041A1 (en) | 2012-07-30 |
US8951907B2 (en) | 2015-02-10 |
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