RU2691757C1 - Multichannel digital excitatory system - Google Patents

Abstract

FIELD: radio engineering and communications.

SUBSTANCE: invention relates to radio engineering and communication and can be used in radio transmitting equipment. To achieve the technical result, the system is based on a single universal digital FPGA module, which includes different functional units which form coherent signals to provide the desired beam pattern. Control of the module operation mode and delivery of all information required for generation of the emitted signal are carried out through the interface unit over an Ethernet network and processed by a digital signal processor which generates a low-frequency quadrature signal. System implements direct synthesis of a radio frequency and transfer of a low-frequency quadrature signal to a working frequency, and a radio signal generated by digital methods is transmitted to a digital-to-analogue converter.

EFFECT: broader functional capabilities by implementing new modes of operation of promising radio links, improved methods of digital signal generation and noise immunity of radio communication.

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Description

The invention relates to the field of radio engineering and communications and can be used in radio transmitting equipment with frequency modulation and telegraphy modes operating in the ELF, ELF, SDV-DV, CB ranges for autonomous operation, as well as for operation in radio transmitter control systems.

The causative agent of a modern radio transmitter is a complex and expensive device, consisting generally of a frequency synthesizer that produces one or several output coherent oscillations with given frequencies, a former type of operation on a fixed subcarrier frequency and a transfer path of the generated oscillations in the working frequency range. The causative agent of the radio transmitter is characterized by the following main parameters: the frequency range of the operating oscillation, the nature of the change in the operating frequency, the total number of fixed frequencies, the instability of the frequency and phase, the level of the side spectral components, the characteristics of the control of the pathogen, the inertia of the rearrangement, the types of work, etc.

The rapid development of microelectronics, analog and digital microprocessor and computer equipment has a significant impact on the development of radio transmitting technology, both in terms of a sharp increase in functionality and in terms of improving its performance. This is achieved through the use of new principles for constructing block diagrams of transmitters and circuit design of individual nodes that implement digital methods of forming, processing and converting vibrations and signals.

In modern pathogens are widely used methods of digital signal generation. Known pathogens for radio transmitters, containing a modulator, a frequency synthesizer, an amplifier-conversion unit (the pathogen BO-71). Technical description ЯР2.209.011. THEN Tambov, 1973. The causative agent of the radio station AN / PRC-70. Collection of CIVTI MO USSR, 1973, no. 300, book 8, pp. 38-41. Pathogen GK-203C. HF SYNTHESISED DRIVER RECEIVER GK-205. 1973. Signal transmitter RU 2106061, containing a modulating signal generator, a frequency modulator, a simulated signal generator, a frequency multiplier unit, a terminating high-power amplifier stage with an output circuit.

Such pathogens have a high level of noise and discrete side components at the output, as well as low stability of the parameters of modulated oscillations in the range of modeling and operating frequencies. Therefore, such pathogens do not allow to implement increased requirements to the quality of the generated radio signals and the suppression of parasitic side oscillations at the output.

The closest in technical essence to the proposed system is the causative agent of the radio transmitter "Surf", developed and mass-produced by the Omsk Scientific-Research Institute. Specifications UIYAD.464117.004 TU. The “Surf” pathogen generates J3E, H3E, R3E, A1B, F1B, 3K40J1BEN radiation classes in the operating frequency range from 3 to 30 MHz, has an Ethernet digital input and an intermediate frequency output, and is intended for use in high-speed information transmission equipment complexes.

The excitation device is controlled remotely by one of the joints:

- on the joint of the IRPS (OST 11305.916-84);

- RS-232 in accordance with GOST 18145-81;

- RS-485;

- RS-422.

The “Surf” pathogen is made according to the superheteradin scheme with a single frequency conversion of 65.128 MHz.

The main functional modules of the pathogen are:

- digital modulator of telegraph and telephone signals;

- digital-to-analog converter;

- block conversion and amplification;

- frequency selector;

- frequency synthesis unit;

- control and indication unit;

- interface Ethernet block;

- Power Supply.

The disadvantage of the prototype is the low stability of the parameters of the output modulated oscillations (the level of deviation in the range of modulating operating frequencies) due to the use of two voltage control inputs of the generator for the implementation of frequency modulation and automatic frequency control.

The analysis of the level of technology has allowed to establish that the analogues, characterized by a set of features that are identical to all features of the claimed technical solution, are not in the known sources of information, which indicates that the claimed device complies with the condition of patentability "novelty."

Search results known solutions in this and related areas of technology in order to identify signs that match the distinctive features of the prototype features of the declared object, showed that they do not follow explicitly from the prior art. The prior art also revealed no prominence of the effect of the transformations envisaged by the essential features of the claimed invention on the achievement of the said technical result. Therefore, the claimed invention meets the condition of patentability "inventive step".

The aim of the invention is the extension of functionality through the implementation of new modes of operation of promising radio lines, the improvement of methods of digital signal generation and radio interference immunity.

This goal is achieved by the fact that the multi-channel digital excitation system containing the control and display unit, an Ethernet interface unit, a digital-to-analog converter module and a power source, the system is based on a single universal digital module (FPGA), which includes: clock signals, digital signal processor, synchronization and common time system, global navigation satellite system, ELF-ELF, SDL-DV and SV signal generator, digital-to-analog module a transducer, an external communication controller and a control module for code combinations, the system is built on the basis of a single universal digital module (FPGA), two such universal digital modules operate at a considerable distance from each other and generate coherent signals to provide the desired radiation pattern, and the entire control the mode of operation of the module and the delivery of all information necessary for the formation of the emitted signal is carried out via the interface unit via the Ethernet network and processed digitally a signal processor which generates a low-frequency quadrature signals, wherein the system is implemented in the radio frequency and direct synthesis transfer baseband quadrature signal to the operating frequency, and a fully formed digitally radio signal is supplied to digital-to-analog converter.

Due to the new set of essential features in the claimed device due to the fact that the system is built on the basis of a single universal digital module (FPGA), which includes various functional units that form coherent signals to provide the desired radiation pattern. The mode of operation of the module and the delivery of all the information necessary for the formation of the emitted signal are controlled via the interface unit via the Ethernet network and processed by a digital signal processor that generates a low-frequency quadrature signal. And also due to the fact that the system implements direct radio frequency synthesis and the transfer of a low-frequency quadrature signal to the operating frequency, and the radio signal fully generated by digital methods is fed to a digital-analog converter. Thus, it is possible to achieve a formulated technical result: expanding the functionality by implementing new modes of operation of promising radio lines, improving methods of digital signal generation and noise immunity of radio communications.

FIG. 1 is a functional diagram of the MFCS, which is built on the basis of a single universal digital FPGA module (1). The schema contains:

1 - a single universal digital FPGA module;

2 - clock generation module;

3 - digital signal processor;

4 and 5 - the shaper of the signals of ELF-VLF, SDV-DV and ST ranges;

6 - digital-to-analog converter control module;

7 - external communication controller;

8 - control module code combinations;

9 - control and indication device;

10 - synchronization system and a single time;

11 - global navigation satellite system;

12 - Ethernet interface unit;

13 - power supply unit.

The clock generation module (2) provides the DAC clocking signal generation and 25 MHz REFCLK clock generation.

The block diagram of the clock generation module is presented in FIG. 2. It contains:

14 is a chip forming the clock signals CDCE72010;

15 - reference generator 10 MHz GK211-TS;

16 - microcircuit 1432UU1V;

17 - digital-to-analog converter 1273PA71 544UD16U3;

18 - ELASH ROM microcontroller with 1887BE1U program;

19 - linear stabilizer (STU);

20 - comparator ADCMP572;

21 - low pass filter;

22 - quartz oscillator VCO 250 MHz SiS50.

Clocking signals are generated as differential pairs of the PEKL standard. As a reference signal, the module uses a signal with a frequency of 10 MHz, formed either by the built-in generator GK211-TS (15), or coming from the external connector “10 MHz Bx”. In addition, the output signal of the generator through the buffer on the chip 1432UU1V (18) is fed to the output connector of the module "10 MHz Out". The choice of operating mode, as well as adjustment of the nominal frequency of the generator GK211-TS (15) is made by commands received via the I ² C interface.

2. The clock generation module (2) ensures a high frequency stability and a low level of phase noise, since these characteristics greatly influence the quality of the ICVS as a whole. On this basis, an ultra-precision low-noise temperature-controlled quartz oscillator of the type GK211-TS-10M-5E-10 / AT-B (15) was chosen as the reference. The output frequency is adjusted within the adjustment range using a digital-to-analog converter (17), built on the basis of a parallel DAC chip with a 1273P7171 current output and an 544UD16U3 operational amplifier.

From the output of the reference generator, a sinusoidal signal is fed to one of the inputs of the reference frequency of the chip shaper CDCE72010 (14). The structure of this chip, in addition to the clock distribution system, consisting of output dividers and buffers, includes a phase-locked loop (PLL) subsystem and control circuit. The phase-locked loop subsystem includes two reference signal buffers (PR1 REF, SEC REF), a phase detector (PFD), a divider output frequency of the controlled oscillator, and a control voltage generation circuit. The control & control circuit (Interface & Control) provides for the adjustment of the operating mode of the microcircuit via the SPI interface or by means of dedicated pins.

Chip CDCE72010 (14) provides the ability to work with controlled oscillators with frequencies up to 1500 MHz. The maximum frequency of the reference signal is 500 MHz. Output buffers form up to 10 differential signals (LUPECL, LV8S) or 20 LVCMOS signals. Output dividers provide frequency division of the controlled oscillator with coefficients of 1 ... 6, 8, 10, 12, 16, 20, etc. up to 70 or 80 for each channel independently. The microcircuit provides an ultra-low level of phase noise and can use as an effective device the reduction of clock jitter with a narrow PLL filter bandwidth. The external frequency of the standard 10 MHz is fed to the comparator (20) and further to the chip CDCE72010 (14).

As controlled oscillator in the PLL uses a voltage controlled crystal oscillator (VCXO) SiS50 (22) at a supply voltage of 3.3 V and a nominal frequency of 250 MHz frequency provides temperature stability better than 5⋅10 ^-7 at a temperature range of -40 to +85 degrees WITH.

The clock source is a quartz resonator (CW), which provides high frequency stability and reliability. The frequency synthesizer performs the process of generating oscillations of the required frequency, as well as filtering noise.

Control of the clock signal module is provided using a single-chip microcontroller with a FLASH ROM program 1887BEV1U (18).

The power supply of the module elements is carried out with a voltage of +3.3 V, which is formed with the help of the built-in high-speed linear regulator (19). Such a power scheme can significantly reduce the influence of interference arising from the operation of the remaining modules on the clock generation module (2).

The characteristic of suppressing voltage pulsations with an ADR3338-3.3 microcircuit in the frequency range up to 1 MHz is shown in FIG. 3

The DSP (3) digital signal processor supports the network communication protocol and digitally generates all the necessary signals. The structure of the DSP digital signal processor is shown in FIG. 4. It contains:

23 - RS-232 1 port;

24 - RS-232 2 port;

25 - switch “Mode” boot;

26 - NORFLASH $ dynamic memory chip;

27 - Ethernet port;

28 - chip (Protocol) DR83640 IEEER1588 $;

29 - power source.

The basis of the digital signal processor is a chip type MT47H64M16HR and NOR FLASH. It is designed to store programs. There are 2 RS-232 ports (23-24) in the system. The first port (23) is used to receive information from the CEB (single-time system) hardware, debugging and programming FLASH targets, and the infrared remote control receiver is connected to the second (24). The boot mode switch (25) is used to test and write software in NOR FLASH. To do this, the boot mode is selected via the RS-232 interface and a test program is loaded into the DSP digital signal processor, which performs an initial check of the device’s operability and programs NOR FLASH. In normal operation mode, software download to DSP comes from NOR FLASH (26).

The digital signal processor DSP has two main tasks in the MFCS: support of network protocols for data transmission, control over an Ethernet network (27) and generation of all radiated signals in a digital form.

In the low-frequency part of the range (ELF-VLF), the digital signal processor DSP programmatically generates all reference points of the emitted signal, which without further digital processing in the FPGA are transmitted to the digital-to-analog converter or fed into one of the blocks and the “digital signal generator” and transmitted via fiber optic cable to remote transmitter or MCCS operating in the “slave” mode.

In the high-frequency part of the range (SDV-DV and SV), the digital signal processor DSP implements a complex signal by software, that is, a signal transferred to zero frequency. This complex signal is transferred to the FPGA at the operating frequency and fed to the DAC or to one of the “digital signal shaper” units and transmitted via a fiber optic cable to the remote transmitter or MSCS operating in the “slave” mode.

1. A single universal digital FPGA module (1) serves to connect all parts of the system and performs time-critical actions, clock synchronization, generation of clock signals, generation and transfer of the radio frequency signal to high frequencies (for SDV-DV and SV bands).

3. The digital signal processor (3) generates a complex signal in the I and Q channels, which is fed to the input of the digital upconverter and is implemented on the FPGA. Both channels of the signal pass through several filter stages - interpolators, are multiplied by the I and Q signals of the digital local oscillator and after addition form a output signal transferred to the NCO frequency.

Another important task solved in FPGA is synchronization of work of several pathogens. The system can operate in two modes:

- there is one central MSCS and it transmits via a fiber-optic cable through two “digital signal shaper” blocks to two transmitters fully-formed signals for transmission. In this mode, synchronization is not required, since the signal for the transmitter is transmitted over a fiber-optic cable with a very small and fixed delay;

- the signals generated for transmitters are transmitted between pathogens via the Ethernet network (27). In this case, you need to organize the synchronization of the clock of two or more pathogens. The clocks are implemented on the FPGA and represent a DDS direct frequency synthesizer counter, the frequency and phase of which are adjusted by the synchronization signals. For synchronization, the Ethernet network (27) and the IEEE 1588 protocol are used. Another synchronization method is the use of the time stamp of the synchronization system and the single time of the CET (10).

4. The shaper of the signals of the ELF-VLF ranges (4) contains three channels: two digital and one analog. Digital channels are primary, and analog is optional. Digital channels are designed to transmit radio frequency signals and synchronize to power amplifiers over single-mode fiber. Signals can be transmitted without interference for several tens of kilometers. This allows you to connect two remote transmitters to one exciter and ensure their synchronous operation. The basis of the digital channel is a DS 90C241 microcircuit - a 24-bit parallel digital code converter into a high-speed serial data stream. The module ROM-622 is used for data transmission over fiber.

5. Shaper signals SDV-DV and CB ranges (5) contains three channels: two digital and one analog. Digital channels are primary, and analog is optional. Digital channels are designed to transmit radio frequency signals and synchronize to power amplifiers over single-mode fiber. A fully formed digital data stream comes from the FPGA to the DAC. The received analog signal passes through a low-pass filter and is fed to a radio signal amplifier. The low-pass filter reduces the level of out-of-band noise, and the amplifier brings the signals to the desired level.

6. Digital-to-analog converter control module (6). This unit is used to monitor and control transmitted signals using external measurement equipment. DA07821 with a bit width of 12 bits and a speed of 20.4 MSPS was used as a DAC.

7. External communications controller ICAC (7). Controller C1-TG performs the function of the interface for receiving telegraph signals. It is a level converter of ± 20 V to low-voltage logic signals. The switching threshold is not more than 2 V, the output resistance is 1 kΩ. It is implemented on the LM 339 comparator. The controller C1-PM performs the function of a junction for receiving signals of tone telegraphy. The tone telegraphy signal is data transmitted in an audio frequency range of 300-3500 Hz. The signals of the PM channel pass the input circuits that are needed to protect the input of the device, while the transformer provides galvanic isolation and goes to the AD73322 codec, which converts them into digital form. Data from the AD73322 codec is sent to the FPGA and transmitted to the MOBSP port of the signal processor. The AD73322 codec is dual-channel, so two PM channels can be connected to the MCHCS. RS-485 controller. Three RS-485 channels are used to command and control the ICVS operation. RS-485 channel data is processed by a signal processor. The ADM2682E chip is selected as a driver for RS-485 signals. This chip provides a transfer rate of 16 Mbps, has galvanic isolation and an integrated power supply.

8. Code Code Control Module (8). This module consists of 5 digital inputs coming to the FPGA. It allows you to switch the MCCS operating mode by changing the code combination installed on these inputs.

9. The control and display device (9) consists of a keyboard (4x4 matrix) and a liquid crystal display. It allows you to enter commands and switch the ICVS mode of operation. The control circuit ICVS implemented on the FPGA.

10. The system of synchronization and common time CET (10) provides the possibility of joint work of several pathogens. That is, time, frequency, and phase synchronization in the ELF-VLF band uses several synchronization channels: the main one is transmission via an optical cable and additional channels via the Ethernet network and GLONAS / GPS channels.

11. The global navigation satellite system (11) provides the possibility of joint work of several pathogens.

12. The Ethernet interface unit (12) provides:

- physical interfacing via IEEE 802.3 (Fast Ethernet) 100 Base TX Ethernet. 9 unshielded twisted pair (UTP);

- data transmission from the Ethernet network unit to the modulator via a synchronous serial interface at LVDS levels;

- two-way exchange of commands (messages) with the CU in asynchronous mode in the start-stop code in accordance with the developed communication protocol.

13. Power supply unit (13). Depending on the type of use of the MCVS (as part of a complex or autonomously), the power supply of the MCVS is provided either from the supply voltage set of the on-board network or from a single-phase AC network of 220 V with a frequency of 50 Hz. The power supply unit is designed to provide nodes MTSVS voltage circuits +24 V, -24 V, +12 V, +5 V, +3.3 V, formed from the primary input voltage.

The use of the MFCS allows the software to be changed in order to implement new modes of operation of promising radio links. Updates to the functionality of the ICVS are carried out using a single interface.

MCCS provides the following control modes:

- local control via the infrared port object network interfaces from a portable control device;

- “remote control” through the module object network interfaces.

The MCCS has a 10 MHz signal input and output, providing additional operation of one pathogen to another pathogen from the reference generator. MCCS provides full-time operation of the WDU in the conditions of industrial interference. The control outputs of the MSCS provide for the connection of fiber-optic cables.

MCVS is made on the basis of Profiset crate according to GOST 28601.3-90. The placement of the components is made on the basis of the supporting structure of the EUROPAC series.

Used in the proposed multichannel digital excitatory system, the software of the control and display device (BL. 8 of Fig. 1) made it possible to implement all operating modes of currently used radio lines, including those missing in the prototype of radio lines with phase shift keying (MPSK is phase shift keying and coherent detection, MDPSK - phase shift keying and differential coherent detection) with better noise immunity with respect to other manipulation methods (Muravchenko VL Pairs rating Ametrov digital information transmission channels. Radiotekhnika, 2011, No. 11. Katanovich A.A., Muravchenko V. L. Automation of the control of the naval communications complexes in the ship.-SPb .: Shipbuilding, 2014. 216 p.).

The use of a multichannel digital excitation system of signals of the unified time system (CET) and the Global Navigation Satellite Communication System expanded the functionality of the excitation devices, namely, increasing the accuracy of setting the operating frequency and realizing the formation of radiation patterns by ensuring the required phase shifts. oscillations of excitatory devices included in a multichannel digital excitatory system are essentially a continuation of the improvement of digital signal generation methods.

When developing a digital excitatory system, the known principles of construction and block diagrams of transmitting devices of digital systems are used. (Pershin VT. The formation and generation of signals in digital radio communications: - Minsk: INFRA-M, 2013. 614 p. Vasin VA, Kalmykov VV, Sebekin Yu.N., Senin AI, IB Fedorov, Radio Information Transmission Systems. - M .: Hotline - Telecom, 2005. 472 p.)

All technical solutions proposed in the application were implemented in the device (name) created at the enterprise - the applicant and passed the tests with a positive result.

Thus, the proposed circuit solutions allow us to conclude that the MHCCS provides enhanced functionality, improved new modes of operation of promising radio links and radio interference immunity.

Claims (1)

A multichannel digital excitatory system containing a control and display unit, an Ethernet interface unit, a digital-to-analog converter module and a power supply, characterized in that the system is based on a single universal digital module (FPGA) which includes: a clock generation module, a digital signal processor, system of synchronization and common time, global navigation satellite system, ELF-VLF, SDV-DV and SV signal generator, digital-to-analog converter module, k external communication controller and software control module in accordance with the software, with a single universal digital module (FPGA) connected to the clock generation module (FPGA) with a synchronization system and a single time that is connected to the global navigation satellite system and the interface unit - Ethernet network, which is connected to a single universal digital module (FPGA) and digital signal processor, which in turn is connected to a control and display device and a single un The versatile digital module (FPGA), the latter is connected to the control and display device, as well as the ELF-ELF, SDL-DV and SV signal generator, the external communication controller, the digital-to-analog converter module and the code combination control module, two such universal digital modules work at a considerable distance from each other and form coherent signals to provide the desired radiation pattern, and all control of the module operation mode and delivery of all the information necessary for the formation and The emitted signal is carried out via the interface unit via the Ethernet network and processed by a digital signal processor that generates a low-frequency quadrature signal, the system implements direct radio frequency synthesis and transfers the low-frequency quadrature signal to the operating frequency, and the fully digital radio signal is fed to a digital-to-analog converter.

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