JP2005303632A - Data communications system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data communications system with high transmission quality, while minimizing the number of crystal oscillators and ceramic oscillators used to be an absolute required minimum in number. <P>SOLUTION: A master apparatus 100 calculates a main clock frequency, generated by a transmission source slave apparatus 200 of a received signal Rx_M, on the basis of the received signal Rx_M received from the slave apparatus 200 and generates a carrier adjustment signal Creg on the basis of the frequency fcs. Each slave apparatus 200 adjusts an input signal voltage of a clock generating section 206 in own apparatus, on the basis of the carrier adjustment signal Creg received from the master apparatus 100 so as to match an oscillated frequency fs of the main clock generating section 206 of its own apparatus with the oscillated frequency fm of a main clock generating section 102 of the master apparatus 100. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a data communication system in which a main clock frequency of another transmitting / receiving device is corrected based on a transmission signal generated by one transmitting / receiving device.

  In general, in a data communication system in which a master-side transmission / reception device and a plurality of slave-side transmission / reception devices communicate bidirectionally, as shown in FIG. 8, each of the transmission / reception devices 6-1 to 6-4 is a crystal oscillator or a ceramic oscillation The transmitter / receiver 7 is mounted, and each of the transmission / reception devices 6-1 to 6-4 performs signal processing using a transmission signal of each oscillator as a main clock, thereby performing data communication. Since crystal oscillators and ceramic oscillators have high oscillation frequency accuracy and low temperature dependence, they are used as the main clocks of the respective transmission / reception devices. As a result, even if the software processing of the communication unit is shared and simplified by each transmission / reception device, it is possible to realize communication with a low transmission error and a low code error rate.

In general, in a half-duplex communication type data communication system using a single carrier signal, as shown in FIG. 8, each of the transmission / reception devices 6-1 to 6-4 has a crystal oscillator or a ceramic oscillator 7 respectively. And each of the transmission / reception devices 6-1 to 6-4 performs data communication by using the oscillation signal of each oscillator 7 as a carrier signal. Since crystal oscillators and ceramic oscillators have high oscillation frequency accuracy and low temperature dependency, they are used as oscillators for generating carrier signals, and oscillators having the same oscillation frequency are connected to each of the transmission / reception devices 6-1 to 6- By installing it in 4, communication with high transmission quality with a small code error rate and the like can be realized. (See Patent Documents 1 and 2)
JP-A-10-276105 Japanese Patent Laid-Open No. 10-285027

  However, since crystal oscillators and ceramic oscillators are very expensive compared to LC oscillation circuits, RC oscillation circuits, and the like, a data communication system can be obtained by mounting such expensive components on each transmission / reception device. There is a problem that the overall cost of the system becomes high.

  The present invention has been made in view of the above circumstances, and an object thereof is to realize a data communication system with high transmission quality while minimizing the number of crystal oscillators and ceramic oscillators used.

In order to achieve the above-described object, a data communication system according to the present invention includes:
In a data communication system in which a master-side transceiver device and a plurality of slave-side transceiver devices communicate bidirectionally,
The transmitting / receiving device on the master side
A main clock generator for generating a main clock signal with high frequency accuracy;
A data rate setting unit that sets a transmission rate of transmission data by dividing the main clock signal generated by the main clock generation unit according to a constant C;
A signal processing unit for receiving and processing a received signal;
An SMC frequency information detection unit that reads main lock frequency information on the slave side included in the received signal from the transmission / reception device on the slave side;
An SMC adjustment signal generator that generates an adjustment signal for adjusting the main lock frequency of the corresponding transmission / reception device on the slave side to the same frequency as the master, based on the main lock frequency information on the slave side;
A transmission data generation unit that generates transmission data based on the signals generated by the data rate setting unit and the SMC adjustment signal generation unit,
Multiple slave side transceivers
A signal processing unit for receiving and processing a received signal;
An SMC adjustment signal detection unit that detects an SMC adjustment signal included in a reception signal from a master-side transmission / reception device;
A main lock adjustment unit that generates an adjustment signal for adjusting the main clock frequency of the own transmission / reception device to be the same as that of the master based on the SMC adjustment signal detected by the SMC adjustment signal detection unit;
A main lock generator having a lower frequency accuracy and frequency stability than the main clock generator on the master side, which can adjust the main lock frequency of the own transmission / reception device according to the adjustment signal from the main lock adjustment unit;
A data rate setting unit that sets a transmission rate of transmission data by dividing the main lock signal generated by the main lock generation unit according to a constant C;
A transmission data generation unit that generates transmission data at a transmission rate set by the data rate setting unit;
A data communication system comprising:

In order to achieve the above-described object, a data communication system according to the present invention includes:
In a data communication system in which a master-side transmission / reception device and a plurality of slave-side transmission / reception devices perform modulation / demodulation using a single carrier signal and perform bidirectional communication, the master-side transmission / reception device includes:
A main clock generator for generating a main clock signal with high frequency accuracy;
A data rate setting unit that sets a transmission rate of transmission data by dividing the main clock signal generated by the main clock generation unit according to a constant C;
A carrier signal generation unit that generates a carrier signal by performing signal processing on the main clock signal generated by the main clock generation unit;
A demodulator that demodulates the modulated received signal;
A signal processing unit that processes the demodulated received signal;
An SMC frequency information detector that reads main clock frequency information on the slave side included in the received signal from the transmission / reception device on the slave side;
An SMC adjustment signal generation unit that generates an adjustment signal for adjusting the main clock frequency of the corresponding transmission / reception device on the slave side to the same frequency as the master, based on the main clock frequency information on the slave side;
A transmission data generation unit that generates transmission data based on signals generated by the data rate setting unit and the SMC adjustment signal generation unit;
A modulation unit that generates a transmission signal modulated based on the signal generated by the transmission data generation unit and the carrier signal generation unit, and
Multiple slave side transceivers
A demodulator that demodulates the modulated received signal;
A signal processing unit that processes the demodulated received signal;
An SMC adjustment signal detection unit that detects an SMC adjustment signal included in a reception signal from a master-side transmission / reception device;
Based on the SMC adjustment signal detected by the SMC adjustment signal detection unit, a main clock adjustment unit that generates an adjustment signal for adjusting the main clock frequency of the own transmitting / receiving device to be the same as that of the master,
A main clock generator having a lower frequency accuracy and frequency stability than the main clock generator on the master side, which can adjust the main clock frequency of the own transmission / reception device according to the adjustment signal from the main clock adjustment unit;
A data rate setting unit that sets a transmission rate of transmission data by dividing the main clock signal generated by the main clock generation unit according to a constant C;
A transmission data generation unit that generates transmission data at a transmission rate set by the data rate setting unit;
A carrier signal generation unit that generates a carrier signal by performing signal processing on the main clock signal generated by the main clock generation unit;
A modulation unit that generates a transmission signal modulated based on the signals generated by the transmission data generation unit and the carrier signal generation unit;
It is characterized by having.

In order to achieve the above-described object, a data communication system according to the present invention includes:
In a data communication system in which a plurality of transmission / reception devices perform half-duplex communication with each other using a single carrier signal,
One of the plurality of transmission / reception devices functions as a master device, and other devices function as slave devices,
The master device is
A main clock generator that oscillates a main clock signal using a crystal oscillator or a ceramic oscillator;
A carrier signal generator for generating a carrier signal from the main clock signal;
Based on the received signal, a carrier frequency calculating unit that calculates the frequency of the carrier signal generated by the transmission source slave device of the received signal;
An adjustment signal generator that generates a carrier adjustment signal based on the frequency calculated by the carrier frequency calculator;
A transmission unit for transmitting the carrier adjustment signal to the transmission source slave device,
The slave device is
A clock generator for oscillating a clock signal at an oscillation frequency corresponding to the input signal voltage;
A carrier signal generator for generating a carrier signal from the clock signal;
A receiver for receiving the carrier adjustment signal;
A clock adjustment unit that adjusts the input signal voltage of the clock generation unit based on the carrier adjustment signal so that the oscillation frequency of the clock generation unit matches the oscillation frequency of the main clock generation unit of the master device. It is characterized by that.

  In the data communication system configured as described above, the master device calculates the frequency of the carrier signal generated by the transmission source slave device of the received signal based on the received signal received from the slave device, and the frequency Based on the above, a carrier adjustment signal is generated, and the carrier adjustment signal is transmitted to the transmission source slave device. The slave device adjusts the input signal voltage of the main clock generation unit in its own device based on the carrier adjustment signal received from the master device, so that the oscillation frequency of the main clock generation unit in its own device is adjusted to the main frequency of the master device. Match the oscillation frequency of the clock generator.

  In the data communication system of the present invention, if the master device includes a crystal oscillator or a ceramic oscillator for generating a reference carrier signal, an RC oscillation circuit or an LC oscillation circuit can be used as an oscillation means mounted on each slave device. Therefore, it can be realized at a low cost by minimizing the number of crystal oscillators and ceramic oscillators used.

  The present invention has been briefly described above. Furthermore, the details of the present invention will be further clarified by reading through the best mode for carrying out the invention described below with reference to the accompanying drawings.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described in detail with reference to the drawings.

  FIG. 1 is a conceptual diagram showing a configuration example of a data communication system according to the present invention, and a plurality of (four in the illustrated example) transmission / reception devices 1-1, 1-2, 1- connected to be communicable with each other. 3 shows an example of a system configuration in which one transmission / reception device 1-1 of 1-4 is functioning as the master device 100, and the other devices are each functioning as the slave device 200. This data communication system forms part of an in-vehicle communication system based on a LIN (Local Interconnect Network) protocol using power line communication (PLC), and a power line 2 for supplying power to in-vehicle devices. Is used for the signal transmission path to perform data communication for controlling the in-vehicle device. In communication using the LIN protocol, a sync field (Synch-Field) and a sync break (Synch-Break) are transmitted as a preamble before the frame header (ID-Field) (see FIG. 2).

  FIG. 3 is a block diagram showing a configuration example of a master device and a slave device in the data communication system according to the present invention.

  The master device 100 includes a main clock generation unit 102 that incorporates a crystal oscillator 101. The main clock generation unit 102 outputs a transmission signal of the crystal oscillator 101 as a main clock signal CLK_M (frequency fm). The main clock signal CLK_M is input to the data rate setting unit 104. The data rate setting unit 104 sets the transmission rate of transmission data by dividing the main clock signal CLK_M according to the constant C. The set value is input to the transmission data generation unit 105.

  The SMC frequency information detection unit 120 reads the main lock frequency information on the slave device 100 side included in the received signal and provides the information to the SMC adjustment signal generation unit 121. Note that “SMC” is an abbreviation for “main clock mounted on slave device”.

  The SMC adjustment signal generation unit 121 adjusts the main lock frequency fs on the slave device 100 side to the same frequency as the master device 100 based on the main lock frequency information given from the SMC frequency information detection unit 120. A signal is generated and given to the transmission data generation unit 105.

  The transmission data generation unit 105 generates transmission data TX_M based on the setting value by the data rate setting unit 104 and the adjustment signal generated by the SMC adjustment signal generation unit. The transmission data TX_M is sent to the power line 2.

  On the other hand, a signal transmitted from the slave device 200 via the power line 2 is input to the signal processing unit 109 and subjected to signal processing.

  The slave device 200 includes a VCO formed of an RC oscillation circuit or an LC oscillation circuit using a variable capacitance diode as a main clock generation unit 209. In the slave device 200, the signal Rx_S transmitted via the power line 2 is input to the signal processing unit 203 and the SMC adjustment signal detection unit 250. The signal processing unit 203 processes the reception signal Rx_S.

  The SMC adjustment signal detection unit 250 detects the SMC adjustment signal included in the reception signal from the master device 100 and supplies it to the main lock adjustment unit 205.

  The main lock adjustment unit 205 generates an adjustment signal for adjusting the main clock frequency fs of the slave device 200 to be the same as the main clock frequency fm of the master device 100 based on the SMC adjustment signal, and generates the adjustment signal as the main lock generation unit 209.

  The main lock generation unit 209 sends the generated main lock signal CLK_S to the data rate setting unit 207 while adjusting the main lock frequency according to the adjustment signal from the main lock adjustment unit 205.

  The data rate setting unit 207 sets the transmission rate of transmission data by dividing the main lock signal CLK_S generated by the main lock generation unit 209 according to the constant C, and sends it to the transmission data generation unit 212.

  The transmission data generation unit 212 generates transmission data TX_S at the transmission rate set by the data rate setting unit 207.

  FIG. 4 is a block diagram showing another configuration example of the master device and the slave device in the data communication system according to the present invention.

  The master device 100 includes a main clock generation unit 102 that incorporates a crystal oscillator 101. The main clock generation unit 102 outputs a transmission signal of the crystal oscillator 101 as a main clock signal CLK_M (frequency fm). The main clock signal CLK_M is input to the data rate setting unit 104 and the carrier signal generation unit 103. The data rate setting unit 104 sets the transmission rate of transmission data by dividing the main clock signal CLK_M according to the constant C. The set value is input to the transmission data generation unit 105.

  The carrier signal generation unit 103 processes the main clock signal CLK_M generated by the main clock generation unit 101 to generate a carrier signal C_M.

  A signal transmitted from the slave device 200 via the power line 2 is input to the demodulation unit 108 through the band filter 107. The received signal demodulated by demodulator 108 is input to signal processor 109 and SMC frequency information detector 120. The signal processing unit 109 performs signal processing on the received signal.

  The SMC frequency information detection unit 120 reads the main lock frequency information on the slave device 100 side included in the received signal and provides the information to the SMC adjustment signal generation unit 121.

  The SMC adjustment signal generation unit 121 adjusts the main lock frequency fs on the slave device 100 side to the same frequency as the master device 100 based on the main lock frequency information given from the SMC frequency information detection unit 120. A signal is generated and given to the transmission data generation unit 105.

  The transmission data generation unit 105 generates transmission data TX_M based on the setting value by the data rate setting unit 104 and the adjustment signal generated by the SMC adjustment signal generation unit 121. Transmission data TX_M and carrier signal C_M are sent to modulation section 106.

  The modulation unit 106 modulates the carrier signal C_M according to the transmission data Tx_M. The output signal of the modulation unit 106 is sent to the power line 2 through the band filter 107.

  The slave device 200 includes a VCO formed of an RC oscillation circuit or an LC oscillation circuit using a variable capacitance diode as a main clock generation unit 209. In the slave device 200, a signal transmitted via the power line 2 is input to the demodulation unit 202 through the band filter 201. The demodulator 202 demodulates the received signal Rx (see FIG. 7). The demodulated reception signal Rx_S is input to the signal processing unit 203 and the SMC frequency information detection unit 250. The signal processing unit 203 processes the reception signal Rx_S.

  The SMC frequency information detection unit 250 detects an SMC adjustment signal included in the reception signal Rx_S.

  Based on the SMC adjustment signal detected by the SMC frequency information detection unit 250, the main clock adjustment unit 251 adjusts the main clock frequency fs of the slave device 200 to be the same as the main clock frequency fm of the master device 100. Generate a signal. The generated adjustment signal is sent to the main clock generation unit 209.

  The main clock generation unit 209 generates the main clock signal CLK_S (fs) while adjusting the main clock frequency fs of the slave device 200 according to the adjustment signal from the main clock adjustment unit 251. The generated main clock signal CLK_S (fs) is sent to the data rate setting unit 210 and the carrier signal generation unit 211.

  The data rate setting unit 210 sets the transmission rate of the transmission data TX_S by dividing the main clock signal CLK_S (fs) generated by the main clock generation unit 209 according to the constant C. The set value is passed to the transmission data generation unit 212.

  The transmission data generation unit 212 generates transmission data TX_S at the transmission rate set by the data rate setting unit 210. The carrier signal generation unit 211 performs signal processing on the main clock signal CLK_S generated by the main clock generation unit 209 to generate a carrier signal C_S. Transmission data TX_S and carrier signal C_S are sent to modulation section 213.

  The modulation unit 213 modulates the carrier signal C_M according to the transmission data Tx_M. The output signal of the modulation unit 213 is sent to the power line 2 through the band filter 201.

  FIG. 5 is a block diagram showing still another configuration example of the master device and the slave device in the data communication system according to the present invention.

  The master device 100 includes a main clock generation unit 102 that incorporates a crystal oscillator 101. The main clock generation unit 102 outputs a transmission signal of the crystal oscillator 101 as a main clock signal CLK_M (frequency fm). The main clock signal CLK_M is input to the carrier signal generation unit 103 and the data rate setting unit 104. The carrier signal generation unit 103 generates a carrier signal C_M having a predetermined frequency fcm by dividing the main clock signal CLK_M.

  The data rate setting unit 104 divides the main clock signal CLK_M by a constant C. The set value is input to the transmission data generation unit 105.

  The modulation unit 106 modulates the carrier signal C_M according to the transmission data Tx_M. The output signal of the modulation unit 106 is sent to the power line 2 through the band filter 107.

  On the other hand, the signal Rx transmitted from the slave device 200 via the power line 2 is input to the demodulation unit 108 through the band filter 107. The demodulator 108 demodulates the received signal Rx (see FIG. 7). The reception signal Rx_M demodulated by the demodulation unit 108 is input to the signal processing unit 109 and the data rate measurement unit 110. The signal processing unit 109 executes a load control process or the like according to the received signal.

  The carrier frequency calculation unit 111 calculates the frequency fcs of the carrier signal C_S of the transmission source slave device 200 based on the data rate ys obtained by the data rate measurement unit 110. The output of the carrier frequency calculation unit 111 is input to the carrier adjustment signal generation unit 112.

  The carrier adjustment signal generator 112 generates a carrier adjustment signal Creg based on the value calculated by the carrier frequency calculator 111. The output of the carrier adjustment signal generation unit 112 is input to the transmission data generation unit 105. The transmission data generation unit 105 generates transmission data Tx_M including the carrier adjustment signal Creg addressed to the transmission source slave device 200. Transmission data Tx_M including the carrier adjustment signal Creg is transmitted to the transmission source slave device 200 via the modulation unit 106, the band filter 107, and the power line 2.

  The slave device 200 includes, as the main clock generation unit 206, a VCO including an RC oscillation circuit or an LC oscillation circuit using a variable capacitance diode. In the slave device 200, a signal transmitted via the power line 2 is input to the demodulation unit 202 through the band filter 201. The demodulator 202 demodulates the received signal Rx. The demodulated reception signal Rx_S is input to the signal processing unit 203 and the main clock state detection unit 204. The signal processing unit 203 executes a load control process or the like according to the received signal Rx_S.

  The clock state detection unit 204 analyzes the carrier adjustment signal Creg in the reception signal Rx_S, and generates and outputs a control signal according to the analysis result. This control signal is generated based on the carrier adjustment signal Creg so that the oscillation frequency fs of the clock generation unit 206 matches the oscillation frequency of the main clock generation unit 102 of the master device 100. The output of the main clock state detection unit 204 is input to the main clock frequency adjustment unit 205.

  The main clock frequency adjusting unit 205 outputs a voltage signal corresponding to the control signal from the main clock state detecting unit 204. The output of the main clock frequency adjustment unit 205 is input to the main clock generation unit 206.

  The clock generation unit 206 outputs a clock signal CLK_S having a frequency fs corresponding to the input signal voltage from the clock frequency adjustment unit 205. The frequency fs of the clock signal CLK_S generated by the clock generation unit 206 is adjusted by adjusting the input signal voltage of the clock generation unit 206 according to the carrier adjustment signal Creg from the master device 100. The frequency is adjusted to match the frequency fm of the clock signal CLK_M generated by 102. The clock signal CLK_S output from the clock generation unit 206 is input to the data rate setting unit 207 and the carrier signal generation unit 208.

  The data rate setting unit 207 sets the transmission data rate by dividing the clock signal CLK_S generated by the clock generation unit 206 according to the constant C. The set value is input to the transmission data generation unit 208. The transmission data generation unit 208 generates transmission data Tx_S. The carrier signal generation unit 208 generates a carrier signal C_S having a predetermined frequency fcs (= fcm) by dividing the clock signal CLK_S. Carrier signal C_S and transmission data Tx_S are sent to modulation section 209. The modulation unit 209 modulates the carrier signal C_S according to the transmission data Tx_S. The output signal of the modulation unit 209 is sent to the power line 2 through the band filter 201.

  As described above, in the data communication system according to this embodiment, the master device 100 generates the main clock generated by the transmission source slave device 200 of the received signal Rx_M based on the received signal Rx_M received from the slave device 200. A frequency is calculated, and a carrier adjustment signal Creg is generated based on the frequency fcs. Each slave device 200 adjusts the input signal voltage of the clock generation unit 206 in its own device based on the carrier adjustment signal Creg received from the master device 100, thereby oscillating the main clock generation unit 206 in its own device. fs is matched with the oscillation frequency fm of the main clock generation unit 102 of the master device 100.

  Therefore, according to this data communication system, the clock signal CLK_S of each slave device 200 is converted to an expensive crystal while using an inexpensive device such as an RC oscillation circuit or an LC oscillation circuit for the main clock generation unit 206 of each slave device 200. Since it can be made to coincide with the main clock signal CLK_M of the master device 100 including the vibrator 101, a data communication system with high transmission quality can be realized at a low cost, equivalent to the case where the crystal vibrator 101 is mounted on all transmission / reception devices. .

  The main clock signal adjustment processing of each slave device 200 can be adjusted sequentially during data communication for performing actual load control or the like.

  The present invention is not limited to the above-described embodiments, and modifications, improvements, etc. can be made as appropriate. In addition, the configuration, the number, the arrangement location, and the like of each component in the above-described embodiment are arbitrary and are not limited as long as the present invention can be achieved.

  In the above embodiment, the data communication system using the PLC has been described as an example. However, it goes without saying that the present invention can also be applied to a data communication system using a dedicated transmission line. Further, the communication protocol to be used is not limited to LIN.

It is a conceptual diagram which shows the structural example of the data communication system concerning this invention. It is a figure which shows the frame structure in the communication by a LIN protocol. It is a block diagram which shows the structural example of the master apparatus in the data communication system concerning this invention, and a slave apparatus. It is a block diagram which shows another example of a structure of the master apparatus in the data communication system concerning this invention, and a slave apparatus. It is a block diagram which shows another example of a structure of the master apparatus in the data communication system concerning this invention, and a slave apparatus. It is explanatory drawing regarding the modulation process in a master apparatus. It is explanatory drawing regarding the demodulation process in a slave apparatus. It is a conceptual diagram of the conventional data communication system.

Explanation of symbols

1-1, 1-2, 1-3, 1-4 Transmission / reception device 2 Power line 100 Master device 101 Crystal oscillator 102 Main clock generation unit 103 Carrier signal generation unit 104 Data rate setting unit 105 Transmission data generation unit 106 Modulation unit ( Transmitter)
107 Band filter (transmitter)
108 demodulation unit 109 signal processing unit 110 data rate measurement unit 111 carrier frequency calculation unit 112 carrier adjustment signal generation unit 120 SMC frequency information detection unit 121 SMC adjustment signal generation unit 200 slave device 201 band filter (reception unit)
202 Demodulator (Receiver)
203 Signal Processing Unit 204 Clock State Detection Unit 205 Clock Frequency Adjustment Unit 206 Clock Generation Unit 207 Data Rate Setting Unit 208 Carrier Signal Generation Unit 209 Modulation Unit 250 SMC Frequency Information Detection Unit 251 Main Clock Adjustment Unit CLK_M Main Clock Signal CLK_S Clock Signal C_M Carrier signal C_S Carrier signal Creg Carrier adjustment signal Rx_M Reception signal Rx_S Reception signal Tx_M Transmission data Tx_S Transmission data

Claims (3)

In a data communication system in which a master-side transceiver device and a plurality of slave-side transceiver devices communicate bidirectionally,
The transmitting / receiving device on the master side
A main clock generator for generating a main clock signal with high frequency accuracy;
A data rate setting unit that sets a transmission rate of transmission data by dividing the main clock signal generated by the main clock generation unit according to a constant C;
A signal processing unit for receiving and processing a received signal;
An SMC frequency information detection unit that reads main lock frequency information on the slave side included in the received signal from the transmission / reception device on the slave side;
An SMC adjustment signal generator that generates an adjustment signal for adjusting the main lock frequency of the corresponding transmission / reception device on the slave side to the same frequency as the master, based on the main lock frequency information on the slave side;
A transmission data generation unit that generates transmission data based on the signals generated by the data rate setting unit and the SMC adjustment signal generation unit,
For multiple slave side transceivers,
A signal processing unit for receiving and processing a received signal;
An SMC adjustment signal detection unit that detects an SMC adjustment signal included in a reception signal from a master-side transmission / reception device;
A main lock adjustment unit that generates an adjustment signal for adjusting the main clock frequency of the own transmission / reception device to be the same as that of the master based on the SMC adjustment signal detected by the SMC adjustment signal detection unit;
A main lock generator having a lower frequency accuracy and frequency stability than the main clock generator on the master side, which can adjust the main lock frequency of the own transmission / reception device according to the adjustment signal from the main lock adjustment unit;
A data rate setting unit that sets a transmission rate of transmission data by dividing the main lock signal generated by the main lock generation unit according to a constant C;
A transmission data generation unit that generates transmission data at a transmission rate set by the data rate setting unit;
A data communication system comprising: In a data communication system in which a master-side transmission / reception device and a plurality of slave-side transmission / reception devices perform modulation / demodulation using a single carrier signal and perform bidirectional communication, the master-side transmission / reception device includes:
A main clock generator for generating a main clock signal with high frequency accuracy;
A data rate setting unit that sets a transmission rate of transmission data by dividing the main clock signal generated by the main clock generation unit according to a constant C;
A carrier signal generation unit that generates a carrier signal by performing signal processing on the main clock signal generated by the main clock generation unit;
A demodulator that demodulates the modulated received signal;
A signal processing unit that processes the demodulated received signal;
An SMC frequency information detector that reads main clock frequency information on the slave side included in the received signal from the transmission / reception device on the slave side;
An SMC adjustment signal generation unit that generates an adjustment signal for adjusting the main clock frequency of the corresponding transmission / reception device on the slave side to the same frequency as the master, based on the main clock frequency information on the slave side;
A transmission data generation unit that generates transmission data based on signals generated by the data rate setting unit and the SMC adjustment signal generation unit;
A modulation unit that generates a transmission signal modulated based on the signal generated by the transmission data generation unit and the carrier signal generation unit, and
For multiple slave side transceivers,
A demodulator that demodulates the modulated received signal;
A signal processing unit that processes the demodulated received signal;
An SMC adjustment signal detection unit that detects an SMC adjustment signal included in a reception signal from a master-side transmission / reception device;
Based on the SMC adjustment signal detected by the SMC adjustment signal detection unit, a main clock adjustment unit that generates an adjustment signal for adjusting the main clock frequency of the own transmitting / receiving device to be the same as that of the master,
A main clock generator having a lower frequency accuracy and frequency stability than the main clock generator on the master side, which can adjust the main clock frequency of the own transceiver device according to the adjustment signal from the main clock adjuster,
A data rate setting unit that sets a transmission rate of transmission data by dividing the main clock signal generated by the main clock generation unit according to a constant C;
A transmission data generation unit that generates transmission data at a transmission rate set by the data rate setting unit;
A carrier signal generation unit that generates a carrier signal by performing signal processing on the main clock signal generated by the main clock generation unit;
A modulation unit that generates a transmission signal modulated based on the signals generated by the transmission data generation unit and the carrier signal generation unit;
A data communication system comprising: In a data communication system in which a plurality of transmission / reception devices perform half-duplex communication with each other using a single carrier signal,
One of the plurality of transmission / reception devices functions as a master device, and other devices function as slave devices,
The master device is
A main clock generator that oscillates a main clock signal using a crystal oscillator or a ceramic oscillator;
A carrier signal generator for generating a carrier signal from the main clock signal;
Based on the received signal, a carrier frequency calculating unit that calculates the frequency of the carrier signal generated by the transmission source slave device of the received signal;
An adjustment signal generator that generates a carrier adjustment signal based on the frequency calculated by the carrier frequency calculator;
A transmission unit for transmitting the carrier adjustment signal to the transmission source slave device,
The slave device is
A clock generator for oscillating a clock signal at an oscillation frequency corresponding to the input signal voltage;
A carrier signal generator for generating a carrier signal from the clock signal;
A receiver for receiving the carrier adjustment signal;
A clock adjustment unit that adjusts the input signal voltage of the clock generation unit based on the carrier adjustment signal so that the oscillation frequency of the clock generation unit matches the oscillation frequency of the main clock generation unit of the master device. A data communication system.

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