RU2680762C1 - Device of group structure for detection of groups of zero and one bits and determination of their quantity - Google Patents

Abstract

FIELD: computer equipment.

SUBSTANCE: invention relates to computer equipment. Device contains N bits of the input binary number D1, D2, …, DN, that are divided into L groups of M digits in the group (N = L * M), Z steps of blocks of elements, where Z = ]log2L[ +1 (greater integer), at that the first stage contains L blocks of elements, 1L of the first type, and each i-th stage contains L / 2 (i-1) blocks of elements of 2ij of the second type, 1L of the first type of the first stage contains (M-1) stages of drivers of ordered binary numbers, 3 (M-1), that are combined into a pyramid structure, each v-th cascade 3v (v = 1, …, (M-1)) contains a group of (Mv) elements OR, 4 (Mv), a group of (Mv) elements EXCLUSIVE OR, 5 (Mv), OR element with one inverse input, a group of (M-1) modules of the account of lower ordered units, 7 (M-1), the first group of M adders, 8M, the module of the account of units and the second multigroup adder, each block of elements 2ij of the second type contains a third group of (M * 2 (i-2) +1) adders AND, the fourth adder, the group shift module, the module for generating the shift code and the code for the total number of groups.

EFFECT: technical result is broader functional capabilities.

1 cl, 3 dwg, 3 tbl

Description

FIELD OF TECHNOLOGY

The invention relates to the field of computer engineering, in particular to data processing devices, and can be used to build automation equipment and functional units of control systems, to analyze the properties of pseudorandom sequences of binary numbers, and also to process the results of physical experiments.

BACKGROUND OF THE INVENTION

A known system and method for calculating the initial zero digits and counting the initial unit digits in a digital signal processor (RU No. 2409837 C2, IPC G06F 7/74, announced July 27, 2006, published January 20, 2011, Bull. No. 2) in which the number of bits for different sizes of data words. The device expands the input data with a sign to a temporary sixty-four-bit data word. When counting zero digits, the word digits are inverted. A binary counter is used to calculate the initial bits.

The disadvantage of this device is the low speed, as well as counting only the initial zero digits and the initial single digits in a digital signal.

A device is known for determining the number of units in an ordered binary number (RU No. 2522875, IPC Н03К 21/12, announced May 24, 2012, published July 20, 2014, Bull. No. 20), containing buffers with three states with direct and inverse resolution inputs, n bits of the input binary number, (k + 1) bits of the output binary code (k = [log ₂ n] is a smaller integer), and buffers with three states are combined into a pyramidal structure consisting of (m-1) steps (m =] log ₂ n [larger integer), and to the output block containing k buffers with three states with an inverse of the resolution input and k buffers moat tristate direct enable input, wherein each stage i-i (i = 1, ..., (m-1)) contains (2 ⁱ -1) buffer tristate enable input with an inverted and a buffer 2 ⁱ -1 with three states with direct permission input.

The disadvantage of this device is the determination of the number of units in only an ordered binary number, and not in groups of zero and single digits.

The closest device of the same purpose to the claimed invention according to the totality of features is, adopted for the prototype, a device for determining the number of units (zeros) in a binary number (RU No. 2446442, IPC G06F 7/50, H03K 21/00, stated 04/11/2011, published March 27, 2012, Bull. No. 9) containing a controlled inversion block consisting of n-elements “EXCLUSIVE OR” (n is the number of bits of an input number), OR elements, and modules consisting of an EXCLUSIVE OR element and AND element, which are combined in groups consisting of tiers, and combined in k-cascades (k =] log ₂ n [), so that every ith cascade contains g (i) = n / 2 ⁱ groups (i = 1, ..., k), each group of the ith cascade is divided into j tiers ( j = 1, ..., i), while the first tier of each group of the i-th cascade contains i modules, and each j-th tier of each group of the i-th cascade (j = 2, ..., i,) contains (ij) modules and the element "OR".

The disadvantage of this device is the determination of only the total number of units (zeros) in a binary number, and not by groups of zeros and singles.

The reasons that impede the achievement of the technical result indicated below include the lack of funds for identifying groups and determining the number of zero and single bits in groups, and determining the total number of groups.

OBJECT OF THE INVENTION

The objective of the invention is to develop hardware for studying the properties of generators of pseudo-random sequences of binary numbers, as well as for processing the results of physical experiments.

When analyzing generators of pseudorandom sequences of binary numbers, the device is designed to identify groups (rows) of consecutive single and zero bits, determine the number of bits in groups, the total number of groups and the total number of single bits.

When processing the results of physical experiments, the device is designed to detect events (groups of single bits) and intervals between events (groups of zero bits), determine their duration and determine the total number and duration of events.

The technical result of the invention is to expand the functionality in terms of the possibility of identifying groups of single and zero bits in binary numbers, determining the number of bits in groups and determining the total number of single bits in binary numbers, as well as simply increasing the bit depth of input information while reducing hardware costs and increasing device performance .

SUMMARY OF THE INVENTION

The specified technical result in the implementation of the invention is achieved by the fact that the group structure device for detecting groups of zero and single bits and determining their number

contains N bits of the input binary number D1, D2, ..., DN, which are divided into L groups of M bits in the group (N = L * M), Z steps of blocks of elements, where Z =] log ₂ L [+1 (] [ - a larger integer), and the first step contains L blocks of elements 1 ₁ , 1 ₂ , ..., 1 _{L of the} first type, and each i-th step, starting from the second step to the Z-th step, contains L / 2 ^{(i- 1)} blocks of elements 2ij of the second type, where i = 2, 3, ..., Z, j = 1, 2, ..., L / 2 ^(i-1) ,

moreover, N bits of the input binary number D1, D2, ..., DN in groups of M bits are connected to the inputs of the same input groups of blocks of elements 1 ₁ , 1 ₂ , ..., 1 _{L of the} first type of the first stage, the outputs of the odd blocks of elements 1 ₁ , 1 ₃ , ..., 1 _{1 (L-1)} (LF) and the outputs of even blocks of elements 1 ₂ , 1 ₄ , ..., 1 _L (Th) of the first stage are paired with the corresponding groups of the inputs of the same name, respectively, of the first and second sections of the inputs of blocks of elements 2 ₂₁ , 2 ₂₂ , ..., 2 _{2L / 2 of the} second type of the second stage, and the outputs of the odd blocks of elements 2ij (low) and the outputs of the even blocks of elements 2 ij (th) of each i-th stage, starting from the second stage to the penultimate (Z-1) -th stage, are paired with the corresponding groups of the same inputs of the first and second sections of the inputs of the blocks of elements 2ij of the next stages, starting from the third stage to the last Z-stage, and the outputs of the groups of the block of elements 2zj of the last stage Z are the corresponding groups Q of the external outputs of the same name of the device of the group QK of the total number of groups of single and zero bits, groups QU of the number of unit bits in the input binary number D1, D2, ..., DN, w groups QG of zero and single bits (w = 1, 2, ..., N + 1), and the outputs of the odd groups QG (wf) ⁰ correspond to the groups of zero bits, and the outputs of the even groups QG (wf) ¹ correspond to the groups of single bits, and QDL output corresponding to the left bit of the input binary number D1,

moreover, the output group QK of the total number of groups of unit and zero bits and the output group QU of the number of unit bits in the input binary number D1, D2, ..., DN each contain] log ₂ (N + 1) [(larger integer) bits, output groups of zero and single bits of QGw contain by] log ₂ (N + 3-w) [(larger integer) bits,

each block of elements 1 ₁ , 1 ₂ , ..., 1 _{L of the} first type of the first stage contains (M-1) cascades of shapers of ordered binary numbers 3 ₁ , 3 ₂ , ..., 3 _(M-1) , which are combined into a pyramidal structure, and each v-th cascade 3 _v (v = 1, ..., (M-1)) contains a group of (Mv) elements OR 4 ₁ , 4 ₂ , ..., 4 _(Mv) , a group of (Mv) elements “EXCLUSIVE OR »5 ₁ , 5 ₂ , ..., 5 _(Mv) , a group of (M + 1-v) inputs A1, A2, ..., A (M + 1-v), a group of (Mv) outputs O1, O2, ... , O (Mv) to the next stage and a group of (M + 1-v) bit outputs of the corresponding v-th internal bus Sv from the group S1, S2, ..., S (M-1),

as well as in each block of elements 1 ₁ , 1 ₂ , ..., 1 _{L of the} first type of the first stage, an OR element with one inverse input 6, a group of (M-1) counting units of the lowest ordered units 7 ₁ , 7 ₂ , ..., 7 is introduced _(M-1) , the first group of M adders 8 ₁ , 8 ₂ , ..., 8 _M with an inverse group of inputs of the second term, unit counting module 9 and the second multi-group adder 10, with each v-th adder 8 _v containing] log ₂ (M + 3-v) [(larger integer) bits of the inputs of the terms, and the last _Mth adder 8 _M contains two bits of the inputs of the terms,

moreover, M bits of each of the L groups of the input binary number D1, D2, ..., DN, starting from the first bit to the Mth bit, are connected in the reverse order, respectively, with the inputs AM, AM-1, ..., A1 of the first stages 3 ₁ in the corresponding blocks of elements 1 ₁ , 1 ₂ , ..., 1 _{L of the} first type of the first stage of the same groups L,

in each v-th cascade of shapers 3 _{v, the} first (Mv) inputs A1, A2, ..., A (Mv), except for the last input A (M + 1-v), are connected to the second inputs of the corresponding elements of the same name OR 4 ₁ , 4 ₂ , ..., 4 _(Mv) and the second inputs of the EXCLUSIVE OR elements of the same name 5 ₁ , 5 ₂ , ..., 5 _(Mv) , and the first inputs of the first (M-v-1) elements OR 4 ₁ , 4 ₂ , ..., 4 _(Mv-1) from the group of OR elements, starting from the first OR element, connected to the outputs of the corresponding subsequent elements 4 ₂ , 4 ₃ , ..., 4 _(Mv) from the group of OR elements, starting from the second element, the first input of the last (Mv ) th element 4 _(Mv) from the group of OR elements is connected to the last input A (M + 1-v) of the v-th cascade of formers 3 _v , outputs (Mv) of OR elements 4 ₁ , 4 ₂ , ..., 4 _(Mv) are also connected to the first inputs of the corresponding elements of the EXCLUSIVE OR ”5 ₁ , 5 ₂ , ..., 5 _(Mv) , the outputs of which are a group (Mv) of outputs O1, O2, ..., O (Mv) to the next stage of each v-th stage 3 _v , and the outputs of all (Mv) elements OR 4 ₁ , 4 ₂ , ..., 4 _(Mv) are also the same first lower (Mv) bits of the corresponding v-th internal bus Sv from the group S1, S2, ..., S (M-1), starting from the first bit, and the last A (M + 1-v) -th input of the v-th cascade 3 _v is the senior (M + 1-v) -th bit of the corresponding v-th internal bus Sv,

moreover, in the first (M-2) cascades of the shapers, except for the last (M-1) -th cascade of 3 _(M-1) , (Mv) outputs O1, O2, ..., O (Mv) in the next (v + 1) - cascade 3 _{(v + 1) is} connected to the corresponding (Mv) inputs of the same name A1, A2, ..., A (Mv) of the next (v + 1) th cascade of formers 3 _{(v + 1)} , all bits of each v-th internal buses Sv from the group S1, S2, ..., S (M-1), in each block of elements 1 ₁ , 1 ₂ , ..., 1 _{L of the} first type of the first stage, are connected to the inputs of the corresponding module of the same name 7 _v from the group from (M- 1) count modules of the least ordered units, and the outputs of each v-th module 7 _{v are} connected to the inverse the group of inputs of the second term of the corresponding vth adder 8 _v and the first group of direct inputs of the first term of the subsequent (v + 1) th adder 8 _{(v + 1)} from the first group of M adders 8 ₁ , 8 ₂ , ..., 8 _M , the outputs of which are the corresponding first M groups of output data of unit and zero bits G1, G2, ..., GM of the corresponding block of elements 1 ₁ , 1 ₂ , ..., 1 _{L of the} first type, and the last one-bit output of the group of unit and zero bits G (M + 1 ), the corresponding block of elements 1 ₁ , 1 ₂ , ..., 1 _{L of the} first type, is connected to the output O1 of the last (M-1) stage 3 _(M-1) , which is also connected to the input of the second inverse group of the last _Mth adder 8 _M and the first direct input of the OR element with one inverse input 6, the second inverse input of which is connected to the senior Mth input AM of the first stage 3 _{1 of the} corresponding block of elements 1 ₁ , 1 ₂ , ..., 1 _{L of the} first type, and also is the output of the left bit DL of the corresponding block of elements 1 ₁ , 1 ₂ , ..., 1 _{L of the} first type,

in addition to the group of direct inputs of the first term of the first adder 8 _{1, the} binary number code "M" is supplied, and the logical unit value "1" is fed to the CI carry entries of all M adders 8 ₁ , 8 ₂ , ..., 8 _M ,

the inputs of the groups of the second multi-group adder 10 are connected to the outputs of all even adders 8 (th) in each block of elements 1 ₁ , 1 ₂ , ..., 1 _{L of the} first type, and the group of outputs of the adder 10 is the output group U of the number of unit bits in the input data of the corresponding block elements 1 ₁ , 1 ₂ , ..., 1 _{L of the} first type,

the lower first bits of all (M-1) internal buses of ordered binary numbers S1, S2, ..., S (M-1) are connected to the corresponding inputs of the unit counting unit 9, in which the Mth input is connected to the output of the OR element with one inverse input 6, and the outputs of the unit counting module 9 are the output group K of the total number of groups of unit and zero bits of the corresponding block of elements 1 ₁ , 1 ₂ , ..., 1 _{L of the} first type, and the group of the total number of groups K contains] log ₂ (M + 1) [(larger integer) digits,

moreover, each block of elements 2 _{ij of the} second type of the second, third, ..., Zth stage contains a third group of (M * 2 ^(i-2) +1) adders 11, a fourth adder 12, a group shift module 13, a code generation module shift and code the total number of groups 14, which contains the first element And with one inverse input 15, the second element And with one inverse input 16, the element “EXCLUSIVE OR” 17, the fifth adder 18, the sixth adder 19, the seventh adder 20,

moreover, in each block of elements 2 _{ij of the} second type, the corresponding (M * 2 ^(i-2) +1) groups of inputs of zero and single bits 1G of the first sections of the inputs are connected to the groups of inputs of the first terms of the corresponding adders from the third group of adders 11, in which the second the groups of inputs of the second terms are connected to the corresponding first (M * 2 ^(i-2) +1) output groups of the module of the shift of groups 13, in which the information groups of the inputs are connected to the corresponding (M * 2 ^(i-2) +1) groups of zero inputs and single bits 2G of the second sections of the inputs of the blocks of elements s _ij 2 of the second type, and the control inputs of the shear modulus of groups 13 to set the value of the bus number SK shifts connected to the outputs of the module of code formation and code shift total number of groups 14,

moreover, in the module for generating the shift code and the code for the total number of groups 14, the input of the left bit 1DL of the first section of inputs is connected to the first direct input of the first element And 15 with one inverse input, to the second inverse input of the second element And 16 with one inverse input, the first input of the element eXCLUSIVE OR "17 and is the output of the left bit DL corresponding unit elements 2 _ij, left bit input section 2DL second inputs connected to the second inverted input of the first aND gate 15 with one inverted input to a first direct input of the second element 16 with one inverse input and with the second input of the EXCLUSIVE OR element 17, the third input of which is connected to the lowest zero bit 1k0 of group 1K of the total number of groups of single and zero bits of the first section, as well as all bits of group 1K are connected to the group of inputs of the second term of the fifth the adder 18, in which all the bits of the first term are interconnected and connected to the output of the element “EXCLUSIVE OR” 17, the group of outputs of the fifth adder 18 is connected to the group of inputs of the second term of the sixth adder 19 and to the group of inputs of the first the seventh adder of the seventh adder 20, in which the group of inputs of the second term is connected to the bits of group 2K of the total number of groups of unit and zero bits of the second section, and the group of outputs of the seventh adder 20 is the output group K of the total number of groups of unit and zero bits of the corresponding block of elements 2 _{ij of the} second type

and also all bits of the first term of the sixth adder 19 are interconnected and connected to the output of the second element And with one inverse input 16, and the transfer input CI of the sixth adder 19 is connected to the output of the first element And with one inverse input 15, and the bits of the group of outputs of the sixth adder 19 are the bits of the bus to set the value of the number of shifts SK,

the outputs of the groups of the number of unit bits of the first section 1U and the second section 2U are connected respectively to the groups of the first and second terms of the fourth adder 12, the group of outputs of which is the group of outputs U of the corresponding block of elements 2 _{ij of the} second type,

in addition, in each block 2 _{ij of the} second type, the outputs of the third group of adders 11 and the second groups of outputs of the shift module of groups 13, starting from the group of outputs (M * 2 ^(i-2) +2) to the group of outputs (M * 2 ^{(i- 1)} +1) are the outputs of the corresponding groups G of unit and zero bits of the corresponding block of elements 2 _{ij of the} second type.

BRIEF DESCRIPTION OF THE DRAWINGS

In FIG. 1 is a structural diagram of the proposed group structure device for detecting groups of zero and single bits and determining their number. In FIG. 2 shows a functional diagram of the proposed device with N = 8, M = 4, L = 2, Z = 2. In FIG. Figure 3 shows the output data formats for N bits of the input data and for M = 4 and N = 8. Table 1 shows examples of generating values for the number of zero and single bits for groups G1, G2, ..., G5 in cascades and for the total number of groups K for N = 4 for blocks of elements 1. Table 2 shows examples of generating values for odd groups of zero bits G1 ⁰ , G3 ⁰ , G5 ⁰ , G7 ⁰ , G9 ⁰ and even groups of single bits G2 ¹ , G4 ¹ , G6 ¹ , G8 ¹ , the total number (sum) of groups of single and zero bits K, the bus for setting the number of shifts SK for N = 8, M = 4, L = 2, Z = 2 for blocks of elements 2. Table 3 shows the values of the functions for adjusting the sum code K of the number of groups and shift amount code on the SK bus.

In FIG. 1, FIG. 2, FIG. 3, the following notation is used in the tables and in the text:

D1, D2, ..., DN - N bits of the input binary number,

L is the number of discharge groups,

M is the number of bits in the group, with N = L * M,

Z is the number of steps, where Z =] log ₂ L [+1 (] [is a larger integer),

And - the inputs of the cascades of blocks of elements 1 of the first type of the first stage,

O - the outputs of the cascades of blocks of elements 1 of the first type of the first stage,

G - groups of single and zero bits,

G ⁰ - groups of zero bits,

G ¹ - group of single bits,

K is a group of the total number (sum) of groups of single and zero bits,

U is the group of the quantity (sum) of unit bits,

DL - left bit,

SM - adder

CI - adder transfer input,

F - module counting the lowest ordered binary numbers,

SF is the group shear modulus,

SK is a bus for setting the number of shifts,

S1, S2, ..., S (M-1) - (M-1) internal buses of ordered binary numbers,

1G, 1K, 1U, 1DL - groups of inputs of the first sections of blocks of elements 2ij,

1k0 - the lowest zero bit of group 1K of the total number of groups of single and zero bits of the first section,

2G, 2K, 2U, 2DL - groups of inputs of the second sections of the blocks of elements 2ij,

QG, QK, QU, QDL - groups of device outputs,

i is the number of the stage, where i = 2, 3, ..., Z,

j is the block number of elements in the i-th stage, where j = 1, 2, ..., L / 2 ^(i-1) ,

v is the number of the cascade of the shaper of ordered binary numbers of blocks of the first stage, v = 1, ..., (M-1),

1 ₁ , 1 ₂ , ..., 1 _L - L blocks of elements of the first type of the first stage,

2 _ij - blocks of elements of the second type of the i-th stage, where i = 2, 3, ..., Z, j = 1, 2, ..., L / 2 ^(i-1) ,

3 ₁ , 3 ₂ , ..., 3 _(M-1) - (M-1) cascades of the shaper of ordered binary numbers of blocks of the first stage 1,

4 - groups of elements OR,

5 - groups of elements "EXCLUSIVE OR" (XOR),

6 - OR element with one inverse input,

7 - a group of (M-1) counting units of the lowest ordered units,

8 - the first group of M adders with an inverse group of inputs of the second term,

9 - unit counting module,

10 - the second multi-group adder,

11 - the third group of (M * 2 ^(i-2) +1) adders,

12 - fourth adder

13 - module shift groups

14 - a module for generating a shift code and a code for the total number of groups,

15 - the first element And with one inverse input,

16 - the second element And with one inverse input,

17 - element "EXCLUSIVE OR" (XOR),

18 - fifth adder,

19 - sixth adder,

20 - seventh adder.

The proposed group structure device for detecting groups of zero and single bits and determining their number contains N bits of the input binary number D1, D2, ..., DN, which are divided into L groups of M bits in the group (N = L * M), Z block levels elements, where Z =] log ₂ L [+1 (] [is a larger integer), and the first step contains L blocks of elements 1 ₁ , 1 ₂ , ..., 1 _{L of the} first type, and each i-th step, starting from the second steps to the Z-th step, contains L / 2 ^(i-1) blocks of elements 2ij of the second type, where i = 2, 3, ..., Z, j = 1, 2, ..., L / 2 ^(i-1) .

Moreover, N bits of the input binary number D1, D2, ..., DN in groups of M bits are connected to the inputs of the same input groups of blocks of elements 1 ₁ , 1 ₂ , ..., 1 _{L of the} first type of the first stage.

The outputs of the odd blocks of elements 1 ₁ , 1 ₃ , ..., 1 _{1 (L-1)} (LF) and the outputs of the even blocks of elements 1 ₂ , 1 ₄ , ..., 1 _L (Th) of the first stage are paired with the corresponding groups of inputs of the same name, respectively the first and second sections of the inputs of the blocks of elements 2 ₂₁ , 2 ₂₂ , ..., 2 _{2L / 2 of the} second type of the second stage.

The outputs of the odd blocks of elements 2ij (woofer) and the outputs of the even blocks of elements 2ij (th) of each i-th stage, starting from the second stage to the penultimate (Z-1) -th stage, are paired with the corresponding groups of the same inputs of the first and second sections, respectively inputs of blocks of elements 2ij of subsequent stages, starting from the third stage to the last Z-th stage.

The outputs of the groups of the block of elements 2zj of the last stage Z are the corresponding groups Q of the external device outputs of the same name - groups QK of the total number (sum) of groups of single and zero bits, groups QU of the quantity (sum) of unit bits in the input binary number D1, D2, ..., DN, w groups QG of zero and single bits (w = 1, 2, ..., N + 1), and the outputs of the odd groups QG (wf) ⁰ correspond to the groups of zero bits, and the outputs of the even groups QG (wf) ¹ correspond to the groups of single bits, and QDL output corresponding to the left bit of the input binary number D1. Moreover, the output group QK of the total number of groups of unit and zero bits and the output group QU of the number of unit bits in the input binary number D1, D2, ..., DN each contain] log ₂ (N + 1) [(larger integer) bits, output groups of zero and the unit bits of QGw each contain] log ₂ (N + 3-w) [(larger integer) bits.

Each block of elements 1 ₁ , 1 ₂ , ..., 1 _{L of the} first type of the first stage contains (M-1) cascades of shapers of ordered binary numbers 3 ₁ , 3 ₂ , ..., 3 _(M-1) , which are combined into a pyramidal structure, and each v-th cascade 3 _v (v = 1, ..., (M-1)) contains a group of (Mv) elements OR 4 ₁ , 4 ₂ , ..., 4 _(Mv) , a group of (Mv) elements “EXCLUSIVE OR »5 ₁ , 5 ₂ , ..., 5 _(Mv) , a group of (M + 1-v) inputs A1, A2, ..., A (M + 1-v), a group of (Mv) outputs O1, O2, ... , O (Mv) to the next stage and a group of (M + 1-v) bit outputs of the corresponding v-th internal bus Sv from the group S1, S2, ..., S (M-1).

Also, in each block of elements 1 ₁ , 1 ₂ , ..., 1 _{L of the} first type of the first stage, an OR element with one inverse input 6, a group of (M-1) counting units of the lowest ordered units 7 ₁ , 7 ₂ , ..., 7 _{( M-1)} , the first group of M adders 8 ₁ , 8 ₂ , ..., 8 _M with an inverse group of inputs of the second term, unit counting unit 9 and the second multi-group adder 10, and each v-th adder 8 _v contains] log ₂ (M + 3-v) [(larger integer) category of inputs of terms, and the last _Mth adder 8 _M contains two bits of inputs of terms.

Moreover, the M bits of each of the L groups of the input binary number D1, D2, ..., DN, starting from the first bit to the Mth bit, are connected in reverse order, respectively, with the inputs AM, AM-1, ..., A1 of the first cascades 3 ₁ in the corresponding blocks of elements 1 ₁ , 1 ₂ , ..., 1 _{L of the} first type of the first stage of the same groups L.

In each v-th cascade of shapers 3 _{v, the} first (Mv) inputs A1, A2, ..., A (Mv), except for the last input A (M + 1-v), are connected to the second inputs of the corresponding elements of the same name OR 4 ₁ , 4 ₂ , ..., 4 _(Mv) and the second inputs of the EXCLUSIVE OR elements of the same name 5 ₁ , 5 ₂ , ..., 5 _(Mv) . The first inputs of the first (M-v-1) elements OR 4 ₁ , 4 ₂ , ..., 4 _(Mv-1) from the group of OR elements, starting from the first OR element, are connected to the outputs of the corresponding subsequent elements 4 ₂ , 4 ₃ , ... , 4 _(Mv) from the group of OR elements, starting from the second element. The first input of the last (Mv) th element 4 _(Mv) from the group of OR elements is connected to the last input A (M + 1-v) of the v-th cascade of shapers 3 _v . The outputs (Mv) of the elements OR 4 ₁ , 4 ₂ , ..., 4 _(Mv) are also connected to the first inputs of the corresponding elements of the EXCLUSIVE OR 5 ₁ , 5 ₂ , ..., 5 _(Mv) , the outputs of which are a group (Mv) outputs O1, O2, ..., O (Mv) to the next stage of each v-th stage 3 _v . The outputs of all (Mv) elements OR 4 ₁ , 4 ₂ , ..., 4 _(Mv) are also the same first lower (Mv) bits of the corresponding v-th internal bus Sv from the group S1, S2, ..., S (M-1), starting from the first bit, and the last A (M + 1-v) -th input of the v-th cascade 3 _v is the highest (M + 1-v) -th bit of the corresponding v-th internal bus Sv.

Moreover, in the first (M-2) cascades of the shapers, in addition to the last (M-1) -th cascade of 3 _(M-1) , (Mv) outputs O1, O2, ..., O (Mv) in the next (v + 1) - Stage 3 _{(v + 1) is} connected to the corresponding (Mv) inputs of the same name A1, A2, ..., A (Mv) of the next (v + 1) th stage of the formers 3 _{(v + 1)} .

All bits of each v-th internal bus Sv from the group S1, S2, ..., S (M-1), in each block of elements 1 ₁ , 1 ₂ , ..., 1 _{L of the} first type of the first stage, are connected to the inputs of the corresponding module of the same name 7 _v from the group of (M-1) counting units of the lowest ordered units. The outputs of each v-th module 7 _{v are} connected to the inverse group of inputs of the second term of the corresponding v-th adder 8 _v and the first group of direct inputs of the first term of the subsequent (v + 1) -th adder 8 _{(v + 1)} from the first group of M adders 8 ₁ , 8 ₂ , ..., 8 _M. The outputs of the adders from the first group of M adders 8 ₁ , 8 ₂ , ..., 8 _M are the corresponding first M groups of output data of single and zero bits G1, G2, ..., GM of the corresponding block of elements 1 ₁ , 1 ₂ , ..., 1 _{L of the} first type. The last single-bit output of the group of single and zero bits G (M + 1), the corresponding block of elements 1 ₁ , 1 ₂ , ..., 1 _{L of the} first type, is connected to the output O1 of the last (M-1) stage 3 _(M-1) , which is also connected to the input of the second inverse group of the last _Mth adder 8 _M and the first direct input of the OR element with one inverse input 6, the second inverse input of which is connected to the senior Mth input AM of the first stage 3 _{1 of the} corresponding block of elements 1 ₁ , 1 ₂ , ..., 1 _{L of the} first type, and also is the output of the left bit DL of the corresponding block of elements 1 ₁ , 1 ₂ , ..., 1 _{L of the} first type.

In addition, the binary number code "M" is supplied to the group of direct inputs of the first term of the first adder 8 ₁ , and the logical unit value "1" is applied to the CI carry entries of all M adders 8 ₁ , 8 ₂ , ..., 8 _M.

The inputs of the groups of the second multi-group adder 10 are connected to the outputs of all even adders 8 (Th) in each block of elements 1 ₁ , 1 ₂ , ..., 1 _{L of the} first type, and the group of outputs of the adder 10 is the output group U of the number of unit bits in the input data of the corresponding block elements 1 ₁ , 1 ₂ , ..., 1 _{L of the} first type.

The lower first bits of all (M-1) internal buses of ordered binary numbers S1, S2, ..., S (M-1) are connected to the corresponding inputs of the unit counting unit 9, in which the M-th input is connected to the output of the OR element with one inverse input 6. The outputs of the unit counting module 9 are the output group K of the total number (sum) of groups of unit and zero bits of the corresponding block of elements 1 ₁ , 1 ₂ , ..., 1 _{L of the} first type, and the group of the total number of groups K contains] log ₂ (M + 1) [(larger integer) digits.

Moreover, each block of elements 2 _{ij of the} second type of the second, third, ..., Zth stage contains a third group of (M * 2 ^(i-2) +1) adders 11, a fourth adder 12, a group shift module 13, a code generation module shift and code the total number of groups 14, which contains the first element And with one inverse input 15, the second element And with one inverse input 16, the element “EXCLUSIVE OR” 17, the fifth adder 18, the sixth adder 19, the seventh adder 20.

In each block of elements 2 _{ij of the} second type, the corresponding (M * 2 ^(1-2) +1) input groups of the zero and single bits 1G of the first sections of the inputs are connected to the input groups of the first terms of the corresponding adders of the same name from the third group of adders 11, in which the second groups the inputs of the second terms are connected to the corresponding first (M * 2 ^(i-2) +1) output groups of the group shift module 13. The information groups of the inputs of the shift module 13 groups are connected to the corresponding (M * 2 ^(i-2) +1) input groups zero and single bits 2G of the second sections of the inputs of the blocks of ele cops 2 _{ij of the} second type, and the control inputs of the shift module of groups 13 on the bus for setting the value of the number of shifts SK are connected to the outputs of the module for generating the shift code and the code for the total number of groups 14.

Moreover, in the module for generating the shift code and the code for the total number of groups 14, the input of the left bit 1DL of the first section of inputs is connected to the first direct input of the first element And 15 with one inverse input, with the second inverse input of the second element And 16 with one inverse input, the first input of the element EXCLUSIVE OR ”17 and is the output of the left bit DL of the corresponding block of elements 2 _ij . The input of the left bit 2DL of the second section of inputs is connected to the second inverse input of the first AND 15 element with one inverse input, to the first direct input of the second AND 16 element with one inverse input and to the second input of the EXCLUSIVE OR element 17, the third input of which is connected to the junior zero bit 1k0 of group 1K of the total number of groups of unit and zero bits of the first section. Also, all the digits of group 1K are connected to the group of inputs of the second term of the fifth adder 18, in which all the digits of the first term are interconnected and connected to the output of the EXCLUSIVE OR element 17. The group of outputs of the fifth adder 18 is connected to the group of inputs of the second term of the sixth adder 19 and with the group of inputs of the first term of the seventh adder 20, in which the group of inputs of the second term is connected to the bits of group 2K of the total number of groups of unit and zero bits of the second section. The group of outputs of the seventh adder 20 is an output group K of the total number (sum) of groups of unit and zero bits of the corresponding block of elements 2 _{ij of the} second type.

All bits of the first term of the sixth adder 19 are interconnected and connected to the output of the second element And with one inverse input 16, and the transfer input CI of the sixth adder 19 is connected to the output of the first element And with one inverse input 15. The bits of the group of outputs of the sixth adder 19 are bits tires for setting the value of the number of shifts SK.

The outputs of the groups of the quantity (sum) of unit bits of the first section 1U and the second section 2U are connected respectively to the groups of the first and second terms of the fourth adder 12, the group of outputs of which is the group of outputs U of the corresponding block of elements 2 _{ij of the} second type.

In each block 2 _{ij of the} second type, the outputs of the third group of adders 11 and the second group of outputs of the shift module of groups 13, starting from the group of outputs (M * 2 ^(i-2) +2) to the group of outputs (M * 2 ^(i-1) + 1) are the outputs of the corresponding groups G of unit and zero bits of the corresponding block of elements 2 _{ij of the} second type.

DETAILED DESCRIPTION OF THE INVENTION

The principle of operation of the proposed device is as follows.

The input N digit unsigned binary number is divided into L groups of M bits in the group (N = L * M) and fed to the corresponding L blocks of the same name elements 1 ₁ , 1 ₂ , ..., 1 _{L of the} first type of the first stage.

In the blocks of elements 1 ₁ , 1 ₂ , ..., 1 _{L of the} first type of the first stage in the cascades of the shapers 3 ₁ , 3 ₂ , ..., 3 _(M-1) , the input data groups A are converted into chains of groups of elements OR 4 ₁ , 4 ₂ , ..., 4 _(Mv) , into groups of ordered binary codes “00 ... 011 ... 1” with units arranged in a row, starting with the least significant bits, where the left unit corresponds to the highest unit in the corresponding input data group, and are installed at the outputs of the groups of elements OR 4 ₁ , 4 ₂ , ..., 4 _(Mv) , and also, together with the corresponding senior input bit A (M + 1-v) of the v-th cascade of shapers 3 _v transferred to the internal bus S1, S2, ..., S (M-1).

In the groups of elements “EXCLUSIVE OR” 5 ₁ , 5 ₂ , ..., 5 _(Mv) , which can be considered as elements of a “controlled inverter”, the least significant bits of the groups of input data A are inverted, corresponding to the unit values in the ordered binary code “00 ... 011 ... 1 ”at the outputs of the group of elements OR 4 ₁ , 4 ₂ , ..., 4 _(Mv) . In this case, the highest zero bits of the input data groups A do not change and remain zero, and the bits of the left highest group of single bits of the input data A, corresponding to the unit values of the ordered binary code "00 ... 011 ... 1", are inverted and take zero values. The values from the outputs corresponding to the groups of elements “EXCLUSIVE OR” 5 ₁ , 5 ₂ , ..., 5 _(Mv) are supplied to the outputs O1, O2, ..., O (Mv) of the corresponding cascades of the shapers 3 _v .

The calculation of the number of unit digits in the tires S1, S2, ..., S (M-1) is carried out in the group of modules 7 ₁ , 7 ₂ , ..., 7 _{(M-1) for} counting the lowest ordered units. The sum of the number of units at the outputs of the modules 7 _v is an addition to M to the number of leading zeros in the input data groups A of the corresponding cascades of the shapers 3 _v . The values of the sum of the number of units go to the inverse inputs of the second terms of the same adders 8 ₁ , 8 ₂ , ..., 8 _(M-1) and the direct inputs of the first terms of the subsequent adders 8 ₂ , 8 ₃ , ..., 8 _M , on which the number of zero or single bits in the corresponding groups G, since the additions to M in adjacent stages differ by the number of bits in groups of zero or single bits.

Table 1 shows examples of the formation of the values of the number of zero and single bits for groups G1, G2, ..., G5 of cascades and the total number of groups K for N = 4 for blocks of elements 1. In this case, codes are generated in the odd groups G (low) ⁰ zero bits in groups, and in even groups G (Th) ¹ codes are generated corresponding to the number of single bits in groups. In the first group of bits G1 ⁰ , a code is always generated for a group of zero bits, and if the left most significant bit in a group takes a single value AM = 1, then the code of the sum of bits of the first group takes a zero value G1 ⁰ = 0.

At the same time, in units 9 of the unit counting unit, the number (sum) of unit values in the least significant bits of all internal buses from the group S1, S2, ..., S _(M-1) and at the output of the OR 6 element is calculated, which corresponds to the total number K of groups of zero and one bit. Also, on the second multi-group adders 10, the total number U of unit bits in the input data of the corresponding block of elements 1 is calculated.

Further, the values of the codes for groups from the outputs of the odd blocks of elements 1 ₁ , 1 ₃ , ..., 1 _{1 (L-1)} (LF) and from the outputs of the even blocks of elements 1 ₁ , 1 ₂ , ..., 1 _L (Th) of the first stage in pairs transmitted to the same group of inputs of the first and second sections of the inputs of blocks 2 ₂₁ , 2 ₂₂ , ..., 2 _{2L / 2 of the} second stage, respectively. Then the values from the outputs of the odd blocks of elements 2ij (woofer) and from the outputs of the even blocks of elements 2ij (th) of each i-th stage, starting from the second stage to the penultimate (Z-1) -th stage, are transmitted in pairs to the corresponding groups of inputs of the same name, respectively the first and second sections of the inputs of the blocks of elements of 2 subsequent stages, starting from the third stage to the last Z-th stage. In FIG. 1 is a structural diagram of combining blocks of step elements.

In each block of elements 2 _{ij of the} second type, the values of the input groups of the zero and single bits of the first 1G and second 2G sections are combined. To combine groups, depending on the values of the inputs of the upper left bits of the sections 1DL and 2DL and the value of the lowest zero bit 1k0 of group 1K of the total number of groups of unit and zero bits of the first section, the value of the shift code SK is generated in modules 14 and in the shift modules of groups 13 the shift of the groups of zero and single bits of the second 2G sections by an even number of SK groups. Next, on the third group of adders 11, the groups are combined and groups of zero and single bits G are formed for two sections. Table 2 shows examples of the formation of values of odd groups of zero bits G1 ⁰ , G3 ⁰ , G5 ⁰ , G7 ⁰ , G9 ⁰ and even groups of single bits G2 ¹ , G4 ¹ , G6 ¹ , G8 ¹ , the total number (sum) of groups of single and zero bits K, buses for setting the number of SK shifts at N = 8, M = 4, L = 2, Z = 2 for blocks of elements 2. Moreover, groups G1-G5 are formed at the outputs of the third group of adders 11, and groups G6-G9 are formed at the outputs of shear modulus 13. Table 3 shows the values of the functions (-1 and +1) generated at the outputs of the element “EXCLUSIVE OR” 17, the first 15 and second 16 elements AND with one and population-inverted input, to adjust the sum of the number of code groups (1K + 2K) and the number of code changes to SK bus.

The outputs of the groups of the last stage Z are the corresponding groups Q of the external device outputs of the same name - groups QK of the total number (sum) of groups of single and zero bits, groups QU of the number (sum) of unit bits in the input binary number D1, D2, ..., DN, w of groups QG zero and single bits (w = 1, 2, ..., N + 1), and the outputs of the odd groups QG (wf) ⁰ correspond to the groups of zero bits, and the outputs of the even groups QG (wf) ¹ correspond to the groups of single bits, and the output QDL, corresponding to the left bit of the input binary number D1. In FIG. Figure 3 shows the output data formats for N bits of the input data and for M = 4 and N = 8.

The proposed device operates as follows.

The inputs of the device receive N bits of the input binary number unsigned D1, D2, ..., DN, which are divided into L groups of M bits in the group (N = L * M). The least significant bit of D1 is the left most significant bit of the input binary number. Moreover, the M bits of each of the L groups of the input binary number D1, D2, ..., DN, starting from the first bit to the Mth bit, are connected in reverse order, respectively, with the inputs AM, AM-1, ..., A1 of the first cascades 3 ₁ in the corresponding blocks of elements 1 ₁ , 1 ₂ , ..., 1 _{L of the} first type of the first stage of the same groups L.

In the first stages of the shapers 3 ₁ in the corresponding blocks of elements 1 ₁ , 1 ₂ , ..., 1 _L in each corresponding M bit group of input data A1, A2, ..., AM, the most significant single bit is detected and at the outputs of the group of elements OR 4 ₁ , 4 ₂ , ..., 4 _(M-1) , combined in a chain, the input data A1, A2, ..., AM are converted into an ordered binary code "00 ... 011 ... 1" with the units arranged in a row, starting from the least significant bits, where the left unit corresponds to the highest unit in the corresponding input group. At the same time, the ordered binary code "00 ... 011 ... 1" together with the highest input bit AM of the shaper of the first stage 3 ₁ are received on the internal bus S ₁ .

Then, in modules 7 _{1 of the} count of the lowest ordered units, the number of units on the internal bus S ₁ is counted. The number of units is an addition to M to the number of leading zeros in the input data group A1, A2, ..., AM. The obtained number of units goes to the second inverse group of the second term of the first adder 8 ₁ and is subtracted from the number of bits M of the input data group specified by the binary code “M” at the inputs of the first term, with a unit value at the transfer input CI = 1 of the adder, which corresponds to the subtraction operation for unsigned numbers. Moreover, the difference obtained at the outputs of the first adders 8 ₁ corresponds to the number (sum) of zero bits in the first group G1 ⁰ in the corresponding group of the input binary number D1, D2, ..., DN. The calculated value code of the quantity (sum) of zero bits in the first group G1 ^{0 is} supplied to the outputs of the first group G1 of the corresponding blocks of elements 1 ₁ , 1 ₂ , ..., 1 _L.

For example, for blocks of elements 1 ₁ , 1 ₂ , ..., 1 _L in table 1 with M = 4 for the input number A4-A1 = 0010, an ordered binary code is generated at the outputs of the elements OR 4 ₁ , 4 ₂ , 4 _{3 of the} first stage 3 ₁ “011”, which, together with the high order bit A4 = 0 of the input data, is fed to the first internal bus S1 and the code “2” of the sum of the lowest units is calculated in module 7 ₁ . Further, this code “2” is supplied to the inverse inputs of the first adder 8 ₁ and is subtracted from the code “4” of the number of bits M = 4 of the input number (4-2). Thus, at the outputs of the first “zero” group G1 ⁰ , a code “2” (G1 ⁰ = 2) will be generated, corresponding to the number of first leading zeros in the input data group A4-A1.

At the same time, in the first stages of the shapers 3 _{1, the} least significant bits of the groups of input data are A4-A1, the corresponding groups of the input binary number D1, D2, ..., D (N-1) corresponding to the unit values in the ordered binary code "00 ... 011 ... 1" at the outputs groups of elements OR 4 ₁ , 4 ₂ , ..., 4 _(M-1) are inverted in the group of elements “EXCLUSIVE OR” 5 ₁ , 5 ₂ , ..., 5 _(M-1) , which can be considered as elements of a “controlled inverter” , and arrive at the outputs O1, O2, ..., O (M-1) of the first stage of the formers 3 ₁ and further to the inputs A1, A2, ..., A (M-2) of the next second stage 3 ₂ . In this case, the bits of the first group of unit bits G2 ¹ , the corresponding group of the input binary number A1, A2, ..., AM, are converted to zero values, and the bits of the second group of zero bits (the third group in the input number G3 ⁰ ) are converted to unit values, etc. d. For example, in table 1, in the group of elements “EXCLUSIVE OR” (XOR) 5 ₁ , 5 ₂ , 5 ₃ (at M = 4) of the first stage 3 _{1, the} two least significant bits are inverted, and the code “001” is generated (for input data A4- A1 = 0010), which is supplied to the corresponding outputs O3, O2, O1 and then to the inputs A3, A2, A1 of the second stage 3 ₂ .

In the second stages of the shapers 3 ₂ , similarly to the first stages 3 ₁ , the highest single bit is detected and an ordered binary code "00 ... 011 ... 1" is generated, which is fed to the internal bus S ₂ , where the left unit corresponds to the highest unit - the beginning of the third group (third the group contains zero bits) in the groups of the input binary number D1, D2, ..., DN, and the number of zeros in the ordered binary code "00 ... 011 ... 1" corresponds to the sum of two groups - the first group of zero bits and the second group of unit bits, in the corresponding group input binary of D1, D2, ..., DN. In the second modules 7 ₂ counts of the least ordered units are similarly carried out the calculation of the number of units. The resulting code of the quantity (sum) of units from the outputs of the second modules 7 ₂ goes to the second inverse group of the second term of the second adders 8 ₂ , and is subtracted from the code “M” reduced by the number (sum) of zero bits in the first group, which comes from the outputs the first module 7 ₁ counts the least ordered units to the inputs of the first term of the second adder 8 ₂ and then the outputs of the second adders 8 ₂ generate values corresponding to the number (sum) of units in the second group of unit bits G2 ^{1 of the} corresponding groups of the input binary about the number D1, D2, ..., DN, which goes to the outputs of the second group G2 of the corresponding blocks of elements 1 ₁ , 1 ₂ , ..., 1 _L. Further, similarly, in the group of elements “EXCLUSIVE OR” 5, the least significant bits of the groups of input data A of the second stage 3 ₂ are inverted, which are fed to the outputs O1, O2, ..., O (M-2) of the second stage.

For example, in table 1 in the second stage 3 ₂ at the outputs of the elements OR 4 ₁ , 4 ₂ (at M = 4) an ordered binary code “01” is generated, which, together with the value of the high order bit A3 = 0, are received on the internal bus S ₂ . Then, in the second module 7 ₂ , the code of the sum of units “1” is calculated and then on the second adder 8 ₂ the code “1” is generated as a difference (2-1) corresponding to the number of units in the first group in the input data group A, and which is transmitted to the outputs of the second “unit” group G2 ¹ = 1. Then, in the group of elements EXCLUSIVE OR XOR 5 ₁ , 5 ₂ (at М = 4) of the second stage 3 _{2, the} least significant bits are inverted, and the code “00” is generated, which goes to the corresponding outputs O1, O2 and then to the inputs A1, A2 of the third stage 3 ₃ .

Then, in the same way, the detection of the highest single bits is carried out, the calculation and generation of codes for the values of the number of bits in the third 3 ₃ , fourth 3 ₄ and subsequent stages of the formers. If in the input data in the cascades of the shapers 3 there are no single bits, then in the digits of the corresponding senior groups zero values are formed.

For example, in table 1 (with M = 4 for input data A4-A1 = 0010) in the third stage 3 ₃ , an ordered binary code “0” is similarly generated at the output of the OR 4 ₁ element, which goes to the internal bus S ₃ , then in the third module 7 ₃ calculates the code of the sum of units “0” and then on the third adder 8 ₃ the code “1” is generated as a difference (1-0) corresponding to the number of zeros in the second group of bits in the input data group. Thus, at the outputs of the second “zero” group G3 ⁰ , the code “1” (G3 ⁰ = 1) will be generated, corresponding to the number of zero bits in the third group in the input number. Further, since there are no single bits at the outputs of the cascade, zero codes are generated in the next fourth and fifth groups G4 ^{1 =} 0 and G5 ⁰ = 0.

At the same time, the output O1 of the last (M-1) cascade of the formers 3 _{(M-1) is} fed to the first direct input of the OR element with one inverse input 6, the second inverse input of which receives the value of the highest Mth digit AM of the input code of the corresponding block of elements 1. Thus, a unit value is formed at the output of the element OR 6 at a zero value of the highest order AM = 0 or at a unit value at the output O1 of the last (M-1) stage 3 _(M-1) .

In addition, simultaneously in the blocks of elements 1 ₁ , 1 ₂ , ..., 1 _{L, the} lower first bits of all internal buses from the group S1, S2, ..., S _(M-1) and the outputs of the elements OR 6 go to the corresponding inputs of the unit counting unit 9 , in which the number of units is counted, and this value corresponds to the total number of groups of zero and single bits in the corresponding input group A4-A1 of the input binary number D1, D2, ..., DN, and this value goes to the output group K of the corresponding block of elements 1 ₁ , 1 ₂ , ..., 1 _L.

For example, in table 1 (with M = 4 for input data A4-A1 = 0010) the least significant bits of the internal buses S ₁ , S ₂ , S ₃ , on which the values are set to "110", and the inverse value of the highest digit A4 (AM) input data groups (unit value for input data 0010) from the output of the OR element 6 go to the inputs of unit 9 of the unit count, in which the code “3” will be generated corresponding to the total number (sum) of groups of zero and single bits for the input binary number A4-A1 = 0010, which enters the output group K = 3. In this case, also in the groups of bits the values will be set: G1 ⁰ = 2, G2 ¹ = 1, G3 ⁰ = 1, G4 ¹ = 0 and G5 ⁰ = 0.

Similarly, for the input binary number D1-D4 = 0101 (table 1), with the highest value of the highest digit A4 = 0 (AM) of the input data, the values of zero and single bits G1 ⁰ = 1, G2 ¹ = 1, G3 ⁰ = 1, G4 ¹ = 1, G5 ⁰ = 0 and the total number of groups K = 4, corresponding to the maximum number of groups with the number of bits M = 4 of the input data group.

In table 1, for the input data group “all zeros” A4-A1 = 0000, the “zero” ordered binary code “000” is also generated at the outputs of the OR 4 ₁ , 4 ₂ , 4 ₃ elements of the first stage 3 ₁ , and then “zero” is also generated "The sum code is" 0 "of the smallest units in module 7 ₁ (also A4 = 0), which goes to the inverse inputs of the first adder 8 ₁ and is subtracted from the code" 4 "for the number of bits M = 4 of the input number (4-0) . Thus, the code “4” (G1 ⁰ = 4) corresponding to the number of all zero bits in the input number A4-A1 = 0000 will be generated at the outputs of the first “zero” group G1 ⁰ . In this case, zero values will also be set on all internal buses S1, S2, S3, including the lower first bits of the tires, which are supplied to the inputs of the unit counting unit 9, which also receives a single value from the output of the OR element 6 with one an inverse input, which is connected to the highest bit of the input data, A4 = 0, and therefore, the outputs of module 9 will generate the code "1", which goes to the outputs of the total number of groups K = 1.

For the input data group A4-A1 = 1XXX, with a single value of the highest order A4 = 1 (AM) of the input data (X is any value), an ordered binary is always generated at the outputs of the OR elements 4 ₁ , 4 ₂ , 4 _{3 of the} first stage 3 ₁ the code is "111" units, for which, together with A4 = 1 is calculated code amount "4" elementary units in the module July _1, which is supplied to inverted inputs of the first adder January ₈ and subtracted from "4" code number of bits M = 4 input group number data (4-4). At the same time, the code “0” (G1 ⁰ = 0) will be generated at the outputs of the first “zero” group G1 ⁰ , which corresponds to the absence of the highest “zero” group in the input data, when the senior bit has a unit value A4 = 1.

For example, in table 1 for the input data group D1-D4 = 1010, since the outputs of the OR 4 ₁ , 4 ₂ , 4 ₃ elements of the first stage 3 ₁ have the ordered binary code all units “111”, then the XOR 5 ₁ group of elements , 5 ₂ , 5 _{3 of the} first stage 3 _1, all bits are inverted, and the code "101" is generated, which is fed to the corresponding outputs O1, O2, O3 and then to the inputs A1, A2, A3 of the second stage 3 ₂ .

In the second stage 3 ₂ at the outputs of the elements OR 4 ₁ , 4 ₂ , an ordered binary code “11” is formed, which, together with the value of the high order bit A3 = 1, goes to the internal bus S ₂ . Then, in the second module 7 ₂ , the code of the sum of units “3” is calculated and then on the second adder 8 ₂ the code “1” is generated as a difference (4-3), corresponding to the number of unit bits in the first group in the input data group, and which goes to the outputs the second “unit” group G2 ¹ = 1. Next, the subsequent values of the zero and unit groups are similarly calculated and the values of G1 ⁰ = 0, G2 ¹ = 1, G3 ⁰ = 1, G4 ¹ = 1, G5 ⁰ = 1 are set at the outputs of the groups of the block of elements 1. At the same time, the unit values from the least significant bits of all internal buses S1, S2, S3 and from the output of the OR element 6 with one inverse input (since the unit value is set at the output O1 of the third stage 3 ₃ ) are supplied to the inputs of the unit counting unit 9 and the code “4 »The total number of groups K = 4.

For the input binary number “all units” A4-A1 = 1111, the ordered binary code “111” and the code “all units” “1111” are also generated at the outputs of the OR elements 4 ₁ , 4 ₂ , 4 _{3 of the} first stage 3 ₁ , for which the sum code “4” of the smallest units is generated in module 7 ₁ (since in this case A4 = 1), which goes to the inverse inputs of the first adder 8 ₁ and is subtracted from the number of bits code M = 4 of the input number (4-4) . Thus, the code “0” (G1 ⁰ = 0) will be generated at the outputs of the first “zero” group G1 ⁰ , which corresponds to the absence of the “zero” first group in the input number. Further, in the group of elements “EXCLUSIVE OR” 5 ₁ , 5 ₂ , 5 ₃ (at М = 4) of the first stage 3 _1, all the least significant bits are inverted, and the code “000” is generated, which is supplied to the corresponding outputs O1, O2, O3 and further to the inputs A1, A2, A3 of the second stage 3 ₂ . Then, in the second stage 3 ₂ at the outputs of the elements OR 4 ₁ , 4 ₂ , a binary code “00” is generated, which is fed to the internal bus S ₂ . Then, in the second module 7 ₂ , the code of the sum of units “0” is calculated, which is subtracted from the code “4” from the first module 7 ₁ (4-0) and the code “4” is generated corresponding to the number of unit bits in the group, which is supplied to the outputs of the second “ unit "group G2 ¹ = 4. At the same time, the unit value from the least significant bit of the first internal bus S ₁ and the zero value from the output of the OR 6 element are input to the unit counting unit 9 and the code “1” of the total number of groups K = 1 is generated.

In addition, at the same time, in each block of elements 1, the inputs of the groups of the second multi-group adder 10 receive the values from the outputs of all even adders 8 (th), in which the codes corresponding to the groups of single bits are generated, and the output group of the adder 10 is the output group U of the quantity (sum) single bits in the corresponding input group of the corresponding block of elements 1. Also, the output from the upper left bit of the input AM of the corresponding block of elements 1 is transmitted to the DL output of each block of elements 1 ₁ , 1 ₃ , ..., 1 _L.

Further, the values from the outputs of the odd blocks of elements 1 ₁ , 1 ₃ , ..., 1 _{1 (L-1)} (LF) and the outputs of the even blocks of elements 1 ₁ , 1 ₂ , ..., 1 _L (Th) of the first stage are paired to the corresponding groups inputs of the same name, respectively, of the first and second sections of the inputs of the respective blocks 2 ₂₁ , 2 ₂₂ , ..., 2 _{2L / 2 of the} second stage (Fig. 1).

In each block of elements 2 _{ij of the} second type, in the modules for generating the shift code and the code for the total number of groups 14, based on the values of the left highest bits 1DL of the first section and 2DL of the second section and the value of the lowest zero bit 1k0 of group 1K of the total number of groups of unit and zero bits of the first section , the formation of the value of the shift code SK. In this case, the value of the shift code SK always takes an even value, i.e. in the module shift groups 13 is shifted to an even number of groups. The SK code is generated on the basis of table 2 and in accordance with table 3. Based on table 3, after minimizing for the correction functions (-1 and +1) the code for the sum of the number of groups (2K + 1K) and the code for the amount of shift on the SK bus, the following expressions are obtained :

Q17 (-1) = 1DL xor 1k0 xor 2DL,

Q16 (-1) = not 1DL and 2DL,

Q15 (+1) = not 2DL and 1DL.

Next, on the fifth adder 18, the value corresponding to the 1K code of the total number (sum) of groups of single and zero bits in the first section is reduced by one, when the sum modulo two values 1DL, 2DL and 1k0 at the output of the EXCLUSIVE OR element 17 takes a single value. At the sixth adder 19, in accordance with the values set at the outputs of the fifth adder 18, the first 15 and the second 16 AND elements with one inverse input, the corresponding SK shift code is generated by 1Kcht, (1Kcht-2), (1Kchch-1) th , (1Knch + 1) th groups of digits (table 3).

In each block of elements 2 _{ij of the} second type, the values from the corresponding groups of inputs of zero and single bits 1G of the first sections of the inputs of the blocks of elements 2 _{ij of the} second type go to the groups of inputs of the first terms of the corresponding adders from the third group of adders 11, for which the values of the second groups of inputs a respective first (2 * M ^(i-2) +1) groups groups shear modulus outputs 13, wherein the values of respective groups of inputs and a single zero bit inputs 2G second sections element blocks _ij 2 of the second type are shifted by etnoe number of groups corresponding to the code SK, which is formed on the module 14. The outputs of shift is performed as a logical right shift towards older groups G, with the introduction of zero values into bits left younger groups G (Table 2).

The values from the outputs of the groups of the third group of adders 11 are the corresponding first (M * 2 ^(i-2) +1) groups of outputs of the zero and single bits G of the corresponding block of elements 2 _{ij of the} second type. In this case, the outputs of the groups of the shear modulus 13, from the group of outputs (M * 2 ^(i-2) +2) to the group of outputs (M * 2 ^(i-1) +1), are the outputs of the corresponding groups G of unit G ¹ and zero bits G ⁰ , from the group of outputs (M * 2 ^(i-2) +2) to the group of outputs (M * 2 ^(i-1) +1), the corresponding block of elements 2 _{ij of the} second type.

In addition, the inputs of the first and second terms of the fourth adder 12 receive values from the inputs of the number of unit bits of the first section 1U and the second section 2U and the output (output) of the fourth adder 12 forms the number (sum) of unit bits in two corresponding blocks of elements, which is transmitted to the corresponding group U outputs of the block of elements 2 _ij .

The group of inputs of the first term of the seventh adder 20 from the outputs of the fifth adder 18 receives the code value of the total number of groups of single and zero bits 1K from the inputs of the first section, taking into account the correction for the shift of the groups of the second section (table 2), and the group of inputs of the second term of the seventh adder 20, the code value of the total number of groups of single and zero bits 2K is supplied from the inputs of the second section and at the outputs of the seventh adder 20, a code is generated of the sum of the total number of groups of single and zero bits for two sections, which is received from the corresponding group To the outputs of the block of elements 2 _ij .

The outputs of the groups of the last stage Z are the corresponding groups Q of the external device outputs of the same name - groups QK of the total number of groups of unit and zero bits, groups QU of the number of unit bits in the input binary number D1, D2, ..., DN, w of the group QG of zero and unit bits (w = 1, 2, ..., N + 1), and the outputs of the odd groups QG (wнч) ⁰ correspond to groups of zero bits, and the outputs of the even groups QG (wн) ¹ correspond to groups of single bits, and the output QDL corresponding to the left bit of the input binary number D1.

The output formats are shown in FIG. 3. The total number of groups of single and zero bits w is (N + 1). Moreover, in the output, the first group G1 ⁰ and subsequent odd groups contain the number of bits in the “zero” groups, and the second group G2 ¹ and subsequent even groups contain the number of bits in the “single” groups. The number of bits in each group of single and zero bits is] log ₂ (N + 3-w) [(a larger integer), where w = 1, 2, ..., N + 1. The total number (sum) of groups K contains] log ₂ (N + 1) [digits. The number (sum) of unit bits of U contains] log ₂ (N + 1) [bits.

Consider the operation of the device for input data D1-D8 = 0010 0101, with N = 8, M = 4, L = 2, Z = 2. The inputs of block elements 1 ₁ 0010 receives the data group and the inputs of the block elements 1, ₂ into a group of data 0101. According to Table 1 for the data input of data groups forming respective groups of outputs which are coupled to inputs of the block group ₁ elements 2.

The inputs of the block of elements 2 ₁ will receive the following code values:

- to the first section from the outputs of the block of elements 1 ₁ - 1G1 ⁰ = 2, 1G2 ¹ = 1, 1G3 ⁰ = 1, 1G4 ¹ = 0, 1G5 ⁰ = 0, 1K = 3, 1U = 1, 1DL = 0,

- to the second section from the outputs of the block of elements 1 ₂ - 2G1 ⁰ = 1, 2G2 ¹ = 1, 2G3 ⁰ = 1, 2G4 ¹ = 1, 2G5 ⁰ = 0, 2K = 4, 2U = 2, 2DL = 0.

From the input it follows that in the first section there are three groups of bits 1K = 3 and the third group (right) 1G3 ⁰ is a group of zero bits, and in the second section there are four groups of bits 2K = 4 and the first group (left) 2G1 ^{0 is} also a group of zero bit. Since in the first section there are three groups of bits 1K = 3 „, the least significant bit 1k0 = 1 takes a single value, and the left bits 1DL = 0 and 2DL = 0 in two sections take zero values, then in accordance with tables 2 and 3 in the module 14, the correction code “-1” is formed (a single value at the output of the “EXCLUSIVE OR” element 17), the value of the shift code SK = 1K-1 = 2 (sixth adder 19), and the value of the total number (sum) of the groups K = 2K + 1K- 1 = 4 + 3-1 = 6 (seventh adder 20). Therefore, in shift module 13, all groups of unit and zero bits of the second section are shifted into two groups SK = 2 and zero values are entered into the bits of the first two left groups 0 (2G1 ⁰ ) and 0 (2G2 ¹ ). Next, the inputs of the terms of the third group of adders 11 of the block of elements 2 ₁ receive the codes of the groups of single and zero bits of the first section and the shifted values from the outputs of module 13. At the adder 11 _{3, the} input codes 1G3 ⁰ = 1 and 2G1 ⁰ = 1 are summed up and the code of the third group is generated G3 ⁰ = 2, and on the other adders one of the terms assumes a zero value. Thus, the following values will be generated at the outputs of the device corresponding to the groups of bits: QG1 ⁰ = 2, QG2 ¹ = 1, QG3 ⁰ = 2, QG4 ¹ = 1, QG5 ⁰ = 1, QG6 ¹ = 1, QG7 ⁰ = 0, QG8 ¹ = 0, QG9 ⁰ = 0 and the total number (sum) of groups QК = 6 (seventh adder 20). At the same time, on the fourth adder 12, a code of the quantity (sum) of unit bits QU = 1U + 2U = 1 + 2 = 3 is formed, as well as the value of the left bit QDL = 0.

For the input data, D1-D8 = 1111 0000, with N = 8, M = 4, L = 2, Z = 2, the following code values will be received at the inputs of the block of elements 2 ₁ :

- to the first section from the outputs of the block of elements 1 ₁ - 1G1 ⁰ = 0, 1G2 ¹ = 4, 1G3 ⁰ = 0, 1G4 ¹ = 0, 1G5 ⁰ = 0, 1K = 1, 1U = 4, 1DL = 1,

- to the second section from the outputs of the block of elements 1 ₂ - 2G1 ⁰ = 4, 2G2 ¹ = 0, 2G3 ⁰ = 0, 2G4 ¹ = 0, 2G5 ⁰ = 0, 2K = 1, 2U = 0, 2DL = 0.

From the input it follows that in the first section the number of groups of bits is 1K = 1 and the left bit takes a single value 1DL = 1, while the first group of zero bits contains the zero code 1G1 ⁰ = 0, and the second group contains the code “4” 1G2 ¹ = four. The second section also contains one group 2K = 1, while the left bit takes the zero value 2DL = 0, and the first group of zero bits contains the code “4” 2G1 ⁰ = 4. Since in the first section one group of bits 1K = 1, the least significant bit 1k0 = 1 takes a single value, and the left bit 1DL = 1 takes a single value and in the second section the left bit 2DL = 0 takes a zero value, then in accordance with the tables 2 and 3 in module 14, the correction code “+1” is generated (a single value at the output of the first AND element with one inverse input 15), the value of the shift code SK = 1K + 1 = 2 (sixth adder 19). and the value of the total number (sum) of groups K = 2K + 1K = 1 + 1 = 2 (seventh adder 20). Therefore, in shift module 13, all groups of unit and zero bits of the second section are shifted into two groups SK = 2 and zero values are entered into the bits of the first two left groups 0 (2G1 ⁰ ) 2 and 0 (2G2 ¹ ). In this case, on all adders, one of the terms assumes a zero value, and the first group of zero bits of the second section 2G1 ⁰ = 4 goes to the inputs of the third adder 11 ₃ . The following values will be generated at the device outputs corresponding to the groups of bits: QG1 ⁰ = 0, QG2 ¹ = 4, QG3 ⁰ = 4, QG4 ¹ = 0, QG5 ⁰ = 0, QG6 ¹ = 0, QG7 ⁰ = 0, QG8 ¹ = 0 , QG9 ⁰ = 0, the total number (sum) of groups QК = 2 (seventh adder 20). the code of the quantity (sum) of unit bits QU = 1U + 2U = 4 + 0 = 4 (fourth adder 12), as well as the value of the left bit QDL = 1.

The units 7 and 9 counting modules can be implemented as devices shown in an analog device for determining the number of units in an ordered binary number (RU No. 2522875, IPC Н03К 21/12, announced May 24, 2012, published July 20, 2014, Bull. No. 20) or in the prototype a device for determining the number of units (zeros) in a binary number (RU No. 2446442, IPC G06F 7/50, Н03К 21/00, announced April 11, 2011, published March 27, 2012, Bull. No. 9). The shift modules of groups 13 can be implemented on a matrix of multiplexers with a simultaneous shift of all bits of groups, in which a logical shift to the left is implemented with zero values entered in the bits of left groups. A multi-group adder 10 can be implemented as a tree structure adder containing multi-bit adders at each level (J. F. Wakerley. Designing digital devices. In 2 volumes. - M.: Postmarket, 2002. - 1088 p., Fig. 6.15. p. 606-609).

The proposed device can be used for hardware implementation of statistical tests developed by the Laboratory of Information Technology of the National Institute of Standards and Technology (NIST, USA), the purpose of which is to determine the measure of randomness of binary sequences generated by random number generators. In particular, the proposed device implements:

- frequency bit test, the essence of which is to determine the ratio between zeros and ones in the entire binary sequence. The goal is to find out if the number of zeros and ones in the sequence is really about the same. The test evaluates how close the proportion of units is to 0.5.

- frequency block test, the essence of which is the determination of the fraction of units inside a block of length K bits. The goal is to find out if the repetition frequency of units in a block of length K bits is approximately equal to K / 2.

- a test for a sequence of identical bits, the essence of which is to calculate the total number of rows (groups) in the original sequence, where a series is a continuous subsequence of identical bits. A series (group) of lengths of bits consists of absolutely identical bits, begins and ends with a bit containing the opposite value. The goal is to conclude whether the number of rows (groups) consisting of ones and zeros with different lengths really corresponds to their number in a random sequence. In particular, the units and zeros in the initial sequence are determined either quickly or slowly.

When processing the results of physical experiments, the proposed device provides the detection of events (groups of single bits) and intervals between events (groups of zero bits), determining the duration of events and intervals between them, as well as determining the total number and duration of events.

Introduction to the proposed device group structure provides:

- in the blocks of elements 1 of the first stage, the reduction by (L-1) of cascades of 3 shapers of ordered binary numbers (in the device without introducing groups at N = 16 it is necessary (N-1) = 15 cascades, and at N = 32 - (N-1 ) = 31 cascades, in the proposed device with M = 4 bits in a group, (M-1) = 4-1 = 3 cascades are entered in each group and for L = 4 groups it is necessary (M-1) * L = (4- 1) * 4 = 12 cascades, and for N = 32 and for L = 8 groups - (M-1) * L = (4-1) * 8 = 24 cascades);

- in the blocks of elements 1 of the first stage, the reduction in the amount of hardware — the total number of elements OR 4 and the elements “EXCLUSIVE OR” 5, since the sum of the elements in the cascades of the shapers 3 is determined by the number of cascades and increases in arithmetic progression, and, therefore, decreases with a decrease in the number of cascades (at N = 16 in a device without introducing groups, the number (sum of arithmetic progression) of OR 4 elements is N * (N-1) / 2 = 16 * (16-1) / 2 = 120 elements and also 5 EXCLUSIVE OR elements »120 elements, and for N = 32, N * (N-1) / 2 = 32 * (32-1) / 2 = 496 elements OR 4 and elements “EXCLUSIVE OR” 5, in the proposed device, when introducing groups of M = 4 digits, in each group, M * (M-1) / 2 = 4 * is entered (4-1) / 2 = 6 elements, and for L = 4 groups, 24 OR 4 elements and an “EXCLUSIVE OR” element are required, 5 each, and for N = 32, M = 4 and L = 8 groups, each (M * (M-1) / 2) = (4 * (4-1) / 2) * 8 = 48 elements OR 4 and elements “EXCLUSIVE OR” 5);

- in units 7 and 9 of the unit count, the number of stages is proportional to log ₂ N (M) of the total number of bits N or bits M in the group and, therefore, the number of stages and elements in stages is reduced in the proposed device;

- increase in speed, since in cascades of 3 shapers of ordered binary numbers, serial data is transferred between stages, then in the proposed device, when groups are introduced, serial transmission within groups is also performed sequentially, but simultaneously in all groups, therefore, the data transfer time is reduced by (N -1) / (M-1) times (at N = 16 and M = 4 (N-1) / (M-1) = (16-1) / (4-1) = 5 times, and at N = 32 and M = 4 (N-1) / (M-1) = (32-1) / (4-1) = 10.3 times), then when transferring data in the account modules 7 and 9, the transmission time is proportional to log ₂ N or log ₂ M, consequently decreases significantly with a decrease in the number of cascades, and then in the proposed device, the data transmission time in steps is proportional to log ₂ Z of the number of steps Z.

Thus, the binary codes corresponding to the number of zero and single bits in the groups of the input binary number are generated at the outputs of the proposed device, while the number of zeros is indicated in the odd groups QG ⁰ nch, and the number of units in the even groups QG ^{1 is} read and the total number is formed QK groups and the total number of unit bits QU.

The above information allows us to conclude that the proposed device solves the problem - identifying groups of identical bits, determining the number of single and zero bits in groups and determining the total number of groups, has regular nodes and connections, and corresponds to the claimed technical result — simplification of increasing the bit depth of input data reduced hardware costs and increased device performance.

Claims (18)

A group structure device for detecting groups of zero and single bits and determining their number contains N bits of the input binary number D1, D2, ..., DN, which are divided into L groups of M bits in the group (N = L * M), Z steps of element blocks , where Z =] log ₂ L [+1 (] [is a larger integer), and the first step contains L blocks of elements 1 ₁ , 1 ₂ , ..., 1 _{L of the} first type, and each i-th step, starting from the second step to the Z-th stage, contains L / 2 ^(i-1) blocks of elements 2ij of the second type, where i = 2, 3, ..., Z, j = 1, 2, ..., L / 2 ^(i-1) , moreover, N bits of the input binary number D1, D2, ..., DN in groups of M bits are connected to the inputs of the same input groups of blocks of elements 1 ₁ , 1 ₂ , ..., 1 _{L of the} first type of the first stage, the outputs of the odd blocks of elements 1 ₁ , 1 ₃ , ..., 1 _{1 (L-1)} (LF) and the outputs of even blocks of elements 1 ₂ , 1 ₄ , ..., 1 _L (Th) of the first stage are paired with the corresponding groups of the inputs of the same name, respectively, of the first and second sections of the inputs of blocks of elements 2 ₂₁ , 2 ₂₂ , ..., 2 _{2L / 2 of the} second type of the second stage, and the outputs of the odd blocks of elements 2ij (low) and the outputs of the even blocks of elements 2 ij (th) of each i-th stage, starting from the second stage to the penultimate (Z-1) -th stage, are paired with the corresponding groups of the inputs of the same name, respectively, of the first and second sections of the inputs of the blocks of elements 2ij of the next stages, starting from the third stage to the last Z-stage, and the outputs of the groups of the block of elements 2zj of the last stage Z are the corresponding groups Q of the external outputs of the same name from the device of the group QK of the total number of groups of single and zero bits, groups QU of the number of unit bits in the input binary number D1, D2, ..., DN, w groups QG of zero and single bits (w = 1, 2, ..., N + 1), and the outputs of the odd groups QG (wf) ⁰ correspond to the groups of zero bits, and the outputs of the even groups QG (wf) ¹ correspond to the groups of single bits, and the output QDL corresponds to the left bit of the input binary number D1, moreover, the output group QK of the total number of groups of unit and zero bits and the output group QU of the number of unit bits in the input binary number D1, D2, ..., DN each contain] log ₂ (N + 1) [(larger integer) bits, output groups of zero and single bits of QGw contain by] log ₂ (N + 3-w) [(larger integer) bits, each block of elements 1 ₁ , 1 ₂ , ..., 1 _{L of the} first type of the first stage contains (M-1) cascades of shapers of ordered binary numbers 3 ₁ , 3 ₂ , ..., 3 _(M-1) , which are combined into a pyramidal structure, and each vth cascade 3 _v (v = 1, ..., (M-1)) contains a group of (Mv) elements OR 4 ₁ , 4 ₂ , ..., 4 _(Mv) , a group of (Mv) elements EXCLUSIVE OR 5 ₁ , 5 ₂ , ..., 5 _(Mv) , a group of (M + 1-v) inputs A1, A2, ..., A (M + 1-v), a group of (Mv) outputs O1, O2, ..., O (Mv) to the next stage and a group of (M + 1-v) bit outputs of the corresponding v-th internal bus Sv from the group S1, S2, ..., S (M-1), as well as in each block of elements 1 ₁ , 1 ₂ , ... 1 _{L of the} first type of the first stage, an OR element with one inverse input 6, a group of (M-1) modules of counting the lowest ordered units 7 ₁ , 7 ₂ , ..., 7 _{( M-1)} , the first group of M adders 8 ₁ , 8 ₂ , ..., 8 _M with an inverse group of inputs of the second term, unit counting unit 9 and the second multi-group adder 10, and each v-th adder 8 _v contains] log ₂ (M + 3-v) [(larger integer) category of inputs of terms, and the last _Mth adder 8 _M contains two bits of inputs of terms, moreover, M bits of each of the L groups of the input binary number D1, D2, ..., DN, starting from the first bit to the Mth bit, are connected in the reverse order, respectively, with the inputs AM, AM-1, ..., A1 of the first stages 3 ₁ in the corresponding blocks of elements 1 ₁ , 1 ₂ , ..., 1 _{L of the} first type of the first stage, groups of the same name L, in each v-th cascade of shapers 3 _{v, the} first (Mv) inputs A1, A2, ..., A (Mv), except for the last input A (M + 1-v), are connected to the second inputs of the corresponding elements of the same name OR 4 ₁ , 4 ₂ , ..., 4 _(Mv) and the second inputs of the elements of the same name EXCLUSIVE OR 5 ₁ , 5 ₂ , ..., 5 _(Mv) , and the first inputs of the first (M-v-1) elements OR 4 ₁ , 4 ₂ , ..., 4 _{( Mv-1)} from the group of OR elements, starting from the first OR element, connected to the outputs of the corresponding subsequent elements 4 ₂ , 4 ₃ , ..., 4 _(Mv) from the group of OR elements, starting from the second element, the first input of the last (Mv) - th element 4 _(Mv) from the group OR is connected to the last input of the A (M + 1-v) v-th cascade of drivers 3 _v , outputs (Mv) of the elements OR 4 ₁ , 4 ₂ , ..., 4 _(Mv) are also connected to the first inputs of the corresponding elements of the same name EXCLUSIVE OR 5 ₁ , 5 ₂ , ..., 5 _(Mv) , the outputs of which are a group (Mv) of outputs O1, O2, ..., O (Mv) to the next stage of each v-th stage 3 _v , and the outputs of all (Mv) elements OR 4 ₁ , 4 ₂ , ..., 4 _(Mv) are also the same first lower (Mv) bits of the corresponding v-th internal bus Sv from the group S1, S2, ..., S (M-1), starting from the first bit, and the last A (M + 1-v) -th input of the v-th stage 3 _{v is} is the senior (M + 1-v) -th bit of the corresponding v-th internal bus Sv, moreover, in the first (M-2) cascades of the shapers, in addition to the last (M-1) -th cascade of 3 _(M-1) , (Mv) outputs O1, O2, ..., O (Mv) in the next (v + 1) - stage 3 _{(v + 1) is} connected to the corresponding (Mv) inputs of the same name A1, A2, ..., A (Mv) of the next (v + 1) th stage of the shapers 3 _{(v + 1)} , all bits of each v-th internal bus Sv from the group S1, S2, ..., S (M-1), in each block of elements 1 ₁ , 1 ₂ , ..., 1 _{L of the} first type of the first stage, are connected to the inputs of the corresponding module of the same name 7 _v from the group of (M-1) modules of counting the lowest ordered units, and the outputs of each v-th module 7 _{v are} connected to the inverse group of inputs of the second term of the corresponding v-th adder 8 _v and the first group of direct inputs of the first term of the next (v + 1 ) -th adder 8 _{(v + 1)} from the first group of M adders 8 ₁ , 8 ₂ , ..., 8 _M , the outputs of which are corresponding to the first M groups of output data of the single and zero bits G1, G2, ..., GM of the corresponding block of elements 1 ₁ , 1 ₂ , ..., 1 _{L of the} first type, and the last one-bit output of the group of single and zero bits G (M + 1) of the corresponding block of elements 1 ₁ , 1 ₂ , ..., 1 _{L of the} first type is connected to the O1 output of the last (M-1) stage 3 _(M-1) , which is also connected to the input of the second inverse group of the last M-th adder 8 _M and the first direct input of the element OR with one inverted input 6, a second inverted input coupled with the older m-th input of the first stage AM corresponding to March ₁ its block elements 1 _1, 1 _2, ..., _L 1 of the first type, and is the output of the left bit DL corresponding block elements 1 _1, 1 _2, ..., _L 1 of the first type, in addition, the binary number code "M" is supplied to the group of direct inputs of the first term of the first adder 8 ₁ , and the logical unit value "1" is fed to the CI carry entries of all M adders 8 ₁ , 8 ₂ , ..., 8 _M , the inputs of the groups of the second multi-group adder 10 are connected to the outputs of all even adders 8 (th) in each block of elements 1 ₁ , 1 ₂ , ..., 1 _{L of the} first type, and the group of outputs of the adder 10 is the output group U of the number of unit bits in the input data of the corresponding block elements 1 ₁ , 1 ₂ , ..., 1 _{L of the} first type, the lower first bits of all (M-1) internal buses of ordered binary numbers S1, S2, ..., S (M-1) are connected to the corresponding inputs of the unit counting unit 9, in which the Mth input is connected to the output of the OR element with one inverse input 6, and the outputs of the unit counting module 9 are the output group K of the total number of groups of unit and zero bits of the corresponding block of elements 1 ₁ , 1 ₂ , ..., 1 _{L of the} first type, and the group of the total number of groups K contains] log ₂ (M + 1) [(larger integer) digits, moreover, each block of elements 2 _{ij of the} second type of the second, third, ..., Z-th stage contains a third group of (M * 2 ^(i-2) +1) adders 11, a fourth adder 12, a group shift module 13, a shift code generation module and the code of the total number of groups 14, which contains the first element And with one inverse input 15, the second element And with one inverse input 16, the element EXCLUSIVE OR 17, the fifth adder 18, the sixth adder 19, the seventh adder 20, moreover, in each block of elements 2 _{ij of the} second type, the corresponding (M * 2 ^(i-2) +1) groups of inputs of zero and single bits 1G of the first sections of the inputs are connected to the groups of inputs of the first terms of the corresponding adders from the third group of adders 11, in which the second the groups of inputs of the second terms are connected to the corresponding first (M * 2 ^(i-2) +1) output groups of the module of the shift of groups 13, in which the information groups of the inputs are connected to the corresponding (M * 2 ^(i-2) +1) groups of zero inputs and single bits 2G of the second sections of the inputs of the blocks of elements s _ij 2 of the second type, and the control inputs of the shear modulus of groups 13 to set the value of the bus number SK shifts connected to the outputs of the module of code formation and code shift total number of groups 14, moreover, in the module for generating the shift code and the code of the total number of groups 14, the input of the left bit 1DL of the first section of inputs is connected to the first direct input of the first element And 15 with one inverse input, to the second inverse input of the second element And 16 with one inverse input, the first input of the element EXCLUSIVE OR 17 and is the output of the left bit DL of the corresponding block of elements 2 _ij , the input of the left bit 2DL of the second section of inputs is connected to the second inverse input of the first element And 15 with one inverse input, with the first direct input of the second element And 16 with one inverse input and with the second input of an EXCLUSIVE OR 17 element, the third input of which is connected to the lowest zero bit 1k0 of group 1K of the total number of groups of unit and zero bits of the first section, as well as all bits of group 1K are connected to the group of inputs of the second term of the fifth adder 18, in which all digits of the first term are interconnected and connected to the output of the EXCLUSIVE OR element 17, the group of outputs of the fifth adder 18 is connected to the group of inputs of the second term of the sixth adder 19 and to the group of inputs of the first Guy seventh adder 20, in which the group of inputs of the second term is connected to the discharge groups 2K total number of groups of single and zero bits of the second section, and the group of the seventh adder output 20 is the output groups to the total number of groups of single and zero bits of the corresponding block elements 2 _ij second type , and also all bits of the first term of the sixth adder 19 are interconnected and connected to the output of the second element And with one inverse input 16, and the transfer input CI of the sixth adder 19 is connected to the output of the first element And with one inverse input 15, and the bits of the group of outputs of the sixth adder 19 are the bits of the bus to set the value of the number of shifts SK, the outputs of the groups of the number of unit bits of the first section 1U and the second section 2U are connected respectively to the groups of the first and second terms of the fourth adder 12, the group of outputs of which is the group of outputs U of the corresponding block of elements 2 _{ij of the} second type, in addition, in each block 2 _{ij of the} second type, the outputs of the third group of adders 11 and the second groups of outputs of the shift module of groups 13, starting from the group of outputs (M * 2 ^(i-2) +2) to the group of outputs (M * 2 ^{(i- 1)} +1) are the outputs of the corresponding groups G of unit and zero bits of the corresponding block of elements 2 _{ij of the} second type.

Images