RU2541431C1 - Device for determining role function of member of creative team - Google Patents

Abstract

FIELD: radio engineering, communication.

SUBSTANCE: device consists of a synchronisation unit 8, which is provided with a source data input bus, units of sensors 2 for encoding responses 3, preliminary scoring 4, calculating partial indicators 5, selecting team members 9, evaluating a role function 10, calculating a generalised indicator 6, display 7 and a control unit 1, which is provided with a source data input bus. The control inputs/outputs of the control unit 1 are connected to the control outputs/inputs of corresponding units.

EFFECT: faster operation and high accuracy of evaluating characteristics of test subjects.

6 cl, 17 dwg

Description

The invention relates to computer technology, in particular, to devices for psychological modeling of actions of persons involved in practically important situations, with a subsequent assessment of these actions, to the field of professional suitability tests and related training, to the field of psychometric measurements of intelligence carried out in psychology. The device can be used to conduct individual rapid tests of professional suitability in the absence of resources for a more complete and accurate assessment of the level of readiness of a person for innovative activities in practically important situations, as well as in the formation of teams for the effective solution of highly specialized knowledge-intensive creative tasks.

A well-known automated system for training and knowledge control (Patent RU No. 211,095 C1 G09B 7/00), made on the basis of a personal computer, consisting of a control panel, a device for inputting answers and reactions of a student, information input units, a decoder of control signals, a data buffer, a device control and synchronization, address counter, memory block, digital-to-analog converter and analog multiplexer.

The first analogue allows the use of information stimulation at the subsensory level of perception in the process of accelerated individual learning and knowledge control.

The disadvantage of the first analogue is the cumbersomeness and relatively high cost of one workplace due to the use of a personal computer as the base.

A well-known testing system is “Teletesting” (RU 2186423 C2, G09B 7/00), designed to test the volume and quality of knowledge in distance learning, with automated correspondence determination of professional suitability, with organizational and managerial, career guidance and individual and personal counseling, as well as certification control personnel of enterprises. The system is based on computer network information technologies and includes preparatory modules, testing modules, telecommunication modules, and analysis and processing modules.

The second analogue allows you to implement remote simultaneous testing of many subjects located geographically in different places, and ensures the secrecy of test tasks to increase the reliability of the results.

The disadvantage of the second analogue is the relative complexity of the system and the high cost of one workplace, the need to develop special software for calculating test scores in the telecommunication process.

The closest analogue (prototype) to the claimed device in its technical essence is a knowledge control device (RU 2110096 C1, G09B 7/07), which includes several student remotes, angle-to-angle converters into a code, on-off sensors block, instrument control panel, electric circuit formation of ratings, scoreboard and power source.

The prototype scheme allows you to use it for rapid testing of subjects, while significantly reducing the cost of one workplace.

However, the prototype device has disadvantages:

1. The dependence of the design of the device on the number and complexity of the tests. In this regard, to conduct a comprehensive assessment of the test subject with a large number of heterogeneous test tasks, proportional complexity of the device design is required (difficult to scale);

2. The need for centralized instrument control to set test keys and control the testing process.

The aim of the invention is to develop a testing device that provides a quick assessment of the level of innovative intelligence of the subjects, simplifying scaling in accordance with the required number of subjects through the use of stand-alone individual test panels, decentralization of control of the testing process through the use of microprogram technology, the possibility of using heterogeneous test tasks with a large number questions of varying complexity and answer options due to use of random access memory devices.

This goal is achieved by the fact that in a known testing device containing a sensor unit, D-bit, where D≥2, the information output of which is connected to the D-bit information input of the response coding unit, a private indicator calculation unit, the fifth control output of which is connected to the first the control input of the display unit, and N-bit, where N≥2, the control input of the private indicator calculation unit is connected to the N-bit control output of the control unit, P-bit, where P≥2, the information input of which о is connected to the P-bit control output of the sensor unit, the fifth control output of which is connected to the third control input of the control unit, and the third control output of the sensor unit is connected to the first control input of the control unit and the eighth control input of the display unit, K-bit and M-bit where K≥2 and M≥2, the information outputs of the control unit are connected respectively to the K-bit information input of the response coding unit and to the M-bit information input of the display unit, additionally a synchronization unit, a preliminary score calculation unit, a generalized indicator calculation unit, a team member selection unit and a role function evaluation unit are introduced, S-bit, where S≥2, the information input of which is connected to the S-bit information output of the private indicator calculation unit, the second and the third control inputs of the role function evaluation unit are connected respectively to the seventh and eighth control outputs of the control unit, the fourth, fifth and sixth information outputs of the role function evaluation unit are connected respectively, to the fourth, fifth and sixth information inputs of the display unit, the first information input of the selection unit is connected to the fifth information output of the private indicator calculator, the fourth and fifth control inputs of the selection unit are connected respectively to the seventh and eighth control outputs of the control unit, the second and third information the outputs of the selection unit are connected respectively to the second and third information inputs of the display unit, the S-bit information input of the calculation unit is generally Nogo indicator connected to the S-bit data output unit for calculating the partial indices. The third, fourth and fifth synchronizing inputs of the general indicator calculation unit are connected to the seventh, eighth and ninth synchronizing outputs of the synchronization unit, respectively. The second control input and the seventh control S-bit input of the general indicator calculation unit are connected respectively to the first control output of the sensor unit and to the S-bit tenth control output of the control unit. The S-bit sixth information output of the general indicator calculation unit is connected to the S-bit information input of the indication unit. S-bit information input and output of the preliminary scoring unit are connected respectively to the S-bit information output of the response coding unit and the input of the private indicator calculation unit. The S-bit control input and the sixth control input of the preliminary scoring unit are connected respectively to the S-bit fifth control output of the control unit and to the third output of the database. The fourth synchronizing input of the preliminary scoring unit and the third synchronizing input of the private indicator calculation unit are connected to the sixth output of the synchronization unit. The second and third clock inputs of the preliminary scoring unit are connected respectively to the third and fourth clock outputs of the clock block, the second clock output of which is connected to the clock input of the response coding block. The fifth synchronizing output of the synchronization unit is connected to the second synchronizing input of the private indicator calculation unit. The eleventh control output and the twelfth control input of the control unit are connected respectively to the eleventh control input and the tenth output of the synchronization unit. The first control input of the synchronization unit is connected to the first control output of the sensor unit. The synchronization unit and the control unit are respectively equipped with F-bit, where F≥2 and W-bit, where W≥2, inputs of the initial synchronization and control data.

The block of preliminary scores consists of cascading the first accumulative adder, divider, multiplier and second accumulative adder, the first and second OR elements, cascaded by the S-bit information signal, the outputs of which are connected respectively to the zeroing inputs of the first and second accumulative adders. S-bit information input of the first and output of the second accumulative adders are respectively S-bit information input and output of the block of intermediate scoring. The clock input of the divider is the second clock input of the block of intermediate scoring. The input of the first "OR" element and the input of the multiplier are combined and are the third clock input of the block of intermediate scoring. The first input of the second OR element is the fourth control input of the block of intermediate scoring. The fourth S-bit control input of the divider and the combined second inputs of the first and second elements "OR" are respectively the S-bit seventh and sixth control inputs of the block preliminary calculation of points.

The generalized indicator calculation unit consists of a cascade multiplier, an accumulative adder, a square root calculator, and a divider that are connected in cascade according to the S-bit information signal. The first S-bit information input of the multiplier and the third S-bit information output of the divider are respectively S-bit information input and output of the general indicator calculation unit. The S-bit control input of the divider is the seventh S-bit control input of the general indicator calculation unit. The synchronizing input of the multiplier, the input of the square root calculator and the input of the divider are the third, fourth and fifth synchronizing inputs of the generalized indicator calculation unit, respectively. The control input of the accumulative adder is the second control input of the general indicator calculation unit.

The synchronization unit consists of a clock generator, a trigger key, a decoder, a clock counter, a comparator, an address counter, a memory register, a delay element, and an "OR" element. The information output of the comparator is connected to the “Stop” input of the trigger key and through the delay element to the information input of the address counter, D-bit, where D≥2, the third and first information inputs of the comparator are connected respectively to the D-bit information output of the clock counter and the register output memory, R-bit, where R≥3, the control output of the address counter is connected to the R-bit control inputs of the memory register and decoder. The information output of the trigger key is connected to the information input of the clock counter and the information input of the decoder. The output of the clock generator is connected to the first information input of the trigger key. The control input “Start” of the trigger key is connected to the output of the “OR” element, the sixth input of which is the eleventh control input of the synchronization unit. The information outputs (from the third to the tenth) of the decoder are the correspondingly synchronizing outputs (from the 2nd to the 9th) of the synchronization block. The fourth, sixth, eighth and ninth information outputs of the decoder are connected respectively to the second, third, fourth and fifth inputs of the “OR” element. The information output of the comparator is the tenth control output of the synchronization unit. The inputs “Zero setting” of the clock counter and the address counter are combined and are the first control input of the synchronization block. The D-bit information input / output and the R-bit address input of the memory register form the F-bit input of the synchronization source data, where F = D + R.

The role function evaluation unit consists of a memory register, first, second and third binary number comparators, a second information output of the memory register is connected to the first information input of the first comparator and a third information input of the third comparator, a third information output of the memory register is connected to the third information input of the first comparator and to the first information input of the second comparator, the fourth information output of the memory register is connected to the third information input of the second the comparator and to the first information input of the third comparator, the first 5-bit information input of the memory register being the first information input of the role function evaluation unit, the fifth and sixth control inputs of the memory register are the second and third control inputs of the role function evaluation unit, information outputs of the first, second and the third comparators are the fourth, fifth, and sixth information outputs of the role function evaluation unit, respectively.

The collective member selection block consists of a memory register, a majority element and an “And” element, the second, third and fourth information outputs of the memory register are connected respectively to the first, second and third information inputs of a majority element and an “And” element, the first information input of the memory register being the first information input of the selection unit, the fifth and sixth control inputs of the memory register are respectively the fourth and fifth control inputs of the selection unit, and the fourth information outputs ementa "AND" and the majority element are respectively second and third informational outputs of the selection unit.

The letters indicated in the claims have the following meaning:

S - the number of bits of the code corresponding to the maximum number of points awarded for solving one test task.

P - the number of bits of the code corresponding to the maximum number of test tasks.

D - the number of bits of the code corresponding to the maximum number of questions in the test task.

M - the number of bits of the code, reflecting the maximum amount of data of one test task.

R is the number of bits of the address input of the BS decoder (in this case, R≥3).

V is the number of bits of the code corresponding to the maximum value of the generalized indicator.

Q - the number of bits of the code corresponding to the number of evaluated private indicators (in this case, Q≥3).

U is the number of bits corresponding to the capacity of the control inputs of the graphic LCD.

Thanks to new sets of essential features, the implementation of the device provides a two-level assessment of the overall indicator of innovative intelligence, their simplicity of modifying the structure and contents of tests, and the automation of all procedures, i.e. increasing the efficiency of research, in addition, the device allows the selection of candidates according to specified criteria, to determine for each participant the preferred nature of the tasks of the innovation process.

The invention is illustrated by drawings, which show:

figure 1 is a structural diagram of a device;

figure 2 is a structural diagram of a control unit (BU);

figure 3-6 is a structural diagram of the firmware modules of the control unit;

figure 7 is a structural diagram of a block of sensors (DB);

on Fig is a structural diagram of a block of coding responses (BKO);

figure 9 is a structural diagram of a block of preliminary scores (BPPB);

figure 10 is a structural diagram of a unit for calculating private indicators (BVChP);

figure 11 is a structural diagram of a unit for calculating a generalized indicator (BVOP);

in Fig.12 is a structural diagram of a display unit (BI);

in Fig.13 is a structural diagram of a synchronization unit (BS);

on Fig is a structural diagram of a trigger key BS;

on Fig is a structural diagram of a block for the selection of team members (BVChK);

in Fig.16 is a structural diagram of a role function evaluation unit (BORF);

on Fig - three-component model of innovative intelligence;

on Fig is a block diagram of the algorithm of operation of the device.

The claimed device shown in figure 1, consists of a control unit 1, a sensor unit 2, a response coding unit 3, a preliminary score calculation unit 4, a private indicator calculation unit 5, a generalized indicator calculation unit 6, an indication unit 7, a synchronization unit 8, unit selection of team members 9 and unit evaluation of role functions 10.

D-bit, where D≥2, the information output 2.2 of the OBD 2 is connected to the D-bit information input 3.1 of the BCO 3. The fifth control output 5.5 of the I / O 5 is connected to the first control input of 7.1 BI 7. N-bit, where N≥2, the control input 5.6 BVCHP 5 is connected to the N-bit control output 1.6 BU 1. P-bit, where P≥2, information input 1.2 BU 1 is connected to the P-bit control output 2.4 OBD 2. Fifth 2.5 control output DB 2 is connected to the third 1.3 control input of control unit 1. Third control output 2.3 of database 2 is connected to the first control input 1.1 of control unit 1 and the eighth to the control input 7.8 BI 7. K-bit 1.4 and M-bit 1.9, where K≥2 and M≥2, information outputs of BU 1 are connected respectively to the K-bit information input 3.4 of BKO 3 and to the M-bit information input 7.9 of BI 7 S-bit, where S≥2, information input 6.1 of BVOP 6 is connected to S-bit information output 5.4 of BVChP 5. Third 6.3, fourth 6.4 and fifth 6.5 synchronizing inputs of BVOP 6 are connected to seventh 8.7, eighth 8.8 and ninth 8.9 synchronizing BS outputs 8. Second control input 6.2 and seventh control S-bit input 6.6 BVOP 6 are connected respectively to the first control output 2.1 of DB 2 and to the S-bit control output 1.10 BU 1. S-bit information output 6.6 BVOP 6 is connected to the S-bit information input 7.7 BI 7. S-bit information input 4.1 and output 4.5 BPPB 4 are connected respectively to the S-bit information output 3.3 of BKO 3 and input 5.1 of the I / O 5. The S-bit control input 4.7 and control input 4.6 of BPPB 4 are connected respectively to the S-bit fifth 1.5 control output of BU 1 and to output 2.3 of DB 2. Fourth synchronization input 4.4 BPPB 4 and thirds synchronizing input 5.3 of BCHP 5 is connected to output 8.6 of BS 8. Second 4.2 and third 4.3 synchronizing inputs of BPPB 4 are connected respectively to the third 8.3 and fourth 8.4 synchronizing outputs of BS 8. The second synchronizing output 8.2 of BS 8 is connected to the synchronizing input 3.2 of BKO 3. Fifth 8.5 the synchronizing output of BS 8 is connected respectively to the second 5.2 synchronizing input of the BCHP 5. The eleventh 1.11 control output and the twelfth 1.12 control input of the control unit 1 are connected respectively to the eleventh 8.11 control input and the tenth 8.10 output of the BS 8. The first control input 8.1 BS 8 is connected to the first 2.1 control output of the database 2, and the BS 8 and the control unit 1 are equipped with F-bit, where F≥2 and W-bit, where W≥1, inputs of the source data synchronization and control.

The control unit 1, the structural diagram of which is presented in Fig. 1, is intended for storing test task data, assigning weight coefficients of complexity of test tasks, and also for issuing the necessary data to the main units of the device. The implementation of the block may be different, in particular, as shown in figure 2, on the basis of the principle of construction of the firmware [4, 5, 6].

BU 1 provides timely data output to such elements of the device as multipliers, dividers, comparators. It consists of four cascade connected in P-bit, where Р≥2, the control signal of typical modules 1.1, 1.2, 1.3, 1.4, which implement the principle of operation of the firmware, memory register 1.5 for storing test data, register shift 1.6 with parallel recording and sequentially reading from the queue of the FIFO type, the “OR” 1.7 element and the delay element 1.8. The first input 1.7.1 of the "OR" element is connected to the fourth 1.6.4 information output of the shift register 1.6, and the second 1.7.2 input of the "OR" 1.7 is the third 1.3 control input of BU 1. Information output 1.7.3 of the element "OR" 1.7 is the eleventh 1.11 control output of BU 1. The first 1.6.1, second 1.6.2 and third 1.6.3 information inputs of shift register 1.6 are connected respectively to the seventh 1.2.7 control output of the second module 1.2, the eighth 1.3.8 control output of the third module 1.3 and seventh 1.4.7 control output of the fourth module 1.4. The fifth control input 1.6.5 of shift register 1.6 is the twelfth 1.12 control input of BU 1. The eighth 1.1.8 and P-bit tenth 1.1.10 control outputs of the first module 1.1 are connected respectively through a delay element 1.8 to the second 1.5.2 and the first 1.5.1 control inputs of the memory register 1.5. The second 1.7.2 control input of the “OR” element 1.7 is the third 1.3 control input of the control unit 1. The P-bit control input 1.1.1 of the first module 1.1 is the second 1.2 control input of the control unit 1. Resetting inputs “Set 0” 1.1.9, 1.2 .8, 1.3.9, 1.4.8 modules 1.1-1.4 are combined and form the first 1.1 control input of control unit 1. Information outputs 1.1.4, 1.2.5, 1.3.5, 1.3.6, 1.4.5, 1.4.6 modules 1.1, 1.2, 1.3, 1.4 are respectively K-bit fourth 1.4, S-bit fifth 1.5, N-bit sixth 1.6, seventh 1.7, eighth 1.8 and S-bit tenth 1.10 control outputs of control unit 1. M-bit, where М≥, 2, output 1.5.4 p The memory register 1.5 is the ninth 1.9 control output of the control unit 1.

Each typical module, the schemes of which are shown in FIGS. 3, 4, 5, consists of a comparator 1.1.1-1.4.1, a memory register 1.1.2-1.4.2, an address counter 1.1.3-1.4.3 and a delay element 1.1 .4-1.4.4. A typical module has the following structure, which can be considered by the example of the first module (see figure 3). The address input 1.1.2.6 of the memory register 1.1.2 is connected to the information output 1.1.3.2 of the address counter 1.1.3, and the first information output 1.1.2.1 of the memory register 1.1.2 is connected to the first information input 1.1.1.1 of the comparator 1.1.1. The output of the comparator 1.1.1.2 is connected through the delay element 1.1.4 to the information input 1.1.3.1 of the address counter.

The first module 1.1 (FIG. 3) provides the operation of the CCU 2. The third information input 1.1.1.3 of the comparator 1.1.1 is the first control input 1.1.1 of the module 1.1. The third control input 1.1.3.3 of the address counter 1.1.3 is the ninth control input 1.1.9 of module 1.1. The information output 1.1.1.2 of the comparator 1.1.1 is the eighth 1.1.8 control output of the module 1.1. D-bit third 1.1.2.3 and S-bit fourth 1.1.2.4 information outputs of the memory register 1.1.2 form K-bit, where K = D + S, the fifth control output 1.1.5 of module 1.1. The P-bit second information output 1.1.3.2 of the address counter 1.1.3 and the fifth information output 1.1.2.5 of the memory register 1.1.2 are the seventh 1.1.7 and sixth 1.1.6 control outputs of module 1.1, respectively. The first 1.1.3.1 information input of the address counter 1.1.3, the first 1.1.2.1, the third 1.1.2.3, the fourth 1.1.2.4 and the fifth 1.1.2.5 information outputs and the second 1.1.2.2 control input “Record” of the memory register 1.1.2 are used for preliminary input of initial data into module 1.1.

The second module 1.2 (see Fig. 4) provides the BPPB 4. The third 1.2.1.3 information input of the comparator 1.2.1 is the first control input 1.2.1 of module 1.2. The third control input 1.2.3.3 counter address 1.2.3. is the eighth 1.2.8 control input of module 1.2. The output of comparator 1.2.1.2 is the seventh 1.2.7 control output of module 1.2. The S-bit third 1.2.2.3 information output of the memory register 1.2.2 and the P-bit second 1.2.3.2 information output of the address counter 1.2.3 are the fifth 1.2.5 and sixth 1.2.6 control outputs of module 1.2, respectively. The first 1.2.3.1 information input of the address counter 1.2.3, the first 1.2.2.1 and the third 1.2.2.3 information outputs, as well as the second control input “Record” 1.2.2.2 of the memory register 1.2.2 are used for preliminary data input into module 1.2.

The third module 1.3 provides the operation of BVCHP 5, BV 9 and BORF 10. The P-bit third information input 1.3.1.3 of comparator 1.3.1 and the third control input 1.3.3.3 of address counter 1.3.3 are respectively the first 1.3.1 and ninth 1.3.9 control inputs of the module 1.3. The output 1.3.1.2 of the comparator 1.3.1 is the eighth 1.3.8 control output of the module 1.3. S-bit third 1.3.2.3, fourth 1.3.2.4 and fifth 1.3.2.5 the information outputs of the memory register 1.3.2 form N-bit, where N = 3S, the fifth 1.3.5 control output of module 1.3. The sixth 1.3.2.6 information output of the memory register 1.3.2 is the second control output of the module 1.3. The P-bit second output 1.3.3.2 of the address counter 1.3.3 is the seventh 1.3.7 control output of module 1.3. The first information input 1.3.3.1 of the address counter 1.3.3, the first 1.3.2.1, the third 1.3.2.3, the fourth 1.3.2.4, the fifth 1.3.2.5 information outputs and the second 1.3.2.2 control input of the memory register 1.3.2 are used for preliminary input of the initial data to module 1.3.

The fourth module 1.4 provides the operation of BVOP 6, BV 9 and BORF 10. The P-bit third information input 1.4.1.3 of the comparator 1.4.1 and the third control input 1.4.3.3 of the address counter 1.4.3 are the first 1.4.1 and the eighth 1.4.8 control inputs of the module 1.4. The third 1.4.2.3 and S-bit fourth 1.4.2.4 information outputs of the memory register 1.4.2 are respectively the third 1.4.3 and sixth 1.4.6 control outputs of the module 1.4. The output 1.4.1.2 of the comparator 1.4.1 is the seventh 1.4.7 control output of the module 1.4. The first information input 1.4.3.1 of the address counter 1.4.3, the first 1.4.2.1 and the fourth 1.4.2.4 information outputs, the second 1.4.2.2 control input of the memory register 1.4.2 are used for preliminary input of the initial data into the module 1.4.

The shift register 1.6 is designed to ensure the coordinated operation of BU 1 and BS 8. Through its information inputs 1.6.1-1.6.3, enable signals corresponding to a logical unit are recorded and are read in turn from the first to the third when clock pulses arrive at the fifth 1.6.5 input shift register.

DB 2, the diagram of which is presented in Fig. 7, is intended for encoding with binary code the test number and the response number that are selected by the subjects, as well as for resetting all the device counters. DB 2 can be implemented in various ways, for example, as shown in Fig. 7, using on-off sensors 2.1, 2.2, 2.3, 2.6, a test number counter 2.5, a reverse counter for the response number 2.4, and a memory register 2.7. The D-bit first information input 2.7.1 of the memory register 2.7 is connected to the D-bit information output 2.4.2 of the counter of the response number 2.4. The third control input 2.7.3 of the memory register 2.7 is connected to the output 2.6.2 of the sensor "Record" 2.6. The first information input 2.4.1 of the counter of the answer number 2.4 is connected to the output 2.1.3 of the sensor "Choice of answer" 2.1, and the third zeroing input 2.4.3 of the counter of the answer number is connected to the output of the sensor "Choice of test" 2.2. The first information input 2.5.1 of the counter of test number 2.5 is connected to the output 2.2.2 of the sensor "Select test" 2.2, and the third zeroing input 2.5.3 of the counter of test number 2.5 is connected to the output 2.3.2 of the sensor "Setting 0" 2.3. At the inputs 2.1.1 and 2.1.2 of the sensor "Choice of answer" 2.1, potentials corresponding to logical zero and one are fed, and at the inputs of the sensors 2.2.1, 2.3.1, 2.6.1 "Choice of test" 2.2, "Setting 0" 2.3 and “Record” 2.6 a potential corresponding to a logical unit is supplied. The output 2.3.2 of the sensor "Setting 0" 2.3 is the first 2.1 and third 2.3 control outputs of the database 2. The D-bit output 2.7.2 of the memory register 2.7 and the P-bit output 2.5.2 of the counter of test number 2.5 are respectively the second 2.2 and fourth 2.4 information outputs of the database 2. The output 2.6.2 of the sensor "Record" 2.6 is the fifth 2.5 control output of the database 2.

BKO 3 is designed to determine the number of points for the selected answer to the test task in accordance with the pre-set knowledge factors of the tasks. BCO 3 can be implemented in various ways, in particular, as shown in Fig.8.

BKO 3 consists of a comparator 3.1 and a multiplier 3.2. The first information input 3.2.1 of the multiplier 3.2 is connected to the output 3.1.2 of the comparator 3.1. The first 3.1.1 information input of the comparator 3.1 and the information output 3.2.3 of the multiplier 3.2 are respectively the D-bit information input 3.1 and the S-bit output 3.3 of the BKO 3, and the third input 3.1.3 of the comparator 3.1 and the fourth input 3.2.4 of the multiplier 3.2 form K-bit control input BKO 3, where K = S + D. The second clock input 3.2.2 of the multiplier is the second 3.2 clock input BKO 3.

BPPB 4 is designed to calculate the total and average number of points awarded according to the results of the test tasks and the preparation of the source data for calculating particular indicators of intelligence. BPPB 4 can be implemented in various ways, in particular, as shown in Fig.9.

BPPB 4 consists of the first accumulative adder 4.1, the divider 4.2, the multiplier 4.3, the second accumulative adder 4.4, the first 4.5 and the second 4.6 “OR” elements connected in cascade according to the 5-bit information signal. The multiplier 4.3 performs the squaring of the number received in binary code on its first input 4.3.1.

The first input 4.1.1 of the first and second output 4.4.2 of the second accumulative adder are respectively information input 4.1 and output 4.5 of the BPPB 4. The inputs 4.5.3 and 4.6.3 of the first 4.5 and second 4.6 of the “OR” elements are the sixth 4.6 control input of the BPPB 4 The second input 4.6.2 of the second OR element is the fourth 4.4 control input of the BPPB 4. The synchronizing inputs 4.2.2, 4.3.2 of the divider 4.2 and the multiplier 4.3 are the synchronizing inputs 4.2 and 4.3 of the BPP 4. S-bit fourth 4.2.4 control the input of the divider 4.2 is the seventh 4.7 control input BPPB 4.

Initial initialization of the accumulative totalizers 4.1 and 4.4 is carried out by supplying their control inputs 4.1.3 and 4.4.3 through the first 4.5 and second 4.6 elements of the “OR" potential of the logical unit, which comes through the sixth 4.6 control input BPPB 4. Preparation BPPB 4 to the next stage of work is carried out by zeroing the accumulative adders 4.1. and 4.4 clock pulses coming through the third 4.3 and fourth 4.4 synchronizing inputs BPPB 4.

BVChP 5 is intended for calculating the values of private indicators of intelligence and forming according to the results of the calculation of the information signal on BI 7, as well as for preparing the source data for calculating the value of the generalized indicator. ESP 5 can be implemented in various ways, in particular, as shown in Fig.10.

BVChP 5 consists of cascade connected on the S-bit information signal of the first 5.2 and second 5.3 dividers and 5.1 comparator.

The first input 5.2.1 of the first divider 5.2 and the output 5.3.3 of the second divider 5.3 are respectively the information input 5.1 and the output 5.4 of the I / O 5. The output 5.1.2 of the comparator 5.1 is the fifth 5.5 control output of the I / O 5. The synchronizing inputs 5.2.2 and 5.2.3 dividers 5.2 and 5.3 are respectively the second 5.2 and third 5.3 synchronizing inputs of the I / O 5, and the fourth information inputs 5.2.4, 5.3.4 of the dividers 5.2 and 5.3 and the third information input 5.1.3 of the comparator 5.1 form the control N-bit input 5.6 of the I / O 5 where N = 3S.

BVOP 6 is designed to calculate the value of the generalized indicator of intelligence of the subject and the formation of the information signal in BI 7. BVOP 6 can be implemented in various ways, in particular, as shown in Fig. 11.

BVOP 6 consists of a multiplier 6.1, an accumulative adder 6.2, a square root calculator 6.3, and a divisor 6.4, connected in cascade according to the S-bit information signal. The S-bit input 6.1.1 of the multiplier 6.1 and the output 6.4.3 of the divider 6.4 are respectively the information input 6.1 and the information output 6.6 of the BVOP 6. The synchronizing inputs 6.1.2, 6.3.2, 6.4.2 of the multiplier 6.1, the square root calculator 6.3, and the divider 6.4 are the synchronizing inputs 6.3-6.5 BVOP 6. S-bit input 6.4.1 of the divider 6.4 and the resetting input 6.2.2 of the accumulative adder 6.2 are respectively the control inputs 6.7 and 6.2 of the BVOP 6.

BI 7 is designed to present the subject with the contents of test tasks, as well as display the results of the calculation of particular and generalized indicators of intelligence. BI 7 can be implemented in various ways, in particular, as shown in Fig.12.

BI 7 consists of an address counter 7.1, decoders 7.2-7.6, a segment LCD 7.8, status indicators 7.9-7.12, triggers 7.13-7.15 and a graphic LCD 7.6. The graphic LCD 7.6 is controlled through its inputs 7.6.1 and 7.6.2, to which the outputs 7.5.2 and 7.4.2 of the fourth 7.5 and third 7.4 decoders are connected. The segment LCD 7 is controlled through its input 7.7.1, to which the output 7.2.2 of the first decoder 7.2 is connected. The status indicators 7.9-7.12 are controlled through the corresponding inputs 7.9.1-7.12.1, which are connected to the outputs 7.3.2-7.3.4 of the decoder 7.3 via triggers 7.13-7.15. The Not Ready indicator 7.12 is controlled through its input 7.12.1, which is connected to input 7.3 of the BI via a trigger 7.6. The Q-bit control input 7.3.1 of the second decoder 7.3 is connected to the output 7.1.2 of the address counter 7.1. The information input 7.1.1 of the address counter 7.1 is the first information input 7.1 of the BI 7. The S-bit information input 7.2.1 of the first decoder 7.2 is the seventh 7.7 information input of the BI 7. M / 2-bit information inputs 7.4.1 and 7.5.1 of the third 7.4 and the fourth 7.5 decoders form the ninth 7.9 M-bit information input of BI 7. The third 7.1.3 zeroing input of the address counter 7.1 is the eighth 7.8 control input of the BI 7.

BS 8 is designed to generate synchronizing signals and output them to other blocks in accordance with the algorithm of the device, it ensures the coordinated operation of such elements of the device as multipliers, dividers and a square root calculator. BS 8 can be implemented in various ways, in particular, as shown in Fig.13.

BS 8 consists of a clock pulse generator 8.1, a trigger key 8.2, a decoder 8.3, a clock counter 8.4, a comparator 8.5, an address counter 8.6 and a memory register 8.7, a delay element 8.8, and an “OR” element 8.9. The information output 8.5.3 of comparator 8.5 is connected to the input “Stop” 8.2.2 of the trigger key 8.2.2 and through the delay element 8.8 to the information input 8.6.1 of the address counter 8.6. The D-bit third 8.5.3 and the first 8.5.1 information inputs of the comparator 8.5 are connected respectively to the D-bit information output 8.4.1 of the clock counter 8.4 and the output 8.7.2 of the memory register 8.7 R-bit control output 8.6.2 of the address counter 8.6 connected to the R-bit control input 8.7.1 of the memory register 8.7 and input 8.3.2 of the decoder 8.3. The information output 8.2.3 of the trigger key 8.2 is connected to the information input 8.4.2 of the clock counter 8.4 and the information input 8.3.1 of the decoder 8.3. The output 8.1.1 of the clock 8.1 is connected to the first information input 8.2.1 of the trigger key 8.2. The control input “Start” 8.2.4 of the trigger key 8.2 is connected to the output 8.9.1 of the “OR” element 8.9, the sixth input 8.9.6 of which is the eleventh 8.1 control input of the synchronization unit 8, and the information outputs 8.3.3-8.3.10 of the decoder 8.3 are the corresponding synchronizing outputs 8.2-8.9 of the synchronization unit 8. The fourth 8.3.4, sixth 8.3.6, eighth 8.3.8 and ninth 8.3.9 the information outputs of the decoder 8.3 are connected to the inputs 8.9.2-8.9.5 of the element "OR" 8.9. The “Zero setting” inputs 8.4.3 of the clock counter 8.4 and 8.6.3 of the address counter 8.6 are combined and are the first 8.11 control input of the synchronization block 8. D-bit information output 8.7.2 and R-bit address input 8.7.1. memory register 8.7 form the F-bit input of the synchronization unit 8 for inputting synchronization data, where F = D + R.

The trigger key circuit 8.2 must pass pulses of equal duration. The trigger key 8.2 can be implemented in various ways, in particular, as shown in Fig.14. It consists of the first 8.2.1.1 and the second 8.2.1.3 RS-flip-flops, the inversion element 8.2.1.2 and the “AND” element 8.2.1.4. The output of the first trigger 8.2.1.1 is connected to the D-input of the second trigger 8.2.1.3. The output of the second trigger 8.2.1.3 is connected to the second input of the And element 8.2.1.4. The synchronizing input of the second trigger 8.2.1.3 is connected to the output of the inversion element 8.2.1.2. The inputs of the inversion element 8.2.1.2 and the element “AND” 8.2.1.4 are combined and form the first information input 8.2.1 of the trigger key 8.2. The inverse R-input of the first trigger 8.2.1.1 is the second 8.2.2 control input "Stop" trigger key 8.2. The trigger input of the first trigger 8.2.1.1 is the fourth 8.2.4 control input "Start" of the trigger key. The output of the “AND” element 8.2.1.4 is the third 8.2.3 information output of the trigger key 8.2. At the D-input, the inverse S-input of the first trigger 8.2.1.1 and the inverse inputs R and S of the second trigger 8.2.1.3, the potential of a logical unit is supplied.

BVChK 9 is intended for the selection of members of the creative team according to the normalized values of private indicators and the exclusion of those people who have two or more normalized private indicators have values below the threshold, as well as to identify individuals who can perform any role function (“universal”). BV 9 can be implemented in various ways, in particular, as shown in Fig.15.

BV 9 consists of a memory register 9.1, a majority element 9.2 and an “I” element 9.3, a second 9.1.2, a third 9.1.3 and a fourth 9.1.4 information outputs of the memory register are connected respectively to the first 9.2.1 and 9.3.1, the second 9.2 .2 and 9.3.2 and the third 9.2.3 and 9.3.3 information inputs of the majority element and the “And” element, the first 9.1.1 information input of the memory register being the first 9.1 information input of the selection block, the fifth 9.5 and sixth 9.6 control inputs of the register memory are, respectively, the fourth 9.4 and fifth 9.5 control inputs of the selection block, and inf rmatsionnye exits element "I" and 9.3 9.2.1 majority element are respectively second and third informational outputs of the selection unit.

BORF 10 is designed to determine a private indicator that has a maximum value in comparison with the values of other private indicators and assign the corresponding role function to a member of the creative team. BORF 10 can be implemented in various ways, in particular, as shown in Fig.16.

BORF 10 consists of a memory register 10.1, the first 10.2, the second 10.3 and the third 10.4 binary number comparators, the second information output 10.1.2 of the memory register is connected to the first 10.2.1 information input of the first comparator 10.2 and the third 10.4.3 information input of the third 10.4 comparator, the third information output 10.1.3 of the memory register 10.1 is connected to the third 10.2.3 information input of the first comparator 10.2 and the first 10.3.1 information input of the second comparator 10.3, the fourth information output 10.1.4 of the memory register 10.1 is connected to the third 10.3.3 the information input of the second 10.3 comparator and the first 10.4.1 information input of the third 10.4 comparator, the first S-bit information input 10.1.1 of the memory register being the first 10.1 information input of the role function evaluation unit 10, the fifth 10.1.5 and the sixth 10.1. 6, the control inputs of the memory register 10.1 are the second 10.2 and the third 10.3 control inputs of the role function evaluation unit 10, the information outputs of the first 10.2, second 10.3, and third 10.4 comparators are respectively the fourth 10.4, fifth 10.5, and sixth 10.6 information the outputs of the role function evaluation unit 10.

All elements of the described device blocks are made on standard potential-pulse elements and are described in the well-known literature:

- clock generator [7] p. 243-273, [1] p. 96;

- binary number divider [8, 9];

- binary number multiplier [8];

- decoder [7] p.112-127, [1] p.173-177;

- demultiplexer [7] p.128-134, [1] p.178-180, [2] p.76;

- comparator [1] p.230-234;

- accumulative adder [1] p. 149-150, 216-221, 228;

- counter [7] p. 189-205, [1] p. 102-106, 125-140, [2] p. 96;

- reverse counter [1] p.106-108;

- the multiplier [1] p.225-227;

- calculator of the square root [3];

- parallel shift register [7] p.177-189, [1] p.144-148;

- register memory [1] p. 272-274, [2] p. 95;

- flash memory [1] p.275-276;

- random access memory [1] p.263-272;

- triggers [7] p. 153-177, [1] p. 65-80;

- trigger key [1] p.93-94

- segment liquid crystal indicator [7] p.273-278;

- graphic liquid crystal indicator [10].

The claimed device is based on a method for evaluating innovative personality intelligence, known by the patent of the Russian Federation No. 2230490 dated 06/20/2004 [Bulletin No. 17 2004]. The method uses the concept of a three-vector model of innovative intelligence and a graphical representation of its calculated indicators as elements of a part of the area of the corresponding sectors of the unit circle discogram described in detail in [11, pp. 184-187].

The innovative intelligence of the personality is a way of thinking that allows one to realize and analyze the contradiction that has arisen in culture and put forward an idea and implement its creative solution, which was not at the previous stages of the development of culture, to eliminate it, and then, taking into account possible consequences, contribute to its socialization in culture. [11, p. 44].

In the three-vector model of innovative intelligence (AI), its components are: analytical intelligence (AI), creative intelligence (TI) and practical intelligence (PI) (Fig. 15). These components are measured corresponding coefficients that are direct indicators of the innovation Intelligence: _A K, K _T, K _P.

, $$K_T^{\min }$$

, $$K_{П}^{\min }$$

, которые определяют с учетом области инновационной деятельности будущего специалиста (техническая, управленческая, педагогическая и т.д.). В частности, исследования показали, что в области инженерно-технических знаний необходимо принять $$K_A^{\min }=65-80$$

(определяется величиной IQ); $$K_{Т}^{\min }={\widehat{Е}}_{\ddot{I}}^{\min }=0,3$$

(определяется по тестам «креативность» и «креафорность»). Порядок расчета частных показателей К_А, К_Т, К_П можно рассмотреть на примере вычисления К_Т. Тест представляет собой тестовую батарею, включающую восемь субтестов, объединенных в одну психодиагностическую методику, направленную на измерение общего уровня креативности (К_Т), а также уровней ее n промежуточных частных показателей (в данном случае творческое мышление (М), любознательность (Л), оригинальность (О), воображение (В), интуиция (И), эмоциональность (Э), чувство юмора (Ю), творческое отношение к профессии (П)).Source data includes minimum acceptable levels $$K_A^{\min }$$

, $$K_T^{\min }$$

, $$K_P^{\min }$$

which determine, taking into account the field of innovation, a future specialist (technical, managerial, pedagogical, etc.). In particular, studies have shown that in the field of engineering knowledge it is necessary to accept $$K_A^{\min }=65-80$$

(determined by the value of IQ); $$K_T^{\min }={\widehat{E}}_{\ddot{I}}^{\min }=0,3$$

(determined by the tests "creativity" and "creafor"). The procedure for calculating particular indicators K _A , K _T , K _P can be considered by the example of calculating K _T. The test is a test battery, including eight subtests, combined into one psycho-diagnostic technique, aimed at measuring the general level of creativity (K _T ), as well as the levels of its n intermediate particular indicators (in this case, creative thinking (M), curiosity (L), originality (O), imagination (B), intuition (I), emotionality (E), sense of humor (Yu), creative attitude to the profession (P)).

In this example, the number of subtests and the number of obtained intermediate partial numerical test results are n = 8. The value of the indicator for each subtest is determined by counting the number of matches of the answers of the subject with the answers of the key.

Initial for further evaluation of intermediate psychodiagnostic indicators are numerical test results for n subtests. The normalization of the values of intermediate indicators is carried out by dividing the obtained numerical results for each subtest by the maximum possible numerical result P _m for this subtest.

$$P_{Pj}/P_{mj}=r_j(\mathrm{one})$$

The discogram (Fig), is a unit circle whose radius R _o = 1. For the adopted sampling step Δr, the number m of inscribed concentric circles is m = 1 / Δr-1. In this case, Δr = 0.1, i.e. m = 9.

The radius of the i-th concentric circle r _i = 1-iΔr.

In this example, r ₁ = 1-1 × 0.1 = 0.9; r ₂ = 0.8, etc.

; $${Л}_{н}^{о}=0,7$$

; $${О}_{н}^{о}=0,6$$

и т.д.After normalizing the values of the numerical test results, they are rounded up taking into account the adopted sampling step Δr. For example, the obtained values: M ⁿ = 0.78; L ⁿ = 0.71; About ⁿ = 0.58, etc. rounded to the nearest multiple of Δr = 0.1, i.e. after rounding, normalized values: $$M_n^{\mathrm{about}}=0,8$$

; $$L_n^{\mathrm{about}}=0,7$$

; $${\mathrm{ABOUT}}_n^{\mathrm{about}}=0,6$$

etc.

; $$r_2={Л}_{н}^{о}=0,7$$

; $$r_3={О}_{н}^{о}=0,6$$

и т.д.The rounded numerical results for all subtests are displayed on the discogram by hatching part of the corresponding sector of the unit circle from its center to the arc of the inscribed concentric circle whose radius r _j is equal to the rounded numerical result of the corresponding subtest, i.e. $$r_{\mathrm{one}}=M_n^{\mathrm{about}}=0,8$$

; $${\mathrm{<figure-callout\; id="2"\; label="r"\; filenames="00000036.png,00000037.png"\; state="\{\{state\}\}">r</figure-callout>}}_2=L_n^{\mathrm{about}}=0,7$$

; $${\mathrm{<figure-callout\; id="3"\; label="r"\; filenames="00000042.png,00000043.png"\; state="\{\{state\}\}">r</figure-callout>}}_3={\mathrm{ABOUT}}_n^{\mathrm{about}}=0,6$$

etc.

The obtained intermediate results provide the basis for determining both particular and generalized K _t psychodiagnostic indicators through the ratio of the hatched S _j and the total S _o areas of the respective sectors. This fact is due to the fact that in order to achieve the highest indicators, the test person must correctly answer all questions, which corresponds to the values of all particular indicators equal to unity, and, therefore, the entire unit circle is shaded. For private indicators that differ from unity, only part of the unit circle (sector) will be shaded. The ratio of the hatched and total areas of the unit circle (sector) shows the level of the total (private) indicator without involving any subjective assessments of the researcher.

. Следовательно, j-й промежуточный психодиагностический показатель K_j определяется как $$K_j=S_j/S_o=r_j^2$$

, а частный психодиагностический показатель К_Т по полной тестовой батарее определяется выражением:For a unit circle, the total area S _{o of} its any j-th angular sector S _o = π / n [m ² ]; the area S _{j of the} hatched part of the angular sector at the level of the inscribed concentric circle with radius r _j is $$S_j=\pi r_{\mathrm{<figure-callout\; id="2"\; label="j"\; filenames="00000036.png,00000037.png"\; state="\{\{state\}\}">j</figure-callout>}}^2/n[m^2]$$

. Therefore, the j-th intermediate psychodiagnostic indicator K _j is defined as $$K_j=S_j/S_o={\mathrm{<figure-callout\; id="2"\; label="r\; j"\; filenames="00000036.png,00000037.png"\; state="\{\{state\}\}">r\; </figure-callout>}}_j^{}$$

, and a private psychodiagnostic indicator K _T for a full test battery is determined by the expression:

$$K_T=(\mathrm{one}/n){\displaystyle \sum _{j=\mathrm{one}}^n{r}_j^2}(2)$$

The generalized indicator of innovative intelligence in accordance with the three-vector model (Fig. 16) is estimated as the rms value of the normalized particular indicators:

$${\mathrm{TO}}_{\mathrm{AND}\mathrm{AND}}=(\mathrm{one}/3)\sqrt{{({\mathrm{TO}}_{\mathrm{BUT}}^N)}^2+{({\mathrm{TO}}_T^N)}^2+{({\mathrm{TO}}_P^N)}^2}(3)$$

, $$K_T^{\min }$$

, $$K_{П}^{\min }$$

).The normalized values of particular indicators are determined in relation to the specified minimum permissible values ( $$K_A^{\min }$$

, $$K_T^{\min }$$

, $$K_P^{\min }$$

)

The obtained elementary relations allow us to automate the processing and final assessment of the psychodiagnostic indicator using a computer.

Thus, the first action performed by the claimed device is the summation of the number of points R _p for the correct execution of subtests.

The second action of the device is the normalization of intermediate indicators of testing by dividing by the formula (1).

The third step is to calculate the root mean square value according to the formula (2), for which it is necessary to perform:

;a) squaring $${\mathrm{<figure-callout\; id="2"\; label="r\; j"\; filenames="00000036.png,00000037.png"\; state="\{\{state\}\}">r\; </figure-callout>}}_j^{}$$

;

;b) summation $${\displaystyle \sum _{j=\mathrm{one}}^{\mathrm{<figure-callout\; id="2"\; label="n\; r\; j"\; filenames="00000036.png,00000037.png"\; state="\{\{state\}\}">n\; </figure-callout>}}{r}_j^{}{}_2^{}}$$

;

.c) dividing by the number of tests in the battery of tests (1 / n) $${\displaystyle \sum _{j=\mathrm{one}}^{\mathrm{<figure-callout\; id="2"\; label="n\; r\; j"\; filenames="00000036.png,00000037.png"\; state="\{\{state\}\}">n\; </figure-callout>}}{r}_j^{}{}_2^{}}$$

.

The fourth action is the determination of those subjects in whom the values of two or more particular indicators are less than the established permissible minimum values. For this, comparison and selection on a majority basis is necessary.

The fifth action is the determination of the subjects, which corresponds to the role function "universal". For this, it is necessary to determine the subjects for whom the values of all particular indicators exceed the threshold.

The sixth action is to determine the role function of the test person. For this, it is necessary to determine the maximum of the values of particular indicators.

The seventh action is the calculation of a generalized indicator of innovative intelligence by the formula (3), for which it is necessary to perform:

; $${К}_T^{Н}={К}_T/K_T^{\min }$$

; $${К}_{П}^{Н}={К}_{П}/K_{П}^{\min }$$

;a) division: $${\mathrm{TO}}_{\mathrm{BUT}}^N={\mathrm{TO}}_{\mathrm{BUT}}/K_A^{\min }$$

; $${\mathrm{TO}}_T^N={\mathrm{TO}}_T/K_T^{\min }$$

; $${\mathrm{TO}}_P^N={\mathrm{TO}}_P/K_P^{\min }$$

;

; $${({К}_T^{Н})}^2$$

; $${({К}_{П}^{Н})}^2$$

;b) squaring: $${({\mathrm{TO}}_{\mathrm{BUT}}^N)}^2$$

; $${({\mathrm{TO}}_T^N)}^2$$

; $${({\mathrm{TO}}_P^N)}^2$$

;

;c) summation: $${({\mathrm{TO}}_{\mathrm{BUT}}^N)}^2+{({\mathrm{TO}}_T^N)}^2+{({\mathrm{TO}}_P^N)}^2$$

;

;d) calculation of the square root: $$\sqrt{{({\mathrm{TO}}_{\mathrm{BUT}}^N)}^2+{({\mathrm{TO}}_T^N)}^2+{({\mathrm{TO}}_P^N)}^2}$$

;

.d) division: (1/3) $$\sqrt{{({\mathrm{TO}}_{\mathrm{BUT}}^N)}^2+{({\mathrm{TO}}_T^N)}^2+{({\mathrm{TO}}_P^N)}^2}$$

.

Depending on the goals, content and purpose of the test, a qualitative assessment of the levels of indicators: “low”, “medium”, “high” can be different. In the particular case of the application of tests of achievements, creativity or special abilities, representing psycho-diagnostic methods for measuring relevant skills, knowledge, skills; creative abilities or individual aspects of intelligence and psychomotor functions, depending on the numerical values of the psychodiagnostic indicators K, the corresponding personality characteristics are assessed as: “low” at K≤0.3; “Average” at 0.3 <K≤0.6; "High" at K> 0.6.

The fifth action of the device is to compare the values of particular indicators with predefined values and display the evaluation results.

The claimed device operates as follows.

The order of operation of the device is represented by a block diagram of the algorithm (Fig. 15).

Preliminarily, in the synchronization unit BS 8 through "Input of the initial data 1" the data necessary to coordinate the operation of the elements of the device are recorded. In the control unit BU 1 through the "Input of initial data 2" write the data of the test tasks and the data necessary to calculate the private and generalized indicators of intelligence. In this case, the contents of test tasks are recorded in the memory register 1.5 of control unit 1 (see Fig. 1, Fig. 2) through its information output 1.5.4 and address input 1.5.1 when the logical unit potential is applied to the "Record" 1.5 control input .3. Data is written to the memory registers of the firmware modules 1.1-1.4 BU 1 through the corresponding information outputs / inputs of the memory registers and the inputs of the address counters.

The device is prepared for work by pressing the button of the sensor "Installation 0" 2.3 OBD 2, while all the counters and accumulative adders of the device are set to their original (zero) state. On the graphical liquid crystal indicator 7.7 BI 7 displays the greeting information from the starting address of the memory register 1.5 BU. The device enters the "Waiting for test selection" mode.

The choice of the first or the next test is carried out by single-clicking on the button of the “Test selection” sensor 2.2 OBD 2, the status of the test number counter 2.5 is changed and the binary code of the test number is fed to output 2.4 of the DB 2. At the same time, the response number counter 2.4 is reset to zero 2.4 DB 2, the binary code of the test number is fed to the second input 1.1.1.3 of the comparator 1.1.1 of the first 1.1 of the control unit 1. In this case, from the starting address of the memory register 1.1.2 to the first 1.1.1.1, the input of the comparator 1.1.1 of the first module of the control unit 1 is supplied code number of the first test task. If the binary codes at the inputs of the comparator 1.1.1 match, from its output 1.1.1.2, through the delay element 1.1.4, the potential of the logical unit arrives at the input 1.1.3.1 of the address counter 1.1.3. The address counter 1.1.3 changes its state, and from its output 1.1.3.2, the binary code of the data address arrives at the input 1.1.2.6 of the memory register 1.1.2. From the corresponding memory cell of the memory register 1.1.2 from its fifth output 1.1.2.5, the binary code of the current job address is supplied through the output 1.1.10 of module 1.1 to the address input 1.5.1 of the memory register 1.5 BU 1, and from the first output 1.1.2.1 of the memory register 1.1.2 the binary code of the number of the next test task is fed to the input 1.1.1.1 of the comparator 1.1.1. From the corresponding address of the memory register 1.5 through the output 1.9 BU 1, the data are fed to the input 7.9 BI 7, as a result of which the contents of the next test task and the answers to it are displayed on the graphic liquid crystal display 7.7.

From the memory register 1.1.2 of the first module 1.1, through its output 1.1.5 and output 1.4 BU 1, the binary code of the number of the correct answer option is supplied to the third input 3.1.3 of the comparator 3.1 BKO 3, and binary is fed to the input 3.2.4 of the multiplier 3.2 BKO 3 code of the weight coefficient of the test task. Thus, the device enters the “Waiting for a response selection” mode.

The number of one of the answer options is selected by pressing the button of the “Answer Selection” sensor 2.1 DB 2. The state of the reverse counter of the answer number 2.4 is changed. The binary code of the selected answer number from the output of the counter of the answer number 2.4 is fed to the input 2.7.1 of the memory register 2.7 DB 2. When the “Record” button 2.6 is pressed, the binary code of the response number is written to the memory register 2.7 and through output 2.2 of the DB 2, input 3.1 3 is fed to the first input 3.1.1 of the comparator 3.1 BKO 3. If the selected answer is correct, the codes at the inputs of the comparator 3.1 are the same and its output 3.1.2 shows the potential of the logical unit, which is fed to the input 3.2.1 of the multiplier 3.2 BKO 3. If the selected answer is incorrect, then from exit 3.1.1 omparatora 3.1 comes the potential of a logic zero at the input of the multiplier 3.2.1 3.2.

Scoring for the correct answer is carried out by applying to the second synchronizing input 3.2.2 of the multiplier 3.2 BKO 3 clock pulses, which are generated by the synchronization unit. The enabling signal for applying clock pulses to the multiplier 3.2 is the potential of the logical unit, which is received when the “Record” sensor button is pressed 2.6. DB 2 through the output 2.5 of the DB, to the input 1.3 of the control unit 1, the second input 1.7.2 of the element "OR" 1.7 to the output 1.11 BU 1 and then to the input 8.11 BS 8.

Thus, the number of points corresponding to the weight coefficient of the assignment is accrued for the correct answer, and zero points are awarded for the incorrect answer. The binary code corresponding to the number of points awarded comes from the output 3.2.3 of the multiplier 3.2 through the output 3.3 of BKO 3, input 4.1 of the BPPB 4 to the input 4.1.1 of the first accumulative adder 4.1 of the BPPB, which performs the summation of the incoming binary code with its source binary code.

BS 8 operates on the principle of a firmware [4, 5, 6], and the number of clock pulses supplied is determined by data previously recorded in memory register 8.7. The state of the address counter 8.6 determines the output address of the decoder 8.3, from which clock pulses are sent to the corresponding blocks of the device, as well as the address of the memory register cell 8.7, in which the binary code of the corresponding number of clock pulses supplied to these blocks is recorded. From the starting or next address of the memory register 8.7, a binary code of the number of ticks for the next stage of operation of the device is supplied to the first information input 8.5.1 of the comparator. From the output 1.11 BU 1, the potential of the logical unit comes through the eleventh 8.11 input of BS 8, the “OR” element 8.9 to the input “Start” 8.2.4 of the trigger key 8.2, which opens. With GTI 8.1, clock pulses are fed through a trigger key to the input 8.3.1 of the decoder 8.3 and the input 8.4.2 of the clock counter 8.4. If the codes match at the inputs of comparator 8.5, output 8.5.2 gives a pulse to the input “Stop” 8.2.2 of the trigger key, which closes through output 8.10 BS 8 to input 1.12 of control unit 1. Through a delay element 8.8, the pulse from comparator 8.5 arrives at the address counter 8.6, it increases its value by one and BS 8 is alerted to the next stage of operation of the device. The duration of the control pulse at the output 8.5.2 of the comparator 8.5 is determined by the delay interval of the delay element 8.8. Two series are fed sequentially to BPPB 4, BVChP 5, and three series of clock pulses from BS 8 to BVOP 6, for which the outputs of 8.3.4, 8.3.6, 8.3.8, and 8.3.9 of the decoder are connected through the "OR" element 8.9 to the input "Start" 8.2.4 trigger key 8.2.

The described operation steps of the device are repeated until the comparator 1.2.1 of module 1.2 BU 1 fixes the equality of codes “Number of tasks in the test” at output 1.2.2.1 of memory register 1.2.2 and the output of the address counter 1.1.3 of module 1.1 BU 1. In this case, the device switches to the "Preliminary scoring" mode.

Preliminary scoring includes summing on the first accumulative adder 4.1 BPPB 4 the total number of points for all completed test tasks of the first (or the next test), calculating on the divider 4.2 the average number of points accrued per test, calculating the sum of the squares of the average points for the battery of tests using the multiplier 4.3 and the second accumulative adder 4.4. A binary code corresponding to the value of the number of test tasks in the test is supplied to the second information input 4.2.4 of divider 4.2 from the memory register 1.2.2 of module 1.2 BU 1. On the multiplier 4.3, squaring the average number of points per test is performed. From the output of the multiplier, the code corresponding to the square of the average number of points per test is fed to the second accumulative adder 4.4. The second accumulative adder 4.4 sequentially adds the binary codes arriving at its input, as a result of which a code is generated at its output corresponding to the sum of the squares of the average values of the number of points accrued for the passed tests.

The enable signal for alternately supplying clock pulses to the divider 4.2 and then to the multiplier 4.3 is the pulse coming from the output 1.2.1.2 of the comparator 1.2.1 through the output 1.2.7 of the module 1.2, the shift register 1.6, the element "OR" 1.7, the output 1.11 BU 1 input 8.11 BS 8, through the element "OR" 8.9 BS 8 to the trigger key 8.2. The duration of the control signal at the output 1.2.1.2 of the comparator 1.2.1 is determined by the interval of the delay element 1.2.4 of module 1.2.

Zeroing the first accumulative adder 4.1 to prepare it for the next test is carried out by a clock pulse coming through the input 4.3 of the BPPB 4, the first OR element 4.5 to the input 4.1.3 of the first accumulative adder 4.1.

The described operation steps of the device are repeated until the comparator 1.3.1 of module 1.3 of BU 1 fixes the equality of the codes “Number of tests in the test battery” at the output of address counter 1.2.3 of module 1.2 and at output 1.3-2.1 of memory register 1.3.2. In this case, the device switches to the mode “Calculation of a private indicator”.

The calculation of the private indicator includes the calculation of the average value of the number of points for the battery of tests on the first divider 5.2, the calculation of the normalized value of the private indicator on the second divider 5.3, the comparison of the normalized value with the preset minimum value of the private indicator on the comparator 5.1.

The potential of the logical unit at the output of the comparator 1.3.1 of module 1.3 of BU 1 is the control signal for the address counter 1.3.3, according to which data for calculating the private indicator is supplied from the corresponding address of the memory register 1.3.2. In this case, the binary code corresponding to the number of tests in the test battery and the code corresponding to the normalized value of the private indicator, as well as the code corresponding to the minimum acceptable normalized value of the private indicator from the outputs 1.3.2.3-1.3.2.5 of the memory register 1.3.2 of module 1.3 are fed through the output 1.6 control unit 1 through the input 5.6 of the inverter 5 to dividers 5.2, 5.3 and the comparator 5.1 of the inverter 5.

The enable signal for sequentially supplying a series of clock pulses to the first 5.2 and second 5.3 dividers is the pulse coming from the output 1.3.1.2 of the comparator 1.3.1 of module 1.3 of the control unit 1, through its output 1.3.8, shift register 1.6, element "OR" 1.7, output 1.11 BU 1, input 8.11 BS 8. Delay element 1.3.4 of module 1.3 of BU 1 determines the duration of the control pulse at output 1.3.1.2 of comparator 1.3.1. At the end of two consecutive series of clock pulses coming from BS 8 to the I / O 5, a binary code is generated at the output of the 5.4 I / O that corresponds to the value of the private indicator.

The display of the private indicator score is carried out according to the signal from the output 5.1.2 of the comparator 5.1 BVChP 5, which is formed at a low value of the private indicator relative to a given minimum normalized level. In this case, through the input 7.1 BI 7, the potential of the logical unit enters the input 7.1.1 of the address counter 7.1, which changes its state and supplies a binary code corresponding to the serial number of the calculated private indicator to the input of the decoder 7.3. From the outputs 7.3.2-7.3.4 of the decoder 7.3, the potential of the logical unit is supplied to the triggers 7.13-7.15 to turn on one of the indicators 7.3, 7.6, 7.7, and through the trigger 7.16 the “Not ready” indicator 7.2 is turned on, if the low voltage compared with the set threshold values, the level of 2 or 3 private indicators.

Zeroing the second accumulative adder 4.4 BPPB 4 to prepare it for the next battery of tests is carried out by a clock pulse supplied through input 4.4 of the BPPB 4, the second element "OR" 4.6 to the input 4.4.3 of the second accumulative adder 4.4 BPPB 4.

The described operation steps of the device are repeated until the comparator 1.4.1 of module 1.4 of control unit 1 fixes the equality of codes “Number of test batteries” at the output of address counter 1.3.3 of module 1.3 and at output 1.4.2.1 of memory register 1.4.2 of module 1.4 control unit one.

The results of comparing the values of particular indicators with threshold values from the comparator 5.1 BVCHP 5 are fed sequentially to the memory register 9.1 of the BVCHK 9. The results of logical multiplication on the element “AND-NOT” 9.3 through the output 9.2 of the BVChK 9 are transmitted through the output 9.2 of the BVChK 9 to the “Universal” indicator 7.20 BI 7. The result of the selection on the majority element 9.2 goes to the Not Ready indicator 7.11 BI 7.

The values of the private indicators from the HPI 5 are fed sequentially to the register 10.1 of BORF 10. By the signal “Reading”, received from the BU 1, the values of the private indicators from the register 10.1 are sent to the first 10.2, second 10.3 and third 10.4 comparators. The comparison results from comparators 10.2, 10.3, 10.4 are sent through the decoder 7.16 to the corresponding indicators “Analyzer” 7.17, “Generator” 7.18, “Realizer” 7.19 BI 7. By the largest of the values of particular indicators, the predominant role of the subject in the creative team is signaled. Next, the device goes into the mode of "Calculating the generalized indicator."

The calculation of the generalized indicator in BVOP 6 includes the calculation of the sum of the squares of the values of the private indicators using the multiplier 6.1 and the accumulative adder 6.2, the calculation of the rms value of the private indicators using the square root calculator 6.3 and the divisor 6.4.

The potential of the logical unit at the output 1.4.1.2 of the fourth comparator 1.4.1 of the module 1.4 BU 1 is the control signal for the address counter 1.4.3, according to which from the memory register 1.4.2 of the module 1.4 through its output 1.4.6, output 1.10 BU 1, through input 6.7 BVOP 6 is supplied to the fourth information input 6.4.4 of the divider 6.4 BVOP 6 binary code "Number of test batteries".

The enabling signal for supplying consecutive series of clock pulses to the multiplier 6.1, the square root calculator 6.3, and the BVOP 6 divider 6 is the pulse that is generated at the output 1.4.1.2 of the fourth comparator 1.4.1 of the module 1.4 and comes through its output 1.4.7, shift register 1.6 , the element “OR” 1.7 BU 1 to the output 1.11 BU 1, through the input 8.11 BS 8 and the element “OR” 8.9 to the input “Start” 8.2.4 trigger key 8.2.

The enabling signals at BS 8 for the supply of clock pulses come from the second, third and fourth modules of the control unit 1 with a delay corresponding to the parameters of the delay elements 1.2.4-1.4.4. In this case, the timely supply of the next enable signal from the BU 1 modules to BS 8 is provided by the shift register 1.6 BU 1, which performs a delay of the enable signals until the completion of the next stage of the device operation. The synchronizing signal, ensuring the coordinated operation of BU 1 and BS 8, is the pulse coming from the output 8.5.2 of the comparator 8.5 BS 8 through its tenth output 8.10, the twelfth input 1.12 BU 1 to the fifth clock input 1.6.5 of shift register 1.6.

The display of the calculation result of the generalized indicator is carried out on the segment liquid crystal indicator 7.7, to which, through the F-bit output of the decoder 7.2, the code "Value of the generalized indicator" is supplied from the output 6.4.3 of the divider 6.4 BVOP 6.

Thus, the introduction of new nodes and constructive relationships makes it possible to ensure the efficiency of evaluations, simplify the scaling of the device depending on the number of subjects, increase the reliability of the assessment due to the possibility of using heterogeneous tests and a two-level assessment using private and generalized indicators, and provide a simple modification of the structure and content of tests by changing source data in the device’s firmware, perform an express analysis to select candidates for the creative team and according to established criteria, determine for each subject his functional role in the creative team.

Information sources

1. Naumkina L.G. Digital circuitry. Lecture notes on the discipline "Circuitry". - M.: Publishing House "Mountain Book", Publishing House of the Moscow Mining University, 2008. - 308 p.

2. Podyakov EA, Orlik VV Pulse and Digital Devices: A Training Manual. - Novosibirsk: Publishing House of NSTU, 2005 .-- 116 p.

3. Description of the invention to the USSR author's certificate No. 957209 of 09/07/89 "Device for extracting the square root" of the authors A.N. Florensov, V.I. Potapov, M.Yu. Plotnikov (Omsk Polytechnic Institute).

4. Samofalov KG, Romankevich A.M., and others. Applied theory of digital automata. - Kiev. Vishka School, 1987.

5. Soloviev G.N. Arithmetic computer devices. - M .: "Energy". 1978.

6. Savelyev A.Ya. Applied Theory of Digital Automata - M.: Higher School. 1987.

7. Zibchuk V.I., Sigorsky V.P., Shkuro A.N. Handbook of digital circuitry.

8. http://www.elektrotehno.ru/cfsxem_umndel.html.

9. A method for dividing integer binary numbers without a remainder, starting with the least significant bits. I.P. Osinin.

10. http://www.display.by/ru/graphicmodules.htm.

11. Kholodkova L.A. Innovative culture of subjects of military vocational education: theory and practice. Monograph. - SPb .: VUS, 2004 .-- 236 p.

Claims (6)

1. A device for determining the role function of a member of a creative team, containing a sensor unit, D-bit, where D≥2, the information output of which is connected to the D-bit information input of the response coding unit, a private indicator calculation unit, the fifth control output of which is connected to the first control the input of the display unit, and N-bit, where N≥2, the control input of the private indicator calculation unit is connected to the N-bit control output of the control unit, P-bit, where P≥2, the information input of which о is connected to the P-bit control output of the sensor unit, the fifth control output of which is connected to the third control input of the control unit, and the third control output of the sensor unit is connected to the first control input of the control unit and the eighth control input of the display unit, K-bit and M-bit where K≥2 and M≥2, the information outputs of the control unit are connected respectively to the K-bit information input of the response coding unit and to the M-bit information input of the display unit, different t we note that an additional synchronization block, a block of preliminary scoring, a general indicator calculation unit, a team member selection block and a role function evaluation unit are introduced, S-bit, where S≥2, the information input of which is connected to the S-bit information output of the private calculation unit indicators, the second and third control inputs of the role function evaluation unit are connected respectively to the seventh and eighth control outputs of the control unit, the fourth, fifth and sixth information outputs of the role evaluation unit functions are connected respectively to the fourth, fifth and sixth information inputs of the display unit, the first information input of the selection unit is connected to the fifth information output of the private indicator calculation unit, the fourth and fifth control inputs of the selection unit are connected respectively to the seventh and eighth control outputs of the control unit, the second and the third information outputs of the selection unit are connected respectively to the second and third information inputs of the display unit, S-bit information input bl As the generalized indicator calculation is connected to the S-bit information output of the private indicator calculation unit, the third, fourth and fifth synchronizing inputs of the generalized indicator calculation unit are connected to the seventh, eighth and ninth synchronizing outputs of the synchronization unit, the second control input and the seventh S-bit control input the general indicator calculation unit is connected respectively to the first control output of the sensor unit and to the S-bit tenth control output at the control unit, the S-bit sixth information output of the general indicator calculation unit is connected to the S-bit seventh information input of the display unit, the S-bit information input and the output of the ball preliminary calculation unit are connected respectively to the S-bit information output of the response coding unit and the input of the unit calculation of particular indicators, the S-bit seventh control input and the sixth control input of the preliminary calculation of points are connected respectively to the S-bit fifth to the output of the control unit and to the third output of the sensor unit, and the fourth synchronizing input of the preliminary calculation unit of points and the third synchronizing input of the calculating unit of private indicators are connected to the sixth output of the synchronization unit, the second and third synchronizing inputs of the preliminary calculation of points are connected to the third and fourth synchronizing the outputs of the synchronization unit, the second synchronizing output of which is connected to the synchronizing input of the encoding unit ov, and the fifth synchronizing output of the synchronization unit is connected to the second synchronizing input of the private indicator calculation unit, the eleventh control output and the twelfth control input of the control unit are connected respectively to the eleventh control input and the tenth output of the synchronization unit, and the first control input of the synchronization unit is connected to the first control output sensor unit, and the synchronization unit and the control unit are equipped respectively F-bit, where F≥2 and W-bit, where W≥2, inputs source data synchronization and control. 2. The device according to claim 1, characterized in that the block of preliminary scores consists of cascading the first accumulative adder, divider, multiplier and second accumulative adder, the first and second OR elements, the outputs of which are connected respectively according to the S-bit information signal to the zeroing inputs of the first and second cumulative adders, and the S-bit information input of the first and the output of the second cumulative adders are respectively S-bit information input and output ohm of the intermediate scoring block, the synchronizing input of the divider is the second synchronizing input of the block of intermediate scoring, the input of the first "OR" element and the input of the multiplier are combined and are the third synchronizing input of the block of intermediate scoring, the first input of the second element "OR" is the fourth control input of the block intermediate scoring, and the second S-bit control input of the divider and the combined second inputs of the first and second elements "OR" are respectively S-p gas tube seventh and sixth control inputs of the block of preliminary scoring. 3. The device according to claim 1, characterized in that the generalized indicator calculation unit consists of a cascade multiplier, an accumulative adder, a square root calculator and a divider cascaded by the S-bit information signal, the first S-bit information input of the multiplier and the third S-bit the information output of the divider is respectively the S-bit information input and the output of the general indicator calculation unit, the S-bit control input of the divider is the seventh S-bit control input b calculating a generalized indicator of an eye, the synchronizing input of the multiplier, the input of the square root calculator and the divider are input, respectively third, fourth and fifth synchronizing inputs generalized index calculation unit, and a control input cumulative adder is a second control input calculation unit generalized indicator. 4. The device according to claim 1, characterized in that the synchronization unit consists of a clock generator, a trigger key, a decoder, a clock counter, a comparator, an address counter, a memory register, a delay element and an “OR” element, the information output of the comparator is connected to the “Stop” input of the trigger key and through the delay element to the information input of the address counter, D-bit, where D≥2, the third and first information inputs of the comparator are connected respectively to the D-bit information output of the clock and pulses and the output of the memory register, R-bit, where R≥2, the control output of the address counter is connected to the R-bit control inputs of the memory register and the decoder, the information output of the trigger key is connected to the information input of the clock counter and the information input of the decoder, the output of the clock generator pulses connected to the first information input of the trigger key, the control input "Start" of the trigger key is connected to the output of the element "OR", the sixth input of which is the eleventh control input m of the synchronization unit, and the information outputs from the third to tenth decoder are respectively the synchronizing outputs from the 2nd to the 9th synchronization block, the first, sixth, eighth and ninth information outputs of the decoder are connected respectively to the second, third, fourth and fifth inputs of the element "OR", the information output of the comparator is the tenth control output of the synchronization block, the inputs "Zero" of the clock counter and the address counter are combined and are the first control input ohm of the synchronization block, and the D-bit information output and the R-bit address input of the memory register form the F-bit input of the initial synchronization data, where F = D + R. 5. The device according to claim 1, characterized in that the role function evaluation unit consists of a memory register, first, second and third binary number comparators, a second information register of the memory register is connected to the first information input of the first comparator and the third information input of the third comparator, the third the information output of the memory register is connected to the third information input of the first comparator and to the first information input of the second comparator, the fourth information output of the memory register is connected to the third information input of the second comparator and the first information input of the third comparator, the first S-bit information input of the memory register being the first information input of the role function evaluation unit, the fifth and sixth control inputs of the memory register are the second and third control inputs of the role function evaluation unit, information outputs the first, second and third comparators are the fourth, fifth and sixth information outputs of the role function evaluation unit, respectively. 6. The device according to claim 1, characterized in that the unit for selecting members of the collective consists of a memory register, a majority element and an “And” element, the second, third and fourth information outputs of the memory register are connected respectively to the first, second and third information inputs of the majority element and element "And", and the first information input of the memory register is the first information input of the selection block, the fifth and sixth control inputs of the memory register are the fourth and fifth control inputs of the block ora, and the fourth information outputs of the “AND” element and the majority element are the second and third information outputs of the selection block, respectively.

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