RU2548478C1 - Device for rating evaluation of level of readiness to innovative activity - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: device consists of a response encoding unit, a personal performance computing unit, a display unit, a synchronisation unit, a preliminary scoring unit, an overall performance computing unit, a team member selection unit, a role function estimation unit and a rating estimate unit.

EFFECT: faster analysis, device enables to select candidates based on given criteria, determine for each participant the preferred nature of the solved tasks of the innovative process and rank candidates according to the overall intellectual performance with display of the current and overall rating of each test subject in a group of candidates - members of a creative team.

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Description

The invention relates to computer technology, in particular, to devices for psychological modeling of actions of persons involved in practically important situations, with a subsequent assessment of these actions, to the field of professional suitability tests and related training, to the field of psychometric measurements of intelligence carried out in psychology. The device can be used to conduct individual rapid tests of professional suitability in the absence of resources for a more complete and accurate assessment of the level of readiness of a person for innovative activities in practically important situations, as well as in the formation of teams for the effective solution of highly specialized knowledge-intensive creative tasks.

A well-known automated system for training and knowledge control (Patent RU No. 2110095 C1 G09B 7/00), made on the basis of a personal computer, consisting of a control panel, a device for inputting responses and reactions of a student, information input units, a decoder of control signals, a data buffer, a device control and synchronization, address counter, memory block, digital-to-analog converter and analog multiplexer.

The known device allows the use of information stimulation at the subsensory level of perception in the process of accelerated individual learning and knowledge control.

The disadvantage of the analogue is the bulkiness and relatively high cost of one workplace due to the use of a personal computer as the base.

The “Testing” testing system (RU 2186423 C2, G09B 7/00) is also known. It is designed to test the volume and quality of knowledge in distance learning, in the case of automated correspondence determination of professional suitability, in organizational and managerial, vocational guidance and individual and personal counseling, as well as certification control of personnel of enterprises. The system is based on computer network information technologies and includes blocks of preparatory modules, testing modules, telecommunication modules and analysis and processing modules.

The known device allows you to implement remote simultaneous testing of many subjects located geographically in different places and provides the secrecy of test tasks to increase the reliability of the results.

The disadvantage of this analogue is the relative complexity of the system and the high cost of one workplace, the need to develop special software for calculating test scores in the telecommunication process.

The closest analogue (prototype) to the claimed device in its technical essence is a knowledge control device (RU 2110096 C1, G09B 7/07), which includes several student test panels, angle-to-code converters, on-off sensors, an instrument control panel, an electric grading scheme, scoreboard and power source.

The prototype scheme allows you to use it for rapid testing of subjects, while significantly reducing the cost of one workplace.

However, the prototype device has disadvantages:

1. The dependence of the design of the device on the number and complexity of the tests. In this regard, to conduct a comprehensive assessment of the test subject with a large number of heterogeneous test tasks, proportional complexity of the device design (scaling complexity) is required;

2. The need for centralized instrument control to set test keys and control the testing process;

The aim of the invention is to develop a testing device that provides a quick rating assessment of the level of innovative intelligence in groups of subjects, simplifying scaling in accordance with the required number of subjects through the use of stand-alone test panels for subgroups of subjects, decentralization of control of the testing process through the use of microprogram technology, the possibility of using heterogeneous test items with a lot of questions of various difficult and five possible answers by the use of random access memory.

The claimed device extends the arsenal of funds for this purpose. This goal is achieved by the fact that in a known testing device containing a sensor unit, D-bit, where D≥2 information output of which is connected to the D-bit information input of the response coding unit (BCO), the unit for calculating private indicators (BVCHP), the sixth control the output of which is connected to the first control input of the display unit (BI), and N-bit, where N≥2 the control input of the I / O is connected to the N-bit control output of the control unit 1, P-bit, where P≥2, the information input of which is connected to P-time row control output of the sensor unit (DB), the sixth and fourth control outputs of which are connected respectively to the third and first control inputs of the control unit, K-bit and M-bit, where K≥2 and M≥2 information outputs of the control unit are connected respectively to K - to the bit information input of the response coding unit (BCO) and to the M-bit information input of the BI, a synchronization block, a block of preliminary scoring (BPPB), a unit for calculating the generalized indicator (BVOP), a selection block are additionally introduced team members (BVChK), the role function evaluation unit (BORF) and the rating evaluation unit (BRO). The second BRO control input is connected to the second DB control output. The fourth, fifth and sixth synchronizing inputs of the BRO are connected respectively to the tenth, eleventh and twelfth synchronizing outputs of the synchronization block. The eighth, H-bit ninth and tenth control inputs of the BRO are connected respectively to the eleventh, H-bit twelfth and thirteenth control outputs of the control unit. O-bit, where O≥2, the seventh information output of the BRO is connected to the O-bit sixth information input of the BI. S-bit, where S≥2, the information input of the BORF is connected to the S-bit information output of the UHF. The fourth three-digit information output of the BORF is connected to the fourth information input of the BI. The first information input of the BVChK is connected to the sixth information output of the BVChP. The third and fourth information outputs of the BVChK are connected respectively to the second and third information inputs of the BI. The S-bit information input of the BVOP is connected to the S-bit information output of the BVPP. The third, fourth and fifth synchronizing inputs of the BVOP are connected respectively to the seventh, eighth and ninth synchronizing outputs of the synchronization unit. The S-bit seventh control input of the general indicator calculation unit is connected to the S-bit control output of the control unit. The S-bit information output of the BVOP is connected to the S-bit information inputs of the BI and BRO. The S-bit first information input and the fifth information output of the BPPB are connected respectively to the S-bit information output of the BCO and the input of the BCI. The S-bit sixth input of the BPPB is connected to the S-bit fifth control output of the control unit. The second and third synchronizing inputs of the BPPB are connected respectively to the third and fourth synchronizing outputs of the BS. The second synchronizing output of the BS is connected to the synchronizing input of the BKO. The fifth synchronizing output of the BS is connected to the second synchronizing input of the I / O. The sixth BS output is connected to the fourth and third synchronizing inputs of the BPPB and BVChP, respectively, as well as to the second synchronizing input of the BVChK. The thirteenth BS output is connected to the second BVOP synchronizing input and the seventh BI synchronizing input. The seventh control output of the control unit is connected to the fifth and second control inputs, respectively, BVChK and BORF. The P-bit eighth control output of the control unit is connected to the P-bit third control input of the BORF. The fourteenth control output and the fifteenth control input of the control unit are connected respectively to the fifteenth control input and the fourteenth output of the BS. The first control output of the database is connected to the first control inputs of the BS and BRO, as well as to the eighth control input of the BI. The synchronization unit and the control unit are respectively equipped with F-bit, where F≥2 and W-bit, where W≥2, buses of the original synchronization and control data, respectively.

BPPB consists of a first accumulating adder, a divider, a multiplier and a second accumulating adder, the first and second OR elements, included in cascade on an S-bit information signal. The S-bit information input of the first and the output of the second accumulating adders are respectively the S-bit information input and output of the BPPB. The synchronizing input of the divider is the second synchronizing input of the BPPB. The second inputs of the multiplier and the first element "OR" are combined and are the third synchronizing input BPPB. The third inputs of the first and second accumulating adders are connected to the outputs of the first and second OR elements, respectively. The second input of the second element "OR" is the fourth synchronizing input BPPB. The fourth S-bit control input of the divider and the combined third inputs of the first and second OR elements are, respectively, the S-bit seventh and sixth control inputs of the BPPB.

The generalized indicator calculation unit consists of a cascade multiplier, an accumulating adder, a square root calculator, and a divider that are connected in cascade according to the S-bit information signal. The first S-bit information input of the multiplier and the third S-bit information output of the divider are respectively S-bit information input and output of the BVOP. The fourth S-bit control input of the divider is the seventh S-bit control input of the BVOP. The synchronizing input of the multiplier, the input of the square root calculator, and the input of the divider are the third, fourth, and fifth synchronizing inputs of the BVOP, respectively. The control input of the accumulating adder is the second control input of the BVOP.

The synchronization unit consists of a clock generator, trigger key, demultiplexer, clock counter, comparator, address counter, memory register, delay element and the element "OR". The information output of the comparator is connected to the “Stop” input of the trigger key and through the delay element to the information input of the address counter. D-bit, where D≥2, the first and second information inputs of the comparator are connected respectively to the D-bit information output of the clock counter and the output of the memory register. R-bit, where R≥2, the control output of the address counter is connected to the R-bit control inputs of the memory register and demultiplexer. The information output of the trigger key is connected to the information input of the clock counter and the information input of the demultiplexer. The output of the clock generator is connected to the first information input of the trigger key. The control input “Start” of the trigger key is connected to the output of the “OR” element. The ninth input of the OR element is the fifteenth control input of the BS. Information outputs from the 3rd to the 14th demultiplexer are respectively the synchronizing outputs from the 2nd to the 13th BS. The fourth, sixth, eighth, ninth, eleventh, twelfth and thirteenth information outputs of the demultiplexer are connected respectively to the second, third, fourth, fifth, sixth, seventh and eighth inputs of the “OR” element. The information output of the comparator is the fourteenth control output of the BS. The inputs “Zero setting” of the clock counter and the address counter are combined and are the first control input of the BS. The D-bit information output and the R-bit address input, as well as the write-enabled second input of the memory register, form the F-bit input data bus of the synchronization block, where F = D + R + 1.

The team member selection block consists of a shift register, a majority element, an AND element, and three inverting elements. The third, fourth, and fifth information outputs of the shift register are connected through inverting elements to the first, second, and third information inputs of the majority element, respectively, and to the first, second, and third inputs of the AND element. The first information input of the shift register is the first information input of the BVCHK. The second and sixth control inputs of the shift register are, respectively, the second and wrinkled control inputs of the HVAC. The fourth information outputs of the “And” element and the majority element are respectively the third and fourth information outputs of the BVChK.

The role function evaluation unit consists of a memory register, first, second and third binary number comparators. The second information output of the memory register is connected to the first information input of the first comparator and the third information input of the third comparator. The third information output of the memory register is connected to the third information input of the first comparator and the first information input of the second comparator. The fourth information output of the memory register is connected to the third information input of the second comparator and the first information input of the third comparator. The first S-bit information input of the memory register is the first information input of the BORF. The fifth and P-bit sixth control inputs of the memory register are respectively the second and P-bit third control inputs of the BORF. The information outputs of the first, second and third comparators form the fourth three-digit information output of the BORF.

The block of ratings consists of an address counter, first and second memory registers, a comparator, a pulse counter, and V-5 linear recurrent registers. The second information inputs of linear recurrence registers are connected to the V-bit information output of the first memory register. The third information outputs of the linear recurrence registers are connected to the V-bit third information input of the comparator. The information output of the comparator is connected to the fourth control inputs of the linear recurrence registers and to the first information input of the pulse counter. G-bit, where G≥2, the information output of the pulse counter is connected to the G-bit information input of the second memory register. I-bit, where I≥2 information output of the address counter is connected to I-bit control inputs of the first and second memory registers. The first information input of the address counter is the second information input of the BRO. The third control input of the address counter is the eighth control input of the BRO. The second and S-bit fourth inputs of the first memory register are, respectively, the fourth synchronizing and third information inputs of the BRO. The I-bit output of the address counter and the G-bit output of the second memory register form the seventh O-bit, where O≥2, is the information output of the BRO. The third control input of the second memory register and the first information input of the address counter are combined and are the sixth control input of the BRO. The sixth synchronizing inputs of linear recursive registers are combined and are the fifth synchronizing input of the BRO. The fifth control inputs of the linear recurrence registers are combined and are the tenth clock input of the BRO. The control inputs from the seventh to the mth linear recurrence registers form H-bit, where H = (m-5) (V-5), the ninth control input of the BRO. The first control inputs of linear recurrence registers, the fifth control input of the first, the fourth control input of the second memory registers and the second control input of the pulse counter are combined and are the first control input of the BRO.

The letters indicated in the claims have the following meaning:

S - the number of bits of the code corresponding to the maximum number of points awarded for solving one test task.

P - the number of bits of the code corresponding to the maximum number of test tasks.

D - the number of bits of the code corresponding to the maximum number of questions in the test task.

M - the number of bits of the code, reflecting the maximum amount of data of one test task.

R is the number of bits of the address input of the BS decoder (in this case, R≥3).

V is the number of bits of the code corresponding to the maximum value of the generalized index of intelligence.

Q is the number of bits of the code corresponding to the number of estimated private intelligence indicators (in the case under consideration, Q≥3).

U is the number of bits corresponding to the capacity of the control inputs of the graphic liquid crystal indicator.

I is the number of bits of the binary code corresponding to the maximum number of subjects.

H is the number of bits of the binary decimal code corresponding to the maximum number of subjects.

G is the number of bits of the binary code corresponding to the maximum rating value.

F - bit width of the source data bus to the synchronization unit.

W is the bit width of the source data bus to the control unit.

Z is the number of bits of the binary code required to display on the segmented liquid crystal indicators the corresponding values of the generalized indicator, the number in the order of the subject, the rating of the subject.

Thanks to the new set of essential features, the implementation of the device provides a two-level assessment of the overall indicator of innovative intelligence, their simplicity of modifying the structure and contents of tests and the automation of all procedures, i.e. increasing the efficiency of research, in addition, the device allows for the selection of candidates according to specified criteria, to determine for each participant the preferred nature of the tasks of the innovation process and to rank the candidates by the value of the generalized intelligence indicator, displaying the current and generalized rating of each subject in the group of candidates participating in the creative team .

The invention is illustrated by drawings, which show:

in FIG. 1 is a block diagram of a device;

in FIG. 2 is a structural diagram of a control unit (CU);

in FIG. 3-7 are structural diagrams of the firmware of the control unit;

in FIG. 8 is a block diagram of a sensor unit (DB);

in FIG. 9 is a block diagram of a response coding unit (BCO);

in FIG. 10 is a block diagram of a block preliminary calculation of points (BPPB);

in FIG. 11 is a block diagram of a block for calculating private indicators (BVChP);

in FIG. 12 is a structural diagram of a general indicator calculator (BVOP);

in FIG. 13 is a structural diagram of a display unit (BI);

in FIG. 14 is a structural diagram of a synchronization unit (BS);

in FIG. 15 is a structural diagram of a trigger key BS;

in FIG. 16 is a block diagram of a team member selection unit (BVIK);

in FIG. 17 is a block diagram of a role function evaluation unit (BORF);

in FIG. 18 is a block diagram of a block of rating estimates (BRO);

in FIG. 19 is a structural diagram of a linear recurrence register;

in FIG. 20 is a block diagram of a device operation algorithm;

in FIG. 21 is a vector model of innovative intelligence;

in FIG. 22 is a discogram of particular indicators of innovative intelligence.

The claimed device shown in FIG. 1, consists of a control unit 1, a sensor unit 2, a response coding unit 3, a preliminary score calculation unit 4, a private indicator calculation unit 5, a generalized indicator calculation unit 6, an indication unit 7, a synchronization unit 8, a team member selection unit 9, a unit evaluations of the role function 10 and the block of ratings 11.

D-bit, where D≥2 information output 2.3 BD 2 is connected to the D-bit information input 3.1 BCO 3. The sixth control output of the I / O 5 is connected to the first control input of the BI, a N-bit, where N≥2 is the control input 5.5 I / O 5 connected to the N-bit control output 1.6 of the control unit 1. P-bit, where P≥2, the information input 1.2 of the control unit 1 is connected to the P-bit control output of the 2.5 database 2. The sixth 2.6 and the fourth 2.4 control outputs of the database 2 are connected respectively to the third 1.3 and the first 1.1 control inputs BU 1, K-bit 1.4 and M-bit 1.9, where K≥2 and M≥2 information the ion outputs of the control unit 1 are connected respectively to the K-bit information input 3.4 of the BCO 3 and to the M-bit information input of 7.9 BI 7. The second 11.2 control input of the BRO 11 is connected to the second 2.2 control output of the BD2, the fourth 11.4, fifth 11.5 and sixth 11.6 synchronization inputs BRO 11 are connected respectively to the tenth 8.10, eleventh 8.11 and twelfth 8.12 synchronizing outputs of BS 8. The eighth 11.8, H-bit ninth 11.9, where H≥2, and the tenth 11.10 control inputs of BRO 11 are connected respectively to the eleventh 1.11, H-bit twelfth 1.12 and tr the eleventh 1.13. control outputs BU 1, and O-bit, where O≥2, seventh 11.7 information output BRO 11 is connected to O-bit sixth 7.6 information input BI 7. S-bit, where S≥2, information input 10.1 BORF 10 is connected to S -digit information output 5.4 BVChP 5, 3-bit, fourth 10.4 information output BORF 10 is connected to the fourth 7.4 information input BI 7. The first 9.1 information input BVChK 9 is connected to the sixth 5.6 information output BVChP 5. The third 9.3 and fourth 9.4 information the outputs of the BVChK 9 are connected respectively to the second 7.2 and t For 7.3 information inputs of BI 7. S-bit, where S≥2, information input 6.1 of BVOP 6 is connected to S-bit information output 5.4 of BVChP 5. Third 6.3, fourth 6.4 and fifth 6.5 synchronization inputs of BVOP 6 are connected to seventh 8.7, respectively the eighth 8.8 and the ninth 8.9 synchronizing outputs of BS 8. The S-bit seventh 6.7 control input of the BVOP 6 is connected to the S-bit control output 1.10 of the BU 1. The S-bit information output 6.6 BVOP 6 is connected to the S-bit information input 7.5 of the BI 7 and the third 11.3 information input BRO 11, S-bit information input 4.1 and output 4.5 of the BPPB 4 are connected respectively to the S-bit information output 3.3 of the BCO 3 and the input 5.1 of the high-frequency converter 5. The S-bit sixth 4.6 input of the BPPB 4 is connected to the S-bit fifth 1.5 control output of the control unit 1. Second 4.2 and third 4.3 BPBB 4 synchronization inputs are connected respectively to the third 8.3 and fourth 8.4 BS 8 synchronization outputs. BS 8 second 8.2 output is connected to BSK 3.2 synchronization input 3. BS 8 fifth 8.5 output is connected to BCU 5 second 5.2 synchronization input 5. Sixth 8.6 block output BS 8 synchronization is connected to the fourth 4.4 and third 5.3 synchronizing inputs of BPPB 4 and BVChP 5, as well as to the second synchronizing input 9.2 of BVChK 9. The thirteenth 8.13 BS 8 output is connected to the second 6.2 synchronizing input of BVOP 6 and the seventh 7.7 synchronizing input of BI 7. The seventh 1.7 control output BU 1 is connected to the fifth 9.5 and second 10.2 control inputs respectively BVChK 9 and BORF 10. P-bit eighth 1.8 control output BU 1 is connected to the P-bit third 10.3 control input BORF 10. Fourteenth 1.14 control output and the fifteenth 1.15 control input of the control unit 1 is connected respectively to the fifteenth 8.15 control input and the fourteenth of 8.14 output of the BS 8. The first 2.1 control output of the database 2 is connected to the first 8.1 and 11.1 control inputs of the BS 8 and BRO 11, as well as to the eighth 7.8 control input of the BI 7. BS 8 and BU 1 are equipped with F-bit, where F≥2 and W-bit, where W≥2, respectively, the source data buses.

The control unit 1, the block diagram of which is shown in FIG. 2, is intended for storing data of test tasks, assigning weight coefficients of complexity of test tasks, as well as for issuing the necessary data to the main units of the device. The implementation of the block may be different, in particular, as shown in FIG. 2, based on the principle of constructing a microprogram automaton [4, 5, 6].

BU 1 provides timely data output to such elements of the device as multipliers, dividers, comparators, shift registers. It consists of five cascaded in P-bit, where P≥2, control signal of typical modules 1.1, 1.2, 1.3, 1.4, 1.5, which implement the principle of operation of the firmware, memory register 1.6 for storing test data, shift register 1.7 s parallel write and sequential read (PISO), the element "OR" 1.8 and delay element 1.9. The first input 1.8.1 of the “OR” element is connected to the first 1.7.1 information output of the shift register 1.7, and the second 1.8.2 input of the “OR” 1.8 element is the third 1.3 control input of the control unit 1. Information output 1.8.3 of the “OR” element 1.8 is the fourteenth 1.14 control output of the control unit 1. Sixth 1.7.6 the control input of the shift register 1.7 and the control inputs 1.1.9, 1.2.8, 1.3.10, 1.4.8, 1.5.9 modules respectively 1.1, 1.2, 1.3, 1.4, 1.5 combined and are the first 1.1 control input BU 1. The second 1.7.2, the third 1.7.3, the fourth 1.7.4 and the fifth 1.7.5 the information inputs of the shift register 1.7 is connected 1.2.7 respectively to the seventh control output of the second module 1.2, 1.3.9 ninth control output of the third module 1.3, 1.4.7 administrator seventh fourth module output 1.4 1.5.8 and eighth control output of the fifth module 1.5. The seventh control input 1.7.7 of shift register 1.7 is the fifteenth 1.15 control input of BU 1. The eighth 1.1.8 and P-bit tenth 1.1.10 control outputs of the first module 1.1 are connected respectively through the delay element 1.9 to the second 1.6.2 and the first 1.6.1 control inputs of the memory register 1.6. The P-bit control input 1.1.1 of the first module 1.1 is the second 1.2 control input of the control unit 1. Information outputs 1.1.4, 1.2.5, 1.3.5, 1.3.6, 1.3.7, 1.4.5, 1.5.5, 1.5 .6, 1.5.7 modules 1.1, 1.2, 1.3, 1.4, 1.5 are respectively K-bit fourth 1.4, S-bit fifth 1.5, S-bit sixth 1.6, seventh 1.7, P-bit eighth 1.8, S-bit tenth 1.10 , eleventh 1.11, H-bit twelfth 1.12 and thirteenth 1.13 control outputs of the control unit 1. M-bit, where M≥2, the fourth 1.6.4 memory register output 1.6 is the ninth 1.9 control output of the control unit 1.

Each exemplary module whose circuits are shown in FIG. 3-7, consists of a comparator 1.1.1-1.4.1, a memory register 1.1.2-1.4.2, an address counter 1.1.3-1.4.3 and a delay element 1.1.4-1.4.4. A typical module has the following structure, which can be considered by the example of the first module (see Fig. 3). The address input 1.1.2.6 of the memory register 1.1.2 is connected to the information output 1.1.3.2 of the address counter 1.1.3, and the first information output 1.1.2.1 of the memory register 1.1.2 is connected to the first information input 1.1.1.1 of the comparator 1.1.1. The output of the comparator 1.1.1.2 is connected through the delay element 1.1.4 to the information input 1.1.3.1 of the address counter.

The first module 1.1 (Fig. 3) provides the operation of the CCU 2. The second information input 1.1.1.3 of the comparator 1.1.1 is the first control input 1.1.1 of the module 1.1. The third control input 1.1.3.3 of the address counter 1.1.3 is the ninth control input 1.1.9 of module 1.1. The information output 1.1.1.2 of the comparator 1.1.1 is the eighth 1.1.8 control output of the module 1.1. D-bit third 1.1.2.3 and S-bit fourth 1.1.2.4 information outputs of the memory register 1.1.2 form K-bit, where K = D + S, the fifth control output 1.1.5 of module 1.1. The P-bit second information output 1.1.3.2 of the address counter 1.1.3 and the fifth information output 1.1.2.5 of the memory register 1.1.2 are respectively the seventh 1.1.7 and tenth 1.1.10 control outputs of module 1.1. The first 1.1.3.1 information input of the address counter 1.1.3, the first 1.1.2.1, the third 1.1.2.3, the fourth 1.1.2.4, the fifth 1.1.2.5 information outputs and the second 1.1.2.2 control input “Record” of the memory register 1.1.2 are used for preliminary input of initial data into module 1.1.

The second module 1.2 (see Fig. 4) provides the BPPB 4. The third 1.2.1.3 information input of the comparator 1.2.1 is the first control input 1.2.1 of module 1.2. The third control input 1.2.3.3 counter address 1.2.3. is the eighth 1.2.8 control input of module 1.2. The output 1.2.1.2 of the comparator 1.2.1 is the seventh 1.2.7 control output of the module 1.2. The S-bit third 1.2.2.3 information output of the memory register 1.2.2 and the P-bit second 1.2.3.2 information output of the address counter 1.2.3 are the fifth 1.2.5 and sixth 1.2.6 control outputs of module 1.2, respectively. The first 1.2.3.1 information input of the address counter 1.2.3, the first 1.2.2.1 and the third 1.2.2.3 information outputs, as well as the second control input “Record” 1.2.2.2 of the memory register 1.2.2 are used for preliminary data input into module 1.2.

The third module 1.3 (see Fig. 5) provides the operation of the BCHP 5, BVChK 9 and BORF 10. The P-bit third information input 1.3.1.3 of the comparator 1.3.1 and the third control input 1.3.3.3 of the address counter 1.3.3 are respectively the first 1.3 .1 and tenth 1.3.10 the control inputs of module 1.3. The output 1.3.1.2 of the comparator 1.3.1 is the ninth 1.3.9 control output of the module 1.3. S-bit third 1.3.2.3, fourth 1.3.2.4 and fifth 1.3.2.5 information outputs of the memory register 1.3.2 form N-bit, where N + 3S, fifth 1.3.5 control output of module 1.3. The sixth 1.3.2.6 and the P-bit seventh 1.3.2.7 information outputs of the memory register 1.3.2 are the sixth and seventh control outputs of module 1.3, respectively. The P-bit second output 1.3.3.2 of the address counter 1.3.3 is the eighth 1.3.8 control output of module 1.3. The first information input 1.3.3.1 of the address counter 1.3.3, the first 1.3.2.1, the third 1.3.2.3, the fourth 1.3.2.4, the fifth 1.3.2.5, the sixth 1.3.2.6, the seventh 1.3.2.7 information outputs and the second 1.3.2.2 control input memory register 1.3.2 are used for preliminary input of source data into module 1.3.

The fourth module 1.4 (see Fig. 6) provides BVOP 6. The P-bit third information input 1.4.1.3 of the comparator 1.4.1 and the third control input 1.4.3.3 of the address counter 1.4.3 are the first 1.4.1 and the eighth 1.4. 8 control inputs of the module 1.4. The first 1.4.2.1 and S-bit third 1.4.2.3 information outputs of the memory register 1.4.2 are respectively the third 1.4.3 and fifth control outputs of module 1.4. The output 1.4.1.2 of the comparator 1.4.1 is the seventh 1.4.7 control output of the module 1.4 The P-bit output 1.4.3.2 of the address counter 1.4.3 is the sixth 1.4.6 control output of the module 1.4. The first information input 1.4.3.1 of the address counter 1.4.3, the first 1.4.2.1 and the third 1.4.2.3 information outputs, the second 1.4.2.2 control input of the memory register 1.4.2 are used for preliminary input of the initial data into the module 1.4.

The fifth module 1.5 (see Fig. 7) provides the operation of the BRO 11. The P-bit third information input 1.5.1.3 of the comparator 1.5.1 and the third control input 1.5.3.3 of the address counter 1.5.3 are the first 1.5.1 and ninth 1.5, respectively. 9 control inputs of the module 1.5. The third 1.5.2.3 H-bit fourth 1.5.2.4 and fifth 1.5.2.5 outputs of the memory register 1.5.2 are respectively the fifth 1.5.5, sixth 1.5.6 and seventh 1.5.7 control outputs of module 1.5. The output 1.5.1.2 of the comparator 1.5.1 is the eighth 1.5.8 control output of the module 1.5. The first information input 1.5.3.1 of the address counter 1.5.3, the first 1.5.2.1, the third 1.5.2.3, the fourth 1.5.2.4 and the fifth 1.5.2.5 information outputs, the second 1.5.2.2 control input of the memory register 1.5.2 are used for preliminary input of the source data to module 1.5.

The left shift register 1.7 is designed to ensure the coordinated operation of BU 1 and BS 8. Through its information inputs 1.7.2-1.7.5, signals corresponding to a logical unit are recorded and are read in turn from the second to fifth when clock pulses arrive at the seventh 1.7.7 input shift register.

DB 2, the circuit of which is presented in FIG. 8, is intended for encoding with binary code the number of the test person, the number of the test and the response number that are selected by the test subjects, as well as for resetting all device counters. OBD 2 can be implemented in various ways, for example, as shown in FIG. 7: using on-off sensors 2.1, 2.2, 2.3, 2.6, 2.8 counter of test number 2.5, reversible counter of response number 2.4 and memory register 2.7. The D-bit first information input 2.7.1 of the memory register 2.7 is connected to the D-bit information output 2.4.2 of the counter of the response number 2.4. The third control input 2.7.3 of the memory register 2.7 is connected to the output 2.6.2 of the sensor "Record" 2.6. The first information input 2.4.1 of the counter of the answer number 2.4 is connected to the output of the sensor "Choice of answer" 2.1, and the third zeroing input 2.4.3 of the counter of the answer number is connected to the output 2.2.2 of the sensor "Choice of test" 2.2. The first information input 2.5.1 of the counter of test number 2.5 is connected to the output 2.2.2 of the sensor "Select test" 2.2, and the third zeroing input 2.5.3 of the counter of test number 2.5 is connected to the output 2.3.2 of the sensor "Setting 0" 2.3. The potentials corresponding to logical zero and one are supplied to the inputs 2.1.2, 2.1.1 of the sensor “Choice of answer” 2.1, and the potentials corresponding to the logical unit are fed to the inputs of the sensors “Choice of test” 2.2, “Setting 0” 2.3 and “Record” 2.6 . The output 2.3.2 of the sensor "Setting 0" 2.3 is the first 2.1 and fourth 2.4 control outputs of the database 2. D-bit output 2.7.2 of the memory register 2.7 and P-bit output 2.5.2 of the counter of test number 2.5 are respectively the third 2.3 and fifth 2.5 information outputs of the database 2. The output 2.6.2 of the sensor "Record" 2.6 is the sixth 2.6 control output of the database 2. The output 2.8.2 of the sensor 2.8 is the second 2.2 control output of the database 2.

BKO 3 is designed to determine the number of points for the selected answer to the test task in accordance with pre-set task weights. BCO 3 can be implemented in various ways, in particular, as shown in FIG. 9.

BKO 3 consists of a comparator 3.1 and a multiplier 3.2. The first information input 3.2.1 of the multiplier 3.2 is connected to the output 3.1.2 of the comparator 3.1. The first 3.1.1 information input of the comparator 3.1 and the information output 3.2.3 of the multiplier 3.2 are respectively the D-bit information input 3.1 and the S-bit output 3.3 of the BKO 3, and the third input 3.1.3 of the comparator 3.1 and the fourth input 3.2.4 of the multiplier 3.2 form K-bit control input BKO 3, where K = S + D. The second clock input 3.2.2 of the multiplier is the second 3.2 clock input BKO 3.

BPPB 4 is designed to calculate the total and average number of points awarded according to the results of the test tasks and the preparation of the source data for calculating particular indicators of intelligence. BPS 4 can be implemented in various ways, in particular, as shown in FIG. 10.

BPPB 4 consists of the first accumulating adder 4.1, the divider 4.2, the multiplier 4.3, the second accumulating adder 4.4, the first 4.5 and the second 4.6 “OR” elements cascaded by the first accumulating adder 4.1 according to the S-bit information signal. The multiplier 4.3 performs the squaring of the number received in binary code on its first input 4.3.1.

The first input 4.1.1 of the first and second output 4.4.2 of the second accumulating adders are respectively information input 4.1 and output 4.5 of the BPPB 4. Synchronizing input 4.2.2, the divider, and the combined inputs 4.5.2 of the first “OR” element and 4.3.2 of the multiplier 4.2 they are the synchronizing inputs 4.2 and 4.3 of the BPPB 4. The S-bit fourth 4.2.4 control input of the divider 4.2 is the seventh 4.7 control input of the BPP 4. The zeroing inputs 4.1.3 and 4.4.3 of the accumulating adders 4.1 and 4.2 are combined and connected to the outputs respectively 4.5. 1 and 4.6.1 of the elements "OR". The third inputs 4.5.3 and 4.6.3 of the "OR" elements are combined and are the sixth 4.6 control input synchronizing input BPPB 4. The second input 4.6.2 of the element "OR" 4.6 is the fourth synchronizing input BPPB 4.

The initial installation of the accumulating adders 4.1 and 4.4 is carried out by applying a pulse to their control inputs 4.1.3 and 4.4.3 through the "OR" elements 4.5 and 4.6 and the sixth control input 4.6, and preparation of the BPPB 4 for the next stage of work is carried out by zeroing the accumulating adders 4.1. and 4.4 pulses coming through the second 4.2 and fourth 4.4 synchronizing inputs BPPB 4.

BVChP 5 is intended for calculating the values of private indicators of intelligence and forming according to the results of the calculation of the information signal on BI 7, as well as for preparing the source data for calculating the value of the generalized indicator. UHPF 5 can be implemented in various ways, in particular, as shown in FIG. eleven.

BVChP 5 consists of cascade connected on the S-bit information signal of the first 5.2 and second 5.3 dividers and 5.1 comparator.

The first input 5.2.1 of the first divider 5.2 and the output 5.3.3 of the second divider 5.3 are respectively the information input 5.1 and the output 5.4 of the I / O 5. The output 5.1.2 of the comparator 5.1 is the sixth 5.6 control output of the I / O 5. The synchronizing inputs 5.2.2 and 5.3.2 dividers 5.2 and 5.3 are respectively the second 5.2 and third 5.3 synchronizing inputs of the I / O 5, and the information inputs 5.2.4, 5.3.4 of the dividers 5.2 and 5.3 and the third information input 5.1.3 of the comparator 5.1 form the control N-bit input 5.4 of the I / O 5, where N = 3S.

BVOP 6 is designed to calculate the value of the generalized indicator of intelligence of the subject and the formation of the information signal in BI 7. BVOP 6 can be implemented in various ways, in particular, as shown in Fig. 12.

BVOP 6 consists of a multiplier 6.1, an accumulative adder 6.2, a square root calculator 6.3, and a divisor 6.4, connected in cascade according to the S-bit information signal. The S-bit input 6.1.1 of the multiplier 6.1 and the output 6.4.3 of the divider 6.4 are respectively the information input 6.1 and the information output 6.6 of the BVOP 6. The synchronizing inputs 6.1.2, 6.3.2, 6.4.2 of the multiplier 6.1, the square root calculator 6.3, and the divider 6.4 are the synchronizing inputs 6.3-6.5 BVOP 6. S-bit input 6.4.4 of the divider 6.4 and the resetting input 6.2.2 of the accumulative adder 6.2 are the control inputs 6.7 and 6.2 of the BVOP 6.

BI 7 is designed to present the subject with the contents of test tasks, as well as display the results of calculating particular and generalized indicators of intelligence, the serial number of the subject and the value of his rating in the group (subgroup). BI 7 can be implemented in various ways, in particular, as shown in FIG. 13.

BI 7 consists of an address counter 7.6, decoders 7.1, 7.2, 7.4, 7.5, 7.8, 7.9, demultiplexer 7.3, segment liquid crystal indicators 7.18-7.20, status indicators 7.21-7.28, delay triggers 7.10-7.17 and a graphic liquid crystal indicator 7.7. The graphic LCD 7.7 is controlled through its inputs 7.7.1 and 7.7.2, to which the outputs 7.5.2 and 7.4.2 of the fourth 7.5 and third 7.4 decoders are connected. Segmented LCD 7.18-7.20 is controlled through the first 7.1, fifth 7.8 and sixth 7.9 decoders. The status indicators 7.21-7.28 are controlled through the corresponding triggers 7.10-7.17 connected to the outputs of the descrambler 7.2 and demultiplexer 7.3. The Universal indicator 7.24 is controlled by trigger 7.13, the clock input of which is the second control input of BI 7. The Not Ready indicator 7.26 is controlled by trigger 7.17, the clock of which is the third control input of BI 7. Q-bit control input 7.3.2 of the demultiplexer 7.3 is connected to the output 7.6.2 of the address counter 7.6. The information input 7.6.1 of the address counter 7.1 is the seventh clock input 7.7 of BI 7, and the first 7.3.1 information input of the demultiplexer 7.3 is the first information input of BI 7. The 3-bit information input 7.2.1 of the second decoder 7.2 is the fourth 7.4 information input BI 7. S-bit information input 7.1.1 of the first decoder 7.1 is the fifth 7.5 information input of BI 7. M / 2-bit information inputs 7.4.1 and 7.5.1 of the third 7.4 and fourth 7.5 decoders form the ninth 7.9 M-bit information input BI 7. Zeroing Suitable 7.10-7.17 inputs of flip-flops are combined, and the control input of the eighth 7.8 BI 7. Information inputs 7.8.1 and 7.9.1, respectively, the fifth and the sixth 7.8 7.9 decoders form O-sixth bit information input BI 7.6 7.

BS 8 is designed to generate synchronizing signals and output them to other blocks in accordance with the algorithm of the device, it ensures the coordinated operation of such elements of the device as multipliers, dividers and a square root calculator. BS 8 may be implemented in various ways, in particular, as shown in FIG. fourteen.

BS 8 consists of a clock generator 8.1, a trigger key 8.2, a demultiplexer 8.3, a clock counter 8.4, a comparator 8.5, an address counter 8.6 and a memory register 8.7, a delay element 8.8, and an "OR" element 8.9. The information output 8.5.3 of comparator 8.5 is connected to the input “Stop” 8.2.2 of the trigger key 8.2.2 and through the delay element 8.8 to the information input 8.6.1 of the address counter 8.6. The D-bit first 8.5.1 and second 8.5.2 information inputs of the comparator 8.5 are connected respectively to the D-bit information output 8.4.1 of the clock counter 8.4 and the output 8.7.1 of the memory register 8.7. The R-bit control output 8.6.1 of the address counter 8.6 is connected to the R-bit control input 8.7.3 of memory register 8.7 and the input 8.3.2 of demultiplexer 8.3. The information output 8.2.3 of the trigger key 8.2 is connected to the information input 8.4.2 of the clock counter 8.4 and the information input 8.3.1 of the demultiplexer 8.3. The output 8.1.1 of the clock 8.1 is connected to the first information input 8.2.1 of the trigger key 8.2. The control input “Start” 8.2.4 of the trigger key 8.2 is connected to the output 8.9.1 of the “OR” element 8.9, the ninth input 8.9.9 of which is the fifteenth 8.15 control input of the synchronization unit 8, and the information outputs 8.3.3-8.3.14 of the demultiplexer 8.3 are the corresponding synchronizing outputs 8.2-8.13 of the synchronization unit 8. The fourth 8.3.4, sixth 8.3.6 and eighth 8.3.8, ninth 8.3.9, eleventh 8.3.11, twelfth 8.3.12 and thirteenth 8.3.13 information outputs of the demultiplexer 8.3 are connected to the inputs of the element "OR" 8.9. Information output 8.5.2 of comparator 8.5 is the fourteenth control output of the BS. The “Zero setting” inputs 8.4.3 of the clock counter 8.4 and 8.6.3 of the address counter 8.6 are combined and are the first 8.1 control input of the synchronization unit 8. D-bit information output 8.7.1 and R-bit address input 8.7.3. the memory register 8.7 form an F-bit bus synchronization block 8 for input data, where F = D + R.

The trigger key circuit 8.2 must pass pulses of equal duration. The trigger key 8.2 may be implemented in various ways, in particular, as shown in FIG. 15. It consists of the first 8.2.1.1 and the second 8.2.1.3 RS-flip-flops, the inversion element 8.2.1.2 and the “And” element 8.2.1.4. The output of the first trigger 8.2.1.1 is connected to the D-input of the second trigger 8.2.1.3. The output of the second trigger 8.2.1.3 is connected to the second input of the And element 8.2.1.4. The synchronizing input of the second trigger 8.2.1.3 is connected to the output of the inversion element 8.2.1.2. The inputs of the inversion element 8.2.1.2 and the element “AND” 8.2.1.4 are combined and form the first information input 8.2.1 of the trigger key 8.2. The inverse R-input of the first trigger 8.2.1.1 is the second 8.2.2 control input "Stop" trigger key 8.2. The trigger input of the first trigger 8.2.1.1 is the fourth 8.2.4 control input "Start" of the trigger key. The output of the “AND” element 8.2.1.4 is the third 8.2.3 information output of the trigger key 8.2. At the D-input, the inverse S-input of the first trigger 8.2.1.1 and the inverse inputs R and S of the second trigger 8.2.1.3, the potential of a logical unit is supplied.

BVChK 9 is intended for the selection of members of the creative team according to the normalized values of private indicators and the exclusion of those people who have two or more normalized private indicators have values below the threshold, as well as to identify people who can perform any role function in the creative team (“universal "). The UHFV 9 may be implemented in various ways, in particular, as shown in FIG. 16.

BVChK 9 consists of a shift register 9.1, a majority element 9.2 of the element "And" 9.3 and inverting elements 9.4-9.6, a third 9.1.3, a fourth 9.1.4 and a fifth 9.1.5 information outputs of the shift register are connected through the inverting elements 9.4-9.6 respectively to the information the inputs 9.2.1-9.2.3 of the majority element and to the first, second and third inputs 9.3.1-9.3.3 of the "And" element, the first 9.1.1 information input of the shift register being the first 9.1 information input of the unit for selecting members of the collective, the second 9.2 and sixth 9.6 the control inputs of the shift register are Xia 9.2 second and fifth control selection unit 9.5 staff member inputs and outputs fourth information element "AND" 9.3.4 and 9.2.4 majority element are respectively third and fourth data outputs 9,4 selecting unit 9 BVCHK team members.

BORF 10 is designed to determine a private indicator that has a maximum value compared to the values of other private indicators and determine the corresponding role function of a member of a creative team. BORF 10 can be implemented in various ways, in particular, as shown in FIG. 17.

BORF 10 consists of a memory register 10.1, the first 10.2, the second 10.3 and the third 10.4 binary number comparators, the second information output 10.1.1 of the memory register is connected to the first 10.2.1 information input of the first comparator 10.2 and the third 10.4.3 information input of the third 10.4 comparator, the third information output 10.1.3 of the memory register 10.1 is connected to the third 10.2.3 information input of the first comparator 10.2 and the first 10.3.1 information input of the second comparator 10.3, the fourth information output 10.1.4 of the memory register 10.1 is connected to the third 1 0.3.3 information input of the second 10.3 comparator and the first 10.4.1 information input of the third 10.4 comparator, the first S-bit information input 10.1.1 of the memory register being the first 10.1 information input of the role function evaluation unit 10, the fifth 10.1.5 and P-bit the sixth 10.1.6 control inputs of the memory register 10.1 are the second 10.2 and P-bit third 10.3 control inputs of the role function evaluation unit 10, the information outputs of the first 10.2, second 10.3 and third 10.4 comparators form a three-digit fourth 10.4 information Exit estimation unit 10 functions role.

BRO 11 is designed to determine the current and final rating assessments of the level of readiness for innovative activity by the values of the generalized intelligence indicators of the subjects. BRO 11 can be implemented in various ways, in particular as shown in FIG. eighteen.

The BRO consists of the address counter 11.1, the first 11.2 and the second 11.5 memory registers, the comparator 11.3, the shift register 11.4, and the linear recursive registers 11.6-11.V. The second 11.6.2-11.V.2 information inputs of linear recurrent registers 11.6-11.V are connected to the V-bit information output 11.2.3 of the first memory register 11.2, the third information outputs 11.6.3-11.V.3 of linear recurrent registers 11.6-11.V are connected to the V-bit third information input 11.3.3 of the comparator 11.3. Information output 11.3.1 of the comparator 11.3. connected to the fourth control inputs 11.6.4-11.V.4 of the linear recurrence registers 11.6-11.V and to the first information input 11.4.1 of the pulse counter 11.4, the G-bit information output 11.4.3 of the pulse counter 11.4 is connected to the G-bit information input 11.5.2 of the second memory register 11.5, I-bit information output 11.1.2 of the address counter 11.1 is connected to I-bit control inputs 11.2.1 and 11.5.1 of the first 11.2 and second 11.5 memory registers, moreover, the first information input 11.1. 1 counter address 11.1 is the second 11.2 information input BRO, tr The second control input 11.1.3 of the address counter 11.1 is the eighth 11.8 control input of the BRO, the second 11.2.2 and S-bit fourth 11.2.4 the inputs of the first memory register 11.2 are the fourth 11.4 synchronizing and third 11.3 information inputs of the BRO, I-bit output 11.1 .2 address counters 11.1 and the G-bit output 11.5.5 of the second memory register 11.5 form the seventh 11.7 O-bit, where O = I + G, the information output of the BRO, the third control input 11.5.3 of the second memory register 11.5 and the first 11.1.1 the information input of the address counter 11.1 are combined and are The pure 11.6 synchronizing input of the BRO, the sixth synchronizing inputs of 11.6.6-11.V.6 of the linear recurrent registers 11.6-11.V are combined and are the fifth 11.5 synchronizing input of the BRO, fifth control inputs of 11.6.5-11.V.5 linear recurrent registers 11.6-11.V are combined and are the tenth 11.10 control input of the BRO, control inputs 11.6.7-11.6.m, 11.7.7-11.7.m, ... 11.V.7-11.Vm of linear recursive registers 11.6-11.V form an H-bit, where H = (m-5) (V-5), the ninth 11.9 control input of the BRO, and the first control inputs 11.6.1-11.V.1 of the linear recurrence registers 11.6-11.V, the fourth 11.5. 4 w swarm 11.4.2 11.2.5 and fifth control inputs of the second memory register 11.5, a pulse counter 11.4 and 11.2 of the first memory register are merged and the first control input 11.1 BRD.

Linear recurrence registers 11.6-11.V (Fig. 19) of the block of rating estimates are intended for ordering in increasing (decreasing) values of generalized intelligence indicators corresponding to each subject. The principle of its work consists in sequentially comparing the values of the generalized index of intelligence corresponding to the next subject with all the previous values. The next value of the generalized index of intelligence is inserted into the desired position by controlling the length of the linear recursive register using a trigger key, which includes the following elements: logical element "AND" 11.V.1, inverting element 11.V.2, delay triggers 11 .V.3, 11.V.5. Using delay triggers 11.V.5 ... 11.V.m-1, the required length of the linear recursive register is set. The maximum length of a linear recurrence register (m) is determined by the number of bits of the binary code corresponding to the maximum number of subjects. The number of linear recurrence registers (V-5) is determined by the number of bits of the binary code corresponding to the maximum value of the generalized index of intelligence. Using the logical AND element 11.V.1, linear recurrence registers are switched either to mode I - ordering and determining the current rating, or to mode II - determining the final rating.

All elements of the described device blocks are made on standard potential-pulse elements and are described in the well-known literature:

- clock generator [7] p. 243-273, 11] p. 96;

- binary number divider [8, 9];

- binary number multiplier [8];

- decoder [7] p. 112-127 [1] p. 173-177;

- demultiplexer [7] with. 128-134, [1] p. 178-180, [2] p. 76;

- comparator [1] p. 230-234;

- accumulative adder [1] p. 149-150, 216-221, 228;

- counter [7] sec. 189-205, [1] p. 102-106, 125-140, [2] p. 96;

- reverse counter [1] s. 106-108;

- multiplier [1] s. 225-227;

- calculator of the square root [3];

- parallel shift register [7] p. 177-189, [1] p. 144-148;

- register memory [1] s. 272-274, [2] p. 95;

- flash memory [1] p. 275-276;

- random access memory [1] p. 263-272;

- triggers [7] p. 153-177, [1] p. 65-80;

- trigger key [1] s. 93-94;

- segmented liquid crystal indicator [7] p. 273-278;

- graphic liquid crystal indicator [10];

- shift register [1] s. 151-163.

The claimed device is based on a method for evaluating innovative personality intelligence, known by the patent of the Russian Federation No. 2230490 dated 06/20/2004 [Bulletin No. 17 2004]. The method uses the concept of a three-vector model of innovative intelligence and a graphical representation of its calculated indicators as elements of a part of the area of the corresponding sectors of the unit circle discogram described in detail in [11, p. 184-187).

The innovative intelligence of the personality is a way of thinking that allows one to realize and analyze the contradiction that has arisen in culture and put forward an idea and implement its creative solution, which was not at the previous stages of the development of culture, to eliminate it, and then, taking into account possible consequences, contribute to its socialization in culture. [11, p. 44].

In the three-vector model of innovative intelligence (AI), its components are: analytical intelligence (AI), creative intelligence (TI) and practical intelligence (AI) (Fig. 21). The indicated components are estimated by the corresponding coefficients, which are particular indicators of innovative intelligence: K _A , K _T , K _P.

, $$K_T^{\min }$$

, $$K_{П}^{\min }$$

, которые определяют с учетом области инновационной деятельности будущего специалиста (техническая, управленческая, педагогическая и т.д.). В частности, исследования показали, что в области инженерно-технических знаний необходимо принять $$K_{А}^{\min }=\text{65-80}$$

(определяется величиной IQ); $${К}_{Т}^{\min }={\stackrel{⌢}{E}}_{\ddot{I}}^{\min }=\mathrm{0,3}$$

(определяется по тестам «креативность» и «креафорность»). Порядок расчета частных показателей K_А, K_Т, K_П можно рассмотреть на примере вычисления K_Т. Тест представляет собой тестовую батарею, включающую восемь субтестов, объединенных в одну психодиагностическую методику, направленную на измерение общего уровня креативности (K_Т), а также уровней ее S промежуточных частных показателей (в данном случае творческое мышление (М), любознательность (Л), оригинальность (О), воображение (В), интуиция (И), эмоциональность (Э), чувство юмора (Ю), творческое отношение к профессии (П)).Source data includes minimum acceptable levels $$K_{\mathrm{BUT}}^{\min }$$

, $$K_T^{\min }$$

, $$K_P^{\min }$$

which determine, taking into account the field of innovation, a future specialist (technical, managerial, pedagogical, etc.). In particular, studies have shown that in the field of engineering knowledge it is necessary to accept $$K_{\mathrm{BUT}}^{\min }=\text{65-80}$$

(determined by the value of IQ); $${\mathrm{TO}}_T^{\min }={\stackrel{⌢}{E}}_{\ddot{I}}^{\min }=0.3$$

(determined by the tests "creativity" and "creafor"). The procedure for calculating particular indicators K _A , K _T , K _P can be considered by calculating K _T. The test is a test battery, including eight subtests, combined into one psycho-diagnostic technique, aimed at measuring the general level of creativity (K _T ), as well as its S levels of intermediate partial indicators (in this case, creative thinking (M), curiosity (L), originality (O), imagination (B), intuition (I), emotionality (E), sense of humor (Yu), creative attitude to the profession (P)).

In this example, the number of subtests and the number of obtained intermediate partial numerical test results S = 8. The value of the indicator for each subtest is determined by counting the number of matches of the answers of the subject with the answers of the key.

Initial for further evaluation of intermediate psychodiagnostic indicators are numerical test results for S subtests. The normalization of the values of intermediate indicators is carried out by dividing the obtained numerical results for each subtest by the maximum possible numerical result P _m for this subtest.

$$P_{nj}/P_{mj}=r_j\left(\mathrm{one}\right)$$

The discogram (Fig. 22) is a unit circle whose radius R _o = 1. For the adopted sampling step Δr, the number m of inscribed concentric circles is m = 1 / Δr-1. In this case, Δr = 0.1, i.e. m = 9.

The radius of the i-th concentric circumferential r _i = 1-iΔr.

In this example, r ₁ = 1-1 × 0.1 = 0.9; r ₂ = 0.8, etc.

; $${Л}_{н}^{о}=\text{0}\text{,7}$$

; $${О}_{н}^{о}=\text{0}\text{,6}$$

и т.д.After normalizing the values of the numerical test results, they are rounded up taking into account the adopted sampling step Δr. For example, the obtained values: M ^H = 0.78; L ^H = 0.71; О ^Н = 0.58, etc., are rounded to the nearest multiple of Δr = 0.1, i.e. after rounding, normalized values: $$M_n^{\mathrm{about}}=\text{0}\text{,8}$$

; $$L_n^{\mathrm{about}}=\text{0}\text{, 7}$$

; $${\mathrm{ABOUT}}_n^{\mathrm{about}}=\text{0}\text{, 6}$$

etc.

; $${\text{r}}_{\text{2}}={Л}_{н}^{о}=\text{0}\text{,7}$$

; $${\text{r}}_{\text{3}}={О}_{н}^{о}=\text{0}\text{,6}$$

и т.д.The rounded numerical results for all subtests are displayed on the discogram by hatching part of the corresponding sector of the unit circle from its center to the arc of the inscribed concentric circle whose radius r _j is equal to the rounded numerical result of the corresponding subtest, i.e. $${\text{r}}_{\text{one}}=M_n^{\mathrm{about}}=\text{0}\text{,8}$$

; $${\text{<figure-callout id="2" label="r" filenames="00000044.png,00000047.png" state="{{state}}">r</figure-callout>}}_{\text{2}}=L_n^{\mathrm{about}}=\text{0}\text{, 7}$$

; $${\text{<figure-callout id="3" label="r" filenames="00000040.png,00000043.png" state="{{state}}">r</figure-callout>}}_{\text{3}}={\mathrm{ABOUT}}_n^{\mathrm{about}}=\text{0}\text{, 6}$$

etc.

The obtained intermediate results provide the basis for determining both partial and generalized K _T psychodiagnostic indicators through the ratio of the hatched S _j and the total S _o areas of the respective sectors. This fact is due to the fact that in order to achieve the highest indicators, the test person must correctly answer all questions, which corresponds to the values of all particular indicators equal to unity, and, therefore, the entire unit circle will be shaded. With particular indicators differing from unity, only part of the unit circle (sector) is shaded. The ratio of the hatched and total areas of the unit circle (sector) shows the level of the total (private) indicator without involving any subjective assessments of the researcher.

. Следовательно, j-й промежуточный психодиагностический показатель K_j определяется как $$K_j=S_j/S_o=r_j^2$$

, а частный психодиагностический показатель K_Т по полной тестовой батарее определяется выражениемFor a unit circle, the total area S _{o of} its any j-th angular sector S _o = π / S [m ² ]; the area S _{j of the} hatched part of the angular sector at the level of the inscribed concentric circle with radius r _j is $$S_j=\pi r_{\mathrm{<figure-callout\; id="2"\; label="j"\; filenames="00000044.png,00000047.png"\; state="\{\{state\}\}">j</figure-callout>}}^2/S\left[\text{ì}{}^{\text{2}}\right]$$

. Therefore, the j-th intermediate psychodiagnostic indicator K _j is defined as $$K_j=S_j/S_o={\mathrm{<figure-callout\; id="2"\; label="r\; j"\; filenames="00000044.png,00000047.png"\; state="\{\{state\}\}">r\; </figure-callout>}}_j^{}$$

, and a private psychodiagnostic indicator K _T for a full test battery is determined by the expression

$$K_T=\left(\mathrm{one}/n\right){\displaystyle \sum _{j=\mathrm{one}}^n{r}_j^2}\left(2\right)$$

The generalized indicator of innovative intelligence in accordance with the three-vector model (Fig. 21) is estimated as the rms value of normalized particular indicators:

$$K_{\mathrm{AND}\mathrm{AND}}=\left(\mathrm{one}/3\right)\sqrt{{\left(K_A^H\right)}^2+{\left(K_T^H\right)}^2+{\left(K_P^H\right)}^2}\left(3\right)$$

, $$K_T^{\min }$$

, $$K_{П}^{\min }$$

).The normalized values of particular indicators are determined in relation to the specified minimum permissible values ( $$K_{\mathrm{BUT}}^{\min }$$

, $$K_T^{\min }$$

, $$K_P^{\min }$$

)

The obtained elementary relations allow us to automate the processing and final assessment of the psychodiagnostic indicator using a computer.

Thus, the first action performed by the claimed device is the summation of the number of points P _P for the correct execution of subtests.

The second action of the device is the normalization of intermediate indicators of testing by dividing by the formula (1).

The third step is to calculate the root mean square value according to the formula (2), for which it is necessary to perform:

;a) squaring $${\mathrm{<figure-callout\; id="2"\; label="r\; j"\; filenames="00000044.png,00000047.png"\; state="\{\{state\}\}">r\; </figure-callout>}}_j^{}$$

;

;b) summation $${\displaystyle \sum _{j=\mathrm{one}}^{\mathrm{<figure-callout\; id="2"\; label="n\; r\; j"\; filenames="00000044.png,00000047.png"\; state="\{\{state\}\}">n\; </figure-callout>}}{r}_j^{}{}_2^{}}$$

;

.c) dividing by the number of tests in the battery of tests $$\text{(1 / n)}{\displaystyle \sum _{j=\mathrm{one}}^{\mathrm{<figure-callout\; id="2"\; label="n\; r\; j"\; filenames="00000044.png,00000047.png"\; state="\{\{state\}\}">n\; </figure-callout>}}{r}_j^{}{}_2^{}}$$

.

The fourth action is the determination of those subjects in whom the values of two or more particular indicators are less than the established permissible minimum values. For this, a comparison is necessary and the choice is on a majority basis.

The fifth action is the determination of the subjects, which corresponds to the role function "universal". For this, it is necessary to determine the subjects for whom the values of all particular indicators exceed the threshold.

The sixth action is to determine the role function of the test person. For this, it is necessary to determine the maximum of the values of particular indicators.

The seventh action is the calculation of a generalized indicator of innovative intelligence by the formula (3) for which it is necessary to perform:

; $$K_T^H=K_T/K_T^{\min }$$

; $$K_{П}^H=K_{П}/K_{П}^{\min }$$

;a) division: $$K_A^H=K_A/K_A^{\min }$$

; $$K_T^H=K_T/K_T^{\min }$$

; $$K_P^H=K_P/K_P^{\min }$$

;

; $${\left(K_{Т}^H\right)}^2$$

; $${\left(K_{П}^H\right)}^2$$

;b) squaring: $${\left(K_A^H\right)}^2$$

; $${\left(K_T^H\right)}^2$$

; $${\left(K_P^H\right)}^2$$

;

;c) summation: $${\left(K_A^H\right)}^2+{\left(K_T^H\right)}^2+{\left(K_P^H\right)}^2$$

;

;d) calculation of the square root: $$\sqrt{{\left(K_A^H\right)}^2+{\left(K_T^H\right)}^2+{\left(K_P^H\right)}^2}$$

;

.d) division: $$\left(\mathrm{one}/3\right)\sqrt{{\left(K_A^H\right)}^2+{\left(K_T^H\right)}^2+{\left(K_P^H\right)}^2}$$

.

Depending on the goals, content and purpose of the test, a qualitative assessment of the levels of indicators: “low”, “medium”, “high” can be different. In the particular case of the application of tests of achievements, creativity or special abilities, representing psycho-diagnostic methods for measuring relevant skills, knowledge, skills; creative abilities or individual aspects of intelligence and psychomotor functions, depending on the numerical values of the psychodiagnostic indicators K, the corresponding personality characteristics are evaluated as: “low” at K≤0.3; “Average” at 0.3 <K≤0.6; “High” at K> 0.6.

The fifth action of the device is to compare the values of particular indicators with predefined values and display the evaluation results.

The claimed device operates as follows.

The order of operation of the device is represented by a block diagram of the algorithm (Fig. 20).

Preliminarily, in the synchronization unit BS 8 through the "Input data bus 1" the data necessary to coordinate the operation of the elements of the device are recorded. In the control unit BU 1 through the "Spike of initial data 2" write the data of the test tasks and the data necessary for calculating the particular and generalized indicators of intelligence. In this case, the recording of the contents of the test tasks is carried out in the memory register 1.6 of the control unit 1 (see Fig. 1, Fig. 2) through its information output 1.6.4 and input 1.1.6 of the first module 1.1 when applying the potential of the logical unit to the control input "Record "1.5.3. Data is written to the memory registers of the firmware modules 1.1-1.4 BU 1 through the corresponding information outputs / inputs of the memory registers and the inputs of the address counters.

The device is prepared for operation by pressing the button of the sensor “Setting 0” 2.3 OBD 2, while the counters and the shift register of the control unit, synchronization unit and rating unit are set to the initial (zero) state. On the graphic liquid crystal indicator 7.17 BI 7, greeting information is displayed from the starting address of the memory register 1.6 of the control unit. The device enters the "Waiting for test selection" mode.

The choice of the first or the next test is carried out by single-clicking on the button of the “Test selection” sensor 2.2 OBD 2, the status of the test number counter 2.5 is changed and the binary code of the test number is supplied to output 2.5 of the DB 2. At the same time, the answer number counter 2.4 is reset, and from the output 2.5 DB 2, the binary code of the test number is supplied to the third input 1.1.1.3 of the comparator 1.1.1 of the first 1.1 of the control unit 1. From the starting address of the memory register 1.1.2, the binary code of the number is supplied to the third 1.1.1.3 input of the comparator 1.1.1 of the first module of the control unit 1 first test task. If the binary codes match at the inputs of the comparator 1.1.1, its output 1.1.1.2 receives the potential of a logical unit at the input 1.1.3.1 of the address counter 1.1.3. The address counter 1.1.3 changes its state, and from its output, a binary code of the data address arrives at the input 1.1.2.6 of the memory register 1.1.2. From the corresponding memory cell of the memory register 1.1.2 from its fifth output 1.1.2.5, the binary code of the current job address is supplied through the output 1.1.10 of module 1.1 to the address input 1.6.1 of memory register 1.6 BU 1, and from the first output 1.1.2.1 of the memory register 1.1.2 the binary code of the number of the next test task is fed to the input 1.1.1.1 of the comparator 1.1.1. From the corresponding address of the memory register 1.6 through the output 1.9 BU 1, the data are fed to the input 7.9 BI 7, as a result of which, on the graphic liquid crystal display 7.7, the contents of the next test task and the answers to it are displayed.

From the memory register 1.1.2 of the first module 1.1 through its output 1.1.5 and output 1.4 BU 1 to the second input 3.1.3 of the comparator 3.1 BKO 3 the binary code of the number of the correct answer is supplied, and binary 3.2 is supplied to the input 3.2.4 of the multiplier 3.2 BKO 3 code of the weight coefficient of the test task. Thus, the device enters the “Waiting for a response selection” mode.

The number of one of the answer options is selected by pressing the button of the “Answer Selection” sensor 2.1 DB 2. The state of the reverse counter of the answer number 2.4 is changed. The binary code of the selected answer number from the output of the counter of the answer number 2.4 is fed to the input of the memory register 2.7 DB 2. When the “Record” button 2.6 is pressed, the binary code of the response number is written to the memory register 2.7 and through output 2.3 of the DB 2, input 3.1 of BKO 3 will go to the first input 3.1.1 of the comparator 3.1 BKO 3. If the selected answer is correct, the codes at the inputs of the comparator 3.1 are the same and its output 3.1.1 appears the potential of the logical unit, which is fed to the input 3.2.1 of the multiplier 3.2 BKO 3. If the selected option the answer is incorrect, then from exit 3.1.2 com Arathor 3.1 arrives potential logic zero at the input of the multiplier 3.2.1 3.2.

Scoring for the correct answer is carried out by applying to the second synchronizing input 3.2.2 of the multiplier 3.2 BKO 3 clock pulses, which are generated by the synchronization unit. The enabling signal for applying clock pulses to the multiplier 3.2 is the potential of the logical unit, which is received when the “Record” sensor button is pressed 2.6. DB 2 through the output 2.6 of the DB, the second input 1.8.2 of the element "OR" 1.8 to the output 1.14 BU 1 and then to the input 8.15 BS 8.

Thus, the number of points corresponding to the weight coefficient of the assignment is accrued for the correct answer, and zero points are awarded for the incorrect answer. The binary code corresponding to the number of points awarded comes from the output 3.2.3 of the multiplier 3.2 through the output 3.3 of BKO 3, the input 4.1 of the BPPB 4 to the input 4.1.1 of the first accumulating adder 4.1 of the BPPB, which performs the summation of the incoming binary code with its source binary code.

BS 8 operates on the principle of a firmware [4, 5, 6], and the number of clock pulses supplied is determined by data previously recorded in memory register 8.7. The status of the address counter 8.6 determines the output address of the demultiplexer 8.3, from which clock pulses are supplied to the corresponding units of the device, as well as the address of the memory register cell 8.7, in which the binary code of the corresponding number of clock pulses supplied to these blocks is recorded. From the start or next address of the memory register 8.7. to the second information input 8.5.2 of the comparator, a binary code of the number of ticks is supplied for the next stage of the device operation. From the output 1.14 BU 1, the potential of the logical unit comes through the fifteenth 8.15 input BS 8, the element "OR" 8.9 to the input "Start" 8.2.4 trigger key 8.2, which opens. With GTI 8.1, clock pulses through trigger key 8.2 are fed to input 8.3.1 of demultiplexer 8.3 and input 8.4.2 of the clock counter 8.4. If the codes coincide at the inputs of the comparator 8.5, a pulse is transmitted from its output 8.5.3 to the “Stop” input 8.2.2 of the trigger key, which closes through output 8.14 BS 8 to input 1.15 BU 1. Through the delay element 8.8, the pulse from the comparator 8.5 arrives at the address counter 8.6, it increases its value by one and BS 8 is alerted to the next stage of operation of the device. The duration of the control pulse at the output 8.5.3 of the comparator 8.5 is determined by the delay interval of the delay element 8.8. Two series are fed sequentially to BPPB 4, BVChP 5, and three series of clock pulses from BS 8 to BVOP 6 and BRO each, for which outputs 8.3.4, 8.3.6, 8.3.8, 8.3.9, 8.3.11, 8.3.12, 8.3.13 of the demultiplexer are connected via the “OR” element 8.9 to the “Start” input 8.2.3 of the trigger key 8.2.

The described operation steps of the device are repeated until the comparator 1.2.1 of module 1.2 BU 1 fixes the equality of codes “Number of tasks in the test” at the output of memory register 1.2.2 and the output of the address counter 1.1.3 of module 1.1 BU 1.

Preliminary scoring includes summing on the first accumulating adder 4.1 BPPB 4 the total number of points for all completed test tasks of the first (or the next test), calculating on the divider 4.2 the average number of points accrued per test, calculating the sum of the squares of the average points for the battery of tests using the multiplier 4.3 and the second accumulating adder 4.4. The fourth information input 4.2.4 of the divider 4.2 from the memory register 1.2.2 of the module 1.2 BU 1 provides a binary code corresponding to the value of the number of test tasks in the test. On the multiplier 4.3, squaring the average number of points per test is performed. From the output of the multiplier, the code corresponding to the square of the average number of points for the test is fed to the second accumulative adder 4.4. The second accumulative adder 4.4 sequentially adds the binary codes arriving at its input, as a result of which a code is generated at its output corresponding to the sum of the squares of the average values of the number of points accrued for the passed tests.

The enable signal for alternately supplying clock pulses to the divider 4.2 and then to the multiplier 4.3 is the pulse coming from the output 1.2.1.2 of the comparator 1.2.1 through the output 1.2.7 of the module 1.2, the shift register 1.7, the element "OR" 1.8, the output 1.14 BU 1 input 8.15 BS 8, through the element "OR" 8.9 BS 8 on the trigger key 8.2. The duration of the control signal at the output 1.2.1.2 of the comparator 1.2.1 is determined by the interval of the delay element 1.2.4 of module 1.2.

The described operation steps of the device are repeated until the comparator 1.3.1 of module 1.3 of BU 1 fixes the equality of the codes “Number of tests in the test battery” at the output of address counter 1.2.3 of module 1.2 and at the output of memory register 1.3.2.

The calculation of the private indicator includes the calculation of the average value of the number of points for the battery of tests on the first divider 5.2, the calculation of the normalized value of the private indicator on the second divider 5.3, the comparison of the normalized value with the preset minimum value of the private indicator on the comparator 5.1.

The potential of a logical unit at the output of the comparator 1.3.1 of module 1.3 of BU 1 is a control signal for the address counter 1.3.3, according to which the data for calculating the private indicator and evaluating the role function are supplied from the corresponding address of the memory register 1.3.2. In this case, the binary code corresponding to the number of tests in the test battery and the code corresponding to the normalizing value of the private indicator, as well as the code corresponding to the minimum acceptable normalized value of the private indicator from the outputs 1.3.2.3-1.3.2.5 of the memory register 1.3.2 of module 1.3 are fed from the output 1.6 control unit 1 through the input 5.5 of the inverter 5 to dividers 5.2, 5.3 and the comparator 5.1 of the inverter 5.

The enabling signal for sequentially supplying a series of clock pulses to the first 5.2 and second 5.3 dividers is the pulse coming from the output of the comparator 1.3.1 of module 1.3 BU 1, through its output 1.3.9, shift register 1.7, element "OR" 1.8, output 1.14 BU 1, input 8.15 BS 8. The delay element 1.3.4 of module 1.3 BU 1 determines the duration of the control pulse at the output 1.3.1.2 of comparator 1.3.1. At the end of two consecutive series of clock pulses coming from BS 8 to the I / O 5, a binary code is generated at the output of the 5.4 I / O that corresponds to the value of the private indicator.

The display of the private indicator score is carried out according to the signal from the output 5.1.2 of the comparator 5.1 BVChP 5, which is formed at an equal or greater value of the private indicator relative to a given minimum normalized level. In this case, through input 7.1 BI 7 enters input 7.3.1 of demultiplexer 7.3. From the outputs 7.3.3-7.3.5 of the demultiplexer 7.3, the potential of the logical unit is supplied to the triggers 7.14-7.16 to turn on one of the indicators 7.25-7.27.

A generalized assessment of readiness for innovative activity is formed by BVChK 9 by a majority choice of the primary number of those particular intelligence indicators whose values exceed predetermined threshold values. If all particular indicators of intelligence have values that exceed thresholds, then the display unit displays the signal "Universal". At the same time, logical “1” is read from all the cells of the memory register 9.1 and through the element “I” the high potential is fed to the input 7.2 of the display unit and through the trigger 7.13 to the input of the “Universal” indicator. If two or more particular indicators are below the threshold, then the signal “Not Ready” is displayed on the display unit. A generalized assessment is formed by the selection unit using the logical element “AND” and the majority element “M≥2”. In this case, the potential of the logical “1” comes from the output of the majority element 9.2 through the output 9.4 of the selection block and through the input 7.3 of the display unit and trigger 7.28 to the input of the “Not Ready” indicator.

Zeroing the first 4.1 and second 4.4 accumulating adders BPPB 4 to prepare them for the next battery of tests is carried out by a clock pulse coming through input 4.4 BPPB 4.

The described operation steps of the device are repeated until the comparator 1.4.1 of module 1.4 BU 1 determines the equality of the codes “Number of test batteries” at the output of the memory register 1.4.2 of module 1.4 BU 1 and at the output of the address counter 1.3.3 of module 1.3.

The definition of the role function is carried out by determining the private indicator, the value of which has the greatest value in comparison with other private indicators. At the same time, the values of the private indicators from the ESP 5 arrive sequentially and are recorded in the register 10.1 BORF 10. At the address coming from the BU 1, the values of the private indicators from the register 10.1 are sent to the first 10.2, second 10.3 and third 10.4 comparators. As a result of comparison on comparators 10.2, 10.3, 10.4, the corresponding indicators “Analyzer”, “Generator”, or “Realizer” BI 7 are turned on.

The calculation of the generalized gel showing in BVOP 6 includes the calculation of the sum of the squares of the values of the private indicators using the multiplier 6.1 and the accumulating adder 6.2, the calculation of the rms value of the private indicators using the square root calculator 6.3 and the divisor 6.4.

The potential of the logical unit at the output of the fourth comparator 1.4.1 of module 1.4 of control unit 1 is a control signal for the address counter 1.4.3, according to which from the memory register 1.4.2 of module 1.4 through its output 1.4.5, output 1.10 control unit 1, through input 6.7 BVOP 6 is supplied to the fourth information input 6.4.4 of the divider 6.4 BVOP 6 binary code "Number of test batteries".

The enabling signal for feeding consecutive series of clock pulses to the multiplier 6.1, the square root calculator 6.3 and the divider 6.4 BVOP 6, as well as to the address counter 11.1 BRO 11, the first 1 1.2 and second 11.5 memory registers, linear recursive registers 11.6-11.V BRO 11 is the pulse that is generated at the output 1.4.1.1 of the fourth comparator 1.4.1 of module 1.4 and arrives through its output 1.4.7, shift register 1.7, the “OR” element 1.8 BU 1 to the output 1.11 BU 1, through the input 8.1 BS 8 and the element "OR" 8.9 to the input "Start" 8.2.3 trigger key 8.2.

Determining the current value of the test subject’s rating by the value of the generalized indicator includes recording the value of the generalized indicator of the next test subject in the first memory register 11.2, comparing this value on the comparator 11.3 with the values of the generalized indicators of the previous test subjects, which are recorded in the corresponding bits of linear recurrence registers 11.6-11.V , counting the results of the comparison by the pulse counter 11.4 and recording the ratings in the second memory register 11.5. In this case, the linear recurrence registers 11.6-11.V are switched on in the “I - ordering and determining the current rating” mode with the help of the logical “1” potential, which comes through their fifth inputs 11.6.4-11.V.5 from the control unit and turns on the first trigger 11.V.3 to shift mode, and the third trigger 11.V.5 disables. The insertion of the value of the generalized indicator “in the middle” is carried out by turning on or off the first triggers 11.6.3 ... 11.V.3 in the rings of linear recursive registers 11.6-11.V. The identification number of the test subject and the corresponding current rating value is displayed on indicators 7.18 and 7.19 BI 7.

The determination of the final rating is carried out in a similar way, the difference is that the linear recurrence registers 11.6-11.V are included in the "II - determination of the final rating" mode. At the same time, the logic 0 potential comes from BU 1 through the tenth 11.10 input of the BRO 11, the fifth inputs 11.6.5-11.V.5 of the linear recurrent registers 11.6-11.V to the inputs of the logical elements “AND” 11.V.1 which disable the first triggers 11.V.3, and the third triggers 11.V.5 includes in shift mode.

The enabling signal for supplying clock pulses to the BRO 11 in the “II” mode is the pulse that is generated at the output 1.5.1.2 of the fifth comparator 1.5.1 of the module 1.5 and enters through its output 1.5.8, the shift register 1.7, the “OR” element 1.8 BU 1 to the output 1.14 BU 1, through the input 8.15 BS 8 and the element "OR" 8.9 to the input "Start" 8.2.4 trigger key 8.2.

The size of the linear recurrence registers 11.6-11.V is determined by the number of subjects in the group and is set by submitting a binary code to their control inputs from the seventh to the mth. The corresponding code is supplied from the fifth module 1.5 BU 1 through its twelfth 1.12 N-bit output and the ninth 11.9 input BRO 11.

The enabling signals at BS 8 for supplying clock pulses come from the second, third, fourth and fifth modules of the control unit 1 with a delay corresponding to the parameters of the delay elements 1.1.4-1.5.4. In this case, the timely supply of the next enable signal from the BU 1 modules to BS 8 is provided by a shift register 1.7 BU 1, which performs a delay of the enable signals until the completion of the next stage of the device operation. The synchronizing signal ensuring the coordinated operation of the control unit 1 and BS 8 is the pulse coming from the output 8.5.3 of the comparator 8.5 BS 8 through its fourteenth output 8.14, the fifteenth input 1.15 BU 1 to the seventh synchronization input 1.7.7 of shift register 1.7.

The result of the calculation of the generalized indicator is displayed on the segment liquid crystal indicator 7.20, to which, through the Z-bit output of the decoder 7.2, the code "Value of the generalized indicator" is supplied from the output of the divider 6.4 BVOP 6.

Thus, the introduction of new nodes and constructive relationships makes it possible to ensure efficiency, simplify scaling depending on the number of subjects, increase the reliability of the assessment due to the possibility of using heterogeneous tests and a two-level assessment using private and generalized indicators, and provide a simple modification of the structure and content of tests by changing the initial data in the device firmware, select candidates for the creative team according to established criteria and rating in a group of candidates, the definition for each candidate of his functional role in the creative team.

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Claims (7)

1. A device for rating assessing the level of readiness for innovative activity of members of the creative team, containing a sensor unit, D≥2-bit, the information output of which is connected to the D-bit information input of the response coding unit (BCO), the private indicator calculation unit (BCHP), the sixth control output of which is connected to the first control input of the display unit (BI), a N≥2-bit control input of the I / O is connected to the TV-bit control output of the control unit, P≥2-bit information input to It is connected to the P-bit control output of the sensor unit, the sixth and fourth control outputs of which are connected respectively to the third and first control inputs of the control unit, K≥2-bit and M≥2-bit information outputs of the control unit are connected respectively to the K-bit information input BKO and to the M-bit information input BI, characterized in that it additionally introduced a synchronization unit (BS), a block preliminary estimates of points (BPPB), a unit for calculating the generalized indicator (BVOP), b team member selection lock (BVCHK), role function evaluation unit (BORF) and rating rating unit (BRO), the second control input of which is connected to the second control output of the sensor block, the fourth, fifth and sixth synchronizing inputs of the BRO are connected to the tenth, eleventh and the twelfth synchronizing outputs of the synchronization unit, the eighth, H≥2-bit ninth and tenth control inputs of the BRO are connected to the eleventh, twelfth H-bit and thirteenth control outputs of the control unit, respectively and the seventh O≥2-bit information output of the BRO is connected to the O-bit sixth information input of the BI, the S≥2-bit information input of the BORF is connected to the S-bit information output of the BCI, the fourth three-bit information output of the BORF is connected to the fourth information input of the BI , the first information input of the HVAC is connected to the sixth information output of the HVAC, the third and fourth information outputs of the HVAC are connected respectively to the second and third information inputs of the BI, S-bit information input of the BV П is connected to the S-bit information output of the BVCHP, the third, fourth and fifth synchronizing inputs of the BVOP are connected to the seventh, eighth and ninth synchronizing outputs of the synchronization block, the S-bit seventh control input of the BVOP is connected to the S-bit control output of the control unit, S- the BVOP bit information output is connected to the S-bit information inputs of the BI and BRO, the first and fifth S-bit information input and the output of the BPPB are connected respectively to the B-channel S-bit information output and OVC of the BVCHP, the sixth S-bit input of the BPPB is connected to the fifth S-bit control output of the control unit, the second and third synchronizing inputs of the BPPB are connected respectively to the third and fourth synchronizing outputs of the synchronization block, the second synchronizing output of which is connected to the synchronizing input of the BKO, the fifth synchronizing output the synchronization unit is connected to the second synchronizing input of the I / O frequency converter, the sixth output of the synchronization unit is connected to the fourth and third synchronizing inputs, respectively B PPB and BVCHP, as well as to the second synchronizing input of the BVCHK, the thirteenth output of the synchronization unit is connected to the second synchronizing input of the BVOP and the seventh synchronizing input of the BI, the seventh control output of the control unit is connected to the fifth and second control inputs of the BVCHK and BORF, the eighth P-bit control output the control unit is connected to the third P-bit control input BORF, the fourteenth control output and the fifteenth control input of the control unit are connected respectively to the fifteenth control the input and fourteenth output of the synchronization unit, the first control output of the sensor unit is connected to the first control inputs of the synchronization unit and BRO, as well as to the eighth control input of the BI, and the synchronization unit and control unit are equipped with F≥2-bit and W≥2-bit buses, respectively input source data synchronization and control, respectively. 2. The device according to claim 1, characterized in that the block preliminary calculation of points (BPPB) consists of cascade on the S-bit information signal of the first accumulating adder, divider, multiplier and second accumulating adder, the first and second elements "or", and The 5-bit information input of the first and the output of the second accumulating adders are respectively 5-bit information input and output of the BPPB, the synchronizing input of the divider is the second synchronizing input of the BPPB, the second inputs are the multiplier and the first element “or” are combined and are the third synchronizing input of the BPPB, the third inputs of the first and second accumulative adders are connected to the outputs of the first and second elements “or”, the second input of the second element “or” is the fourth synchronizing input of the BPPB, the fourth S- the bit control input of the divider and the combined third inputs of the first and second elements “or” are, respectively, S-bit seventh and sixth control inputs of the BPPB. 3. The device according to claim 1, characterized in that the generalized indicator calculation unit (BVOP) consists of a cascade multiplier connected by the S-bit information signal, the accumulating adder, a square root calculator and a divider, the first S-bit multiplier information input and the third The S-bit information output of the divider is respectively the S-bit information input and output of the BVOP, the fourth S-bit control input of the divider is the seventh S-bit control input of the BVOP, synchronizing The input of the multiplier, the input of the square root calculator, and the input of the divider are the third, fourth, and fifth synchronizing inputs of the BVOP, respectively, and the control input of the accumulating adder is the second control input of the BVOP. 4. The device according to claim 1, characterized in that the synchronization unit (BS) consists of a clock pulse generator, a trigger key, a demultiplexer, a clock counter, a comparator, an address counter, a memory register, a delay element, and an "OR" element, an information output the comparator is connected to the “Stop” input of the trigger key and through the delay element to the information input of the address counter, D≥2-bit first and second information inputs of the comparator are connected respectively to the D-bit information output of the counter x pulses and the output of the memory register, the R≥2-bit control output of the address counter is connected to the R-bit control inputs of the memory register and demultiplexer, the information output of the trigger key is connected to the information input of the clock counter and the information input of the demultiplexer, the output of the clock generator is connected to the first information input of the trigger key, the control input "Start" of the trigger key is connected to the output of the element "OR", the ninth input of which is the fifteenth control BS input, and the information outputs of the demultiplexer from the third to fourteenth are the synchronizing outputs respectively from the second to thirteenth BS, the fourth, sixth, eighth, ninth, eleventh, twelfth and thirteenth information outputs of the demultiplexer are connected respectively to the second, third, fourth, fifth, the sixth, seventh and eighth inputs of the element "OR", the information output of the comparator is the fourteenth control output of the BS, the inputs "Zero" of the clock counter and the address counter are combined and are the first BS control input, and the D-bit information output and the R-bit address input, as well as the second memory register input that allows recording, form the F-bit BS source data bus, where F = D + R + 1. 5. The device according to claim 1, characterized in that the team member selection unit (BVCHK) consists of a shift register, a majority element, an “I” element and three inverting elements, the third fourth and fifth information outputs of the shift register are connected through the inverting elements to the first, second and third information inputs of the majority element and to the first, second and third inputs of the "And" element, and the first information input of the shift register is the first information input of the BVChK, the second and sixth control The input inputs of the shift register are, respectively, the second and fifth control inputs of the IMSC, and the fourth information outputs of the element “I” and the majority element are the third and fourth information outputs of the IMSC, respectively. 6. The device according to claim 1, characterized in that the role function evaluation unit (BORF) consists of a memory register, first, second and third binary number comparators, a second information output of the memory register is connected to the first information input of the first comparator and the third information input of the third comparator, the third information output of the memory register is connected to the third information input of the first comparator and the first information input of the second comparator, the fourth information output of the memory register is connected to the third information input of the second comparator and the first information input of the third comparator, whereby the first S-bit information input of the memory register is the first information input of the BORF, the fifth and P-bit sixth control inputs of the memory register are the second and P-bit third control inputs of the BORF , the information outputs of the first, second and third comparators form the fourth three-digit information output of the BORF. 7. The device according to claim 1, characterized in that the rating unit (BRO) consists of an address counter, first and second memory registers, a comparator, a pulse counter and V-5 linear recurrent registers, the second information inputs of which are connected to a V-bit the information output of the first memory register, the third information outputs of the linear recurrence registers are connected to the V-bit third information input of the comparator, the information output of which is connected to the fourth control inputs of the linear recurrence registers and to the first information input of the pulse counter, G≥2-bit information output of the pulse counter is connected to the G-bit information input of the second memory register, I-bit, where I≥2 information output of the address counter is connected to I-bit control inputs of the first and the second memory register, the first information input of the address counter is the second information input of the BRO, the third control input of the address counter is the eighth control input of the BRO, the second and S-bit fourth inputs are The first memory register are the fourth synchronizing and third information inputs of the BRO, the I-bit output of the address counter and the G-bit output of the second memory register form the seventh O-bit, where O = G + I is the information output of the BRO, the third control input of the second memory register and the first information input of the address counter is combined and is the sixth synchronizing input of the BRO, the fifth control inputs of linear recurrent registers are combined and the tenth control input of the BRO, the sixth synchronizing the inputs of the linear recurrence registers are combined and are the fifth synchronizing input of the BRO, the control inputs from the seventh to the mth linear recurrent registers form H-bit, where H = (m-5) (V-5), the ninth control input of the BRO, and the first control inputs of linear recurrence registers, the fifth control input of the first, the fourth control input of the second memory registers and the second control input of the pulse counter are combined and are the first control input of the BRO.

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