RU2419199C1 - Driver of differential communication line - Google Patents

Abstract

FIELD: radio engineering. ^ SUBSTANCE: driver of differential communication line includes the first (1) and the second (2) opposite phase sources of signal, which are connected to bases of the first (3) and the second (4) input transistors (T), the first (5) and the second (6) output T the emitters of which are connected to the appropriate emitters of the first (3) and the second (4) input T and connected to the first (7) power supply (PS) through the appropriate first (8) and second (9) current-stabilising bipoles (CB); the third (10) and the fourth (11) output T the emitters of which are connected to the first (7) PS through the appropriate third (12) and fourth (13) CB, as well as the appropriate bases of the first (5) and the second (6) output T; load circuit (14) connected between emitters of the third (10) and the fourth (11) output T; the first pedestal current source (PCS) (15) the first output of which is connected to base of the third (10) output T and to collectors of the first (5) output T, and the second one is connected to the second (16) PS; the second PCS (17) the first output of which is connected to base of the fourth (11) output T and collector of the second (6) output T, and the second one is connected to the second (16) PS. At that, collectors of the first (3) and the second (4) input T are connected to collector power source. To the circuit there introduced is the first (18) and the second (19) auxiliary T, the first PCS (15) is made on the basis of the first (20) additional T, the collector of which is connected to collector of the first (5) output T and base of the third (10) output T; emitter is connected through the first (21) auxiliary resistor to the second (16) PS, and base is connected to offset voltage source (22); the second PCS (17) is made on the basis of the second additional T (23) the collector of which is connected to collector of the second (6) output T and base of the fourth (11) output T; emitter is connected through the second (24) auxiliary resistor to the second (16) PS, and base is connected to offset voltage source (22). At that, base of the first (18) auxiliary T is connected to emitter of the second (23) additional T; emitter of the first (18) auxiliary T is connected to collector of the third (10) output T; collectors of the first (18) and the second (19) auxiliary T are connected to the second (16) PS; base of the second (19) auxiliary T is connected to emitter of the first (20) additional T, and emitter of the second (19) auxiliary T is connected to collector of the fourth (11) output T. ^ EFFECT: improving conversion accuracy of input signals to output voltage at low-resistance load without deterioration of power parametres in static mode, and enlarging the range of operating frequencies. ^ 5 dwg

Description

The invention relates to the field of radio engineering and communication and can be used as a device for amplifying analog differential signals in the structure of “systems on a chip” and “systems in a housing” for various functional purposes (for example, drivers of computer communication lines).

Known differential driver circuit communication lines (DDL), built on the basis of operational amplifiers with negative feedback, which became the basis of many serial circuits of the first and second generations [1-6].

In recent years, DDLs of this class have become more actively used in the structure of microwave devices [1-6], implemented on the basis of SiGe technologies. To a large extent, this is facilitated by the simplicity of establishing the static mode of DDL at low-voltage power supply (1.2-2.1) V, which is typical for SiGe transistors with limiting frequencies of 100-200 GHz.

The closest prototype (figure 1) of the claimed device is a differential communication line driver described in US patent No. 4,691.174 fig.1, containing the first 1 and second 2 antiphase signal sources connected to the bases of the first 3 and second 4 input transistors, the first 5 and second 6 output transistors, the emitters of which are connected to the corresponding emitters of the first 3 and second 4 input transistors and are connected to the first 7 power supply through the corresponding first 8 and second 9 current-stabilizing two-terminal devices, the third 10 and fourth 11 output single transistors, the emitters of which are connected to the first 7 power supply through the corresponding third 12 and fourth 13 current-stabilizing two-terminal devices, as well as the corresponding bases of the first 5 and second 6 output transistors, a load circuit 14 connected between the emitters of the third 10 and fourth 11 output transistors, the first source reference current 15, the first output of which is connected to the base of the third 10 output transistor and the collector of the first 5 output transistor, and the second is connected to the second 16 power source, the second source to the reference current 17, the first terminal of which is connected to the base of the fourth output transistor 11 and the collector of the second output transistor 6 and the other - is connected to the second power source 16, and collectors of the first 3 and second 4 input transistors are connected to a source of power collector.

A significant drawback of the known DDL is that for each of the channels with negative feedback it has a relatively small loop gain in voltage at low resistance (for example, R _n = 50 Ohms). This negatively affects the error in converting the input voltage to the output voltage of the DDL.

The main objective of the invention is to increase the accuracy of conversion of input signals to output voltage at low impedance load without deterioration of energy parameters in static mode, expanding the range of operating frequencies.

This object is achieved by the fact that in the driver of the differential communication line of figure 1, containing the first 1 and second 2 antiphase signal sources connected to the bases of the first 3 and second 4 input transistors, the first 5 and second 6 output transistors, the emitters of which are connected to the respective emitters the first 3 and second 4 input transistors and are connected to the first 7 power source through the corresponding first 8 and second 9 current-stabilizing two-terminal devices, the third 10 and fourth 11 output transistors whose emitters are connected to the first 7 power supply through the corresponding third 12 and fourth 13 current-stabilizing two-pole, as well as the corresponding bases of the first 5 and second 6 output transistors, the load circuit 14 connected between the emitters of the third 10 and fourth 11 output transistors, the first reference current source 15, the first output of which connected to the base of the third 10 output transistor and the collector of the first 5 output transistor, and the second is connected to the second 16 power source, the second reference current source 17, the first output of which is connected it is connected with the base of the fourth 11 output transistor and the collector of the second 6 output transistor, and the second is connected to the second 16 power source, and the collectors of the first 3 and second 4 input transistors are connected to the collector power source, new elements and communications are provided - the first 18 are introduced into the circuit and second 19 auxiliary transistors, the first reference current source 15 is based on the first 20 additional transistor, the collector of which is connected to the collector of the first 5 output transistor and the base of the third 10 output of the second transistor, the emitter through the first 21 auxiliary resistor is connected to the second 16 power source, and the base is connected to the bias voltage source 22, the second reference current source 17 is based on the second additional transistor 23, the collector of which is connected to the collector of the second 6 output transistor and the base of the fourth 11 of the output transistor, the emitter through the second 24 auxiliary resistor is connected to the second 16 power source, and the base is connected to the bias voltage source 22, and the base of the first 18 auxiliary the transistor is connected to the emitter of the second 23 auxiliary transistor, the emitter of the first 18 auxiliary transistor is connected to the collector of the third 10 output transistor, the collectors of the first 18 and second 19 auxiliary transistors are connected to the second 16 power source, the base of the second 19 auxiliary transistor is connected to the emitter of the first 20 additional transistor and the emitter of the second 19 auxiliary transistor is connected to the collector of the fourth 11 output transistor.

A diagram of the inventive device corresponding to the claims is shown in figure 2.

Figure 3-figure 4 shows a diagram of the remote control prototype (figure 3) and the claimed remote control (figure 4) in the Cadence computer simulation environment, and figure 5 shows the transmission coefficient K _{u of the} compared circuits (figure 3, figure 4) from the frequency.

The graphs of figure 5 show that the proposed device is characterized by a smaller error in the amplification of differential signals and a larger upper boundary frequency (24 GTZ). This is an important advantage of the proposed DDL during its implementation as part of the SiGe technological process.

The differential communication line driver of figure 2 contains the first 1 and second 2 antiphase signal sources connected to the bases of the first 3 and second 4 input transistors, the first 5 and second 6 output transistors, the emitters of which are connected to the corresponding emitters of the first 3 and second 4 input transistors and connected to the first 7 power source through the corresponding first 8 and second 9 current-stabilizing two-terminal devices, the third 10 and fourth 11 output transistors, the emitters of which are connected to the first 7 power source through the corresponding the third 12 and fourth 13 current-stabilizing two-pole, as well as the corresponding bases of the first 5 and second 6 output transistors, a load circuit 14 connected between the emitters of the third 10 and fourth 11 output transistors, the first reference current source 15, the first output of which is connected to the base of the third 10 the output transistor and the collector of the first 5 output transistor, and the second is connected to the second 16 power source, the second reference current source 17, the first output of which is connected to the base of the fourth 11 output transistor and the collector of the second 6 output transistor, and the second is connected to the second 16 power source, and the collectors of the first 3 and second 4 input transistors are connected to the collector power source. The first 18 and second 19 auxiliary transistors are introduced into the circuit, the first reference current source 15 is based on the first 20 additional transistor, the collector of which is connected to the collector of the first 5 output transistor and the base of the third 10 output transistor, the emitter is connected to the second 16 through the first 21 auxiliary resistors a power source, and the base is connected to a bias voltage source 22, the second reference current source 17 is based on the second additional transistor 23, the collector of which is connected to the collector the second 6 output transistor and the base of the fourth 11 output transistor, the emitter is connected to the second 16 power source through the second 24 auxiliary resistor, and the base is connected to the bias voltage source 22, and the base of the first 18 auxiliary transistor is connected to the emitter of the second 23 additional transistor, the emitter of the first 18 auxiliary transistor is connected to the collector of the third 10 output transistor, the collectors of the first 18 and second 19 auxiliary transistors are connected to the second 16 source pi anija, the base 19 of the second auxiliary transistor is connected to the emitter of the first additional transistor 20, and an emitter of the second auxiliary transistor 19 is connected to the collector of the fourth transistor 11 output.

Consider the operation of the proposed device of figure 2.

ДДЛ фиг.1-фиг.2 на выходы Вых.1 и Вых.2 определяются петлевым усилением T₁ (T₂) повторителей сигналов на основе транзисторов 3, 5 и 10 (4, 6, 11)Input voltage transfer factors u _x and

DDL of Fig.1-Fig.2 to the outputs of Outputs 1 and 2 are determined by the loop gain T ₁ (T ₂ ) of signal repeaters based on transistors 3, 5 and 10 (4, 6, 11)

where T ₁ = K _y1 K _y2 ,

K _y1 is the gain of the differential stage on transistors 3 and 5;

- коэффициент усиления дифференциального каскада на транзисторах 4 и 6;

- gain of the differential stage on transistors 4 and 6;

- коэффициенты усиления по напряжению эмиттерных повторителей на транзисторах 10 и 11 соответственно.

- voltage gain emitter followers on transistors 10 and 11, respectively.

Moreover

β ₁₀ ≈ β ₁₄ - current gain of the base of transistors 10 and 11;

R ₁₄ - differential load resistance 14;

R _n.aq.A - equivalent resistance in the node "A";

R _n.eq.B - equivalent resistance in the node "B".

If we assume that β ₁₀ ≈β ₁₄ = 50, I ₈ = 2 mA, and R _n = 50 Ohms, then from the last formulas we can find that

With such a small loop gain, the voltage transfer coefficient for each of the DDL outputs will differ from unity.

In the inventive device, conditions are created under which R _n.eq.A and R _{n.eq.B are} significantly increased due to the transmission of increments of the base currents of transistors 18 and 19, proportional to the current in load 14, to nodes "A" and "B"

,

- эквивалентные сопротивления в узлах «А» и «В» схемы фиг.2.Where

,

- equivalent resistance in nodes "A" and "B" of the circuit of figure 2.

As a result, the loop gain T ₁ and T ₂ (1), (2) are increased and, as a result, the error in the transmission of input signals at low impedance is reduced, the frequency range of the device is expanded by 4 GHz (Fig. 5).

Thus, the claimed DDL without deterioration of current consumption provides a low-impedance load higher quality conversion of the input signals.

BIBLIOGRAPHIC LIST

1. US Patent No. 4,691.174, fig. 1, fig. 5.

2. US Patent No. 4,667.146 fig. 1.

3. US Patent No. 4,528,515 fig. 2.

4. US Patent No. 4,475.087 fig. 10.

5. US Patent No. 4,536,717 fig. 1.

6. US patent No. 4.714.896 fig. 1.

Claims (1)

A differential communication line driver containing the first (1) and second (2) out-of-phase signal sources connected to the bases of the first (3) and second (4) input transistors, the first (5) and second (6) output transistors, the emitters of which are connected to the corresponding emitters of the first (3) and second (4) input transistors and are connected to the first (7) power source through the corresponding first (8) and second (9) current-stabilizing two-terminal devices, the third (10) and fourth (11) output transistors, the emitters of which connected to the first (7) power source through the corresponding third (12) and fourth (13) current-stabilizing two-terminal devices, as well as the corresponding bases of the first (5) and second (6) output transistors, a load circuit (14) connected between the emitters of the third (10) and fourth (11) output transistors, the first reference current source (15), the first output of which is connected to the base of the third (10) output transistor and the collector of the first (5) output transistor, and the second is connected to the second (16) power source, the second reference current source (17), the first output which is connected to the base of the fourth (11) the output transistor and the collector of the second (6) output transistor, and the second is connected to the second (16) power source, and the collectors of the first (3) and second (4) input transistors are connected to the collector power source, characterized in that in the circuit introduced the first (18) and second (19) auxiliary transistors, the first reference current source (15) is based on the first (20) additional transistor, the collector of which is connected to the collector of the first (5) output transistor and the base of the third (10) output transistor, emitter cut the first (21) auxiliary resistor is connected to the second (16) power source, and the base is connected to a bias voltage source (22), the second reference current source (17) is based on the second additional transistor (23), the collector of which is connected to the collector of the second (6) the output transistor and the base of the fourth (11) output transistor, the emitter through the second (24) auxiliary resistor is connected to the second (16) power source, and the base is connected to a bias voltage source (22), and the base of the first (18) auxiliary trans the torus is connected to the emitter of the second (23) auxiliary transistor, the emitter of the first (18) auxiliary transistor is connected to the collector of the third (10) output transistor, the collectors of the first (18) and second (19) auxiliary transistors are connected to the second (16) power source, base the second (19) auxiliary transistor is connected to the emitter of the first (20) additional transistor, and the emitter of the second (19) auxiliary transistor is connected to the collector of the fourth (11) output transistor.

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