RU2390912C2 - Cascode differential amplifier - Google Patents

Abstract

FIELD: radio engineering.

SUBSTANCE: invention may be used as device for amplification of HF and SHF analogue signals, in structure of analogue microchips of various functional purpose (for instance, operational amplifiers (OA)). Cascode differential amplifier (CDA) comprises the first (1) and the second (2) transistors (T) with combined bases (gates), emitters (sources) of which are connected to according first (3) and second (4) inputs of CDA, and collectors are connected to emitters of the first (5) and second (6) outlet T, and via the first (7) and second (8) current-stabilising dipoles are connected to bus (9) of supply source, the third output T (10), base of which is connected to collector of the first output T (5) and auxiliary dipole I₁₁, emitter is connected to combined bases of the first (5) and second (6) output T, besides collector of the second outlet T (6) is connected to output (12) of CDA. Bases (gates) of the first (1) and second (2) input T are connected to combined bases of the first (5) and second (6) output T.

EFFECT: reduction of consumed static current.

3 cl, 10 dwg

Description

The invention relates to the field of radio engineering and communication and can be used as a device for amplifying RF and microwave analog signals in the structure of analog microcircuits for various functional purposes (for example, operational amplifiers (op amps)).

In modern analog microelectronics, the so-called complementary cascode differential amplifiers based on n-p-n and p-n-p transistors with the architecture of the operational amplifier µА741 are widely used [1-30]. Their main advantage in comparison with the classical differential cascade is a wider frequency range, which makes them especially attractive when building analog microwave devices.

Within its development programs, a number of leading microelectronic companies, including Russian, begin to use technological equipment for 0.25 microns SiGe-technology SGB25VD, capable of producing high-quality heterojunctions within a single cycle. This allows you to implement submicron transistors of the X range, as well as use the economical modes for microwave integrated circuits with a relatively high level of integration. However, the SGB25VD technology imposes additional and significant limitations for analog microcircuitry, expressed in the impossibility of using complementary transistors and relatively low-voltage modes of operation (U _ke.max = 2.9 V or bipolar power supply ± 1.5 V). Creating IP blocks for SiGe SGB25VD technology is (along with its development) the most important task for foreign and domestic centers for the design of analog microcircuits. The present invention relates to this direction of development of microelectronics.

The closest prototype (figure 1) of the claimed device is a CDA described in US patent No. 5521552, containing the first 1 and second 2 input transistors with combined bases (gates), emitters (sources) of which are connected to the corresponding first 3 and second 4 inputs of the cascode differential amplifier, and the collectors are connected to the emitters of the first 5 and second 6 output transistors and through the first 7 and second 8 current-stabilizing two-terminal devices are connected to the first bus 9 of the power source, the third output transistor 10, the base of which is connected with the collector of the first output transistor 5 and the first output of the auxiliary two-terminal 11, the emitter is connected to the combined bases of the first 5 and second 6 output transistors, and the collector of the second output transistor 6 is connected to the output 12 of the cascode differential amplifier, and the second output of the auxiliary two-terminal 11 is connected to the second 9 ^* power supply bus.

A significant drawback of the known KDU is that it has an increased current consumption, which is due to the presence in its architecture (Fig. 1) of a static-mode-setting circuit consuming some current I ₀ , which is not directly involved in amplifying the input signal. The exclusion of this circuit will reduce (ceteris paribus) the power consumption of the control panel.

The main objective of the invention is to reduce the consumption of static current from power supplies.

This object is achieved in that in the cascode differential amplifier of figure 1, containing the first 1 and second 2 input transistors with combined bases (gates), emitters (sources) of which are connected to the corresponding first 3 and second 4 inputs of the cascode differential amplifier, and the collectors connected to the emitters of the first 5 and second 6 output transistors and through the first 7 and second 8 current-stabilizing two-pole connected to the first bus 9 of the power source, the third output transistor 10, the base of which is connected to the collector the torus of the first output transistor 5 and the first output of the auxiliary two-terminal 11, the emitter is connected to the combined bases of the first 5 and second 6 output transistors, the collector of the second output transistor 6 is connected to the output 12 of the cascode differential amplifier, and the second output of the auxiliary two-terminal 11 is connected to the second 9 ^* power supply bus, new elements and communications are provided - the bases (gates) of the first 1 and second 2 input transistors are connected to the combined bases of the first 5 and second 6 output transistors moat.

The amplifier circuit of the prototype is presented in figure 1. Figure 2 shows the inventive device in accordance with claim 1 of the claims.

Figure 3 shows a diagram of the inventive KDU in accordance with claim 2 and claim 3 of the claims.

In Fig. 4, a diagram of the CDD corresponding to Fig. 3 (without a two-terminal 13) in the computer simulation environment PSpice on models of integrated transistors of the Federal State Unitary Enterprise NPP Pulsar is presented, and in Fig. 5 its amplitude-frequency characteristic with "ideal" two-terminal 7, 8 and load (I ₅ ).

The diagram of FIG. 6 in the PSpice environment corresponds to FIG. 3 (without matching circuit 14) in the PSpice environment, and the results of its simulation of the gain are shown in FIG. 7.

The diagrams of Fig. 8 and Fig. 9 fully correspond to Fig. 3. They are a computer model of a CDU in a Cadance environment on SiGe transistor models.

The calculation results of the dependence of the gain K _y on the frequency of these circuits are given in Fig.10.

The cascode differential amplifier of figure 2 contains the first 1 and second 2 input transistors with combined bases (gates), emitters (sources) of which are connected to the corresponding first 3 and second 4 inputs of the cascode differential amplifier, and the collectors are connected to the emitters of the first 5 and second 6 output transistors and through the first 7 and second 8 current-stabilizing two-pole connected to the first bus 9 of the power source, the third output transistor 10, the base of which is connected to the collector of the first output transistor 5 and the first two-pole auxiliary terminal 11, emitter - is connected to the bases of the combined first 5 and second 6 of the output transistors, the collector of the second output transistor 6 connected to the output 12 of the differential cascode amplifier, and the second terminal of the auxiliary two-terminal 11 is connected to a second power source 9 ^* bus. The bases (gates) of the first 1 and second 2 input transistors are connected to the combined bases of the first 5 and second 6 output transistors.

In figure 3, corresponding to claim 2 of the claims, the third 13 current-stabilizing two-terminal network connected to the bases (gates) of the first 1 and second 2 input transistors that are connected to the combined bases of the first 5 and second 6 output transistors through a potential matching circuit is introduced into the circuit fourteen.

In addition, in figure 3, corresponding to claim 3 of the claims, between the differential input source and the first 3, as well as the second 4 inputs of the cascode differential amplifier, the first 15 and second 16 emitter (source) voltage followers are included.

Consider the operation of the circuit of figure 2 (figure 3).

In static mode, the source currents of the differential signal u _c1 and u _c2 flow source currents of transistors 1 and 2, the numerical values of which are set by the first 7 and second 8 current-stabilizing two-terminal, as well as an auxiliary two-terminal 11:

where I _i are the static currents of the two-terminal networks 7, 8 and 11;

I _e6 is the emitter current of the transistor 6.

The emitter current of the transistor 10 is set in the circuit of figure 3 by the third current-stabilizing two-terminal 13 (I _e10 = I ₁₃ ). In the load circuit of the KDU (resistor or reference current source), which is connected to the output of the 12 KDU, the collector current of the transistor 6 I _{k6 flows} . The gate potential of transistors 1 and 2 (u _z12 ) (in accordance with claim 1) is set as the potential of the bases of transistors 5 and 6.

A change in the common-mode component of the input voltages u _c = (u _c1 + u _c2 ) / 2 leads to the same change in the voltages at the bases of transistors 5, 6 and 10, since the currents I ₄ and I ₃ in accordance with (1) and (2) do not change. Thus, the circuit of FIG. 2 has a high attenuation of common mode signals.

If a differential voltage u _in = u _c1 -u _c2 is applied between inputs 3 and 4, this creates an increment of current i ₃ , which is determined by the slope S1 of the input field-effect transistor 1:

The current i ₁ enters the emitter circuit of the transistor 6, and then to the output 12 in the load circuit of the CDU. Thus, input 3 is a non-inverting input of the CDU.

It should be noted that a change in u _I does not lead to a change in the source current of the transistor 2, which follows from equation (1). Thus, on this input 4 KDU always has a high input impedance.

Due to the "double cascode architecture" (transistor 1 and transistor 6), the proposed circuit has a limit value of the upper cutoff frequency and can be used in the microwave range as part of the SGVD25 IHP process technology (Germany).

The first feature of the circuit of Fig. 3 is that the gate potential of the transistors 1 and 2 is shifted to the negative power supply bus 9 by the voltage at the two-terminal network 14. This reduces the static voltage between the gates of transistors 1, 2 and the bases of transistors 5 and 6, expands dynamic range of amplified signals.

The second feature of the circuit of figure 3 is the presence (in accordance with paragraph 3 of the claims) of emitter followers 15 and 16, which reduce the input currents of the CDD of figure 3 and increase its input resistance at a non-inverting input.

A characteristic feature of the circuits of the claimed KDU is the absence of a current source I ₀ (Fig. 1), which degrades by 1 ÷ 2 mA (20 ÷ 25%) the indicators of the known KDU (Fig. 1) for current consumption, does not take part in ensuring the static current of transistors, providing amplification of the input signal.

Thus, the proposed circuitry solution allows the use of SGB25VD process SiGe microwave transistors with a relatively low 2.9 V supply voltage in the structure of not only various analog devices, but also SF blocks of systems on a chip. This important result expands the field of practical use of SGB25VD technology and, therefore, improves the technical and economic performance of microelectronic products. For example, the creation of a new (for the indicated technology) circuitry of wide-range operational amplifiers will allow not only to improve the quality of microwave filters, quadrature modulators, demodulators and other new generation devices that form microwave units of microwave REA, but also to create a new range of ICs of wide functional application .

BIBLIOGRAPHIC LIST

1. US patent No. 3786362.

2. US patent No. 4030044.

3. US patent No. 4059808, Fig.5.

4. US Patent No. 4,286,227.

5. Autosvid. USSR No. 375754, H03F 3/38.

6. Autosvid. USSR No. 843164, H03F 3/30.

7. US Patent No. 3660773.

8. US patent No. 4560948.

9. RF patent No. 2930041, H03F 1/32.

10. Japanese Patent No. 57-5364, H03F 3/343.

11. Czechoslovak Patent No. 134845, cl. 21a ² 18/08.

12. Czechoslovak Patent No. 134849, cl. 21a ² 18/08.

13. Patent of Czechoslovakia No. 135326, cl. 21a ² 18/08.

14. US patent No. 4389579.

15. England patent No. 1543361, H3T.

16. US patent No. 5521552 (figa).

17. US patent No. 4059808.

18. US patent No. 5789949.

19. US Patent No. 4,453,134.

20. US patent No. 4760286.

21. Autosvid. USSR No. 1283946.

22. RF patent No.2019019.

23. US patent No. 4389579.

24. US patent No. 4453092.

25. US patent No. 3566289.

26. US patent No. 4059808 (figure 2).

27. US patent No. 3649926.

28. US patent No. 4714894 (figure 1).

29. Matavkin V.V. High-speed operational amplifiers. - M.: Radio and Communications, 1989.

30. M. Herpy. Analog integrated circuits. - M.: Radio and Communications, 1983, p. 174, Fig. 5.52.

Claims (3)

1. A cascode differential amplifier containing the first (1) and second (2) input transistors with combined bases (gates), emitters (sources) of which are connected to the corresponding first (3) and second (4) inputs of the cascode differential amplifier, and the collectors are connected with emitters of the first (5) and second (6) output transistors and through the first (7) and second (8) current-stabilizing two-terminal circuits are connected to the bus (9) of the power source, the third output transistor (10), the base of which is connected to the collector of the first output transistor (5) and sun auxiliary by a two-terminal device (11), the emitter is connected to the combined bases of the first (5) and second (6) output transistors, the collector of the second output transistor (6) connected to the output (12) of the cascode differential amplifier, characterized in that the base (gate) of the first (1) and the second (2) input transistors are connected to the combined bases of the first (5) and second (6) output transistors. 2. The device according to claim 1, characterized in that a third (13) current-stabilizing two-terminal device is connected to the bases (gates) of the first (1) and second (2) input transistors that are connected to the combined bases of the first (5) and the second (6) output transistors through the potential matching circuit (14). 3. The device according to claim 1, characterized in that between the differential input source and the first (3), as well as the second (4) inputs of the cascode differential amplifier, the first (15) and second (16) emitter (source) voltage followers are included.

Images