RU2284672C1 - Applied television system - Google Patents

Abstract

FIELD: applied television, possible use in video surveillance systems for guarding objects in industrial, medicine and military spheres.

SUBSTANCE: applied television system contains transmitting side, including photo-electric transformer of two images and 1-6 analog-digital converters, and receiving side, including frequencies synthesizer, three video signal channels, 1-6 impulse amplifier blocks, block for modulation of radiations, two piezo-deflectors with reflectors on ends, projection optical system, screen and infrared emitter. On receiving side device additionally contains three-dimensional goggles with infrared receiver, encoder block and code accumulator block. Video signal contains 800 counts in a row, 600 rows and 50 stereo pairs per second.

EFFECT: realization of stereo effect conditions in applied television system, increased frequency of stereo pair frames in two with registration of digital video information on carrier.

13 dwg, 1 tbl

Description

The invention relates to applied television and can be used as television video surveillance devices for the protection of objects in industry, medicine and the army.

An analogue is the PTU-26 applied television installation [1, p. 384], which contains a transmitting camera including a lens, a transmitting tube and a preamplifier, a multicore connecting cable, and a video viewing device including a video amplifier, a CRT, a horizontal scanning generator, and a frame scanning generator. A progressive scan of 50 frames per second is used. The disadvantage of the analogue: the lack of stereo effect when playing the image space. The prototype adopted "Digital stereo television system" [2], containing the transmitting side, including the photoelectric converter of two images / stereo pair /, horizontal and vertical scan units, 1-3 ADCs forming the code representation of the right frame of the stereo pair, 4-6 ADCs forming the code representation the left frame of the stereo pair, two keys and a trigger, a receiving side containing three channels of video signals R, G, B, each of which includes a series-connected register, a code processing unit, a first delay unit and an adder, and W The second delay block includes 1-6 pulse amplifier blocks, a radiation modulation block, horizontal and vertical scanning blocks, a first amplifier and a first, a piezoelectric deflector, a second amplifier and a second piezoelectric deflector, four sources of reference voltages, a projection optical system, a matte screen, an IR emitter and block separate monitoring frames. The transmitting side generates three streams of codes of the right and three streams of codes of the left images, successively following each other. The stereo pair frequency is 25 Hz, the raster scan is line-by-line without reverse moves, the frame scan is without reverse moves. Image reproduction of stereopairs is performed by electron-optical scanning on a matte screen, viewed by the viewer separately using movable filters in the frames of the separate frame observation unit, which includes an IR receiver, a pulse shaper and a piezoelectric motor with a shaft on which frames with rotary mesh filters mounted for rotation are fixed with a frequency of 12.5 Hz. The disadvantages of the prototype: the use of the system as an application is too expensive, the method of viewing frames separately using mechanical rotation of the filters is limited by the frame rate of 25 Hz stereo pairs, this method is unsuitable for a higher frame rate, there is no registration of digital video information.

The purpose of the invention is the implementation of the stereo effect in an applied television system and an increase in the frame rate of stereo pairs. The technical result is the implementation in an applied television system of the stereo effect conditions, an increase in the frame rate of stereo pairs by a factor of 50 Hz / and recording digital video information. The result is achieved by obtaining on the transmitting side stereo pairs from the right and left stereo frames with a frequency of 100 Hz, using a video mode of 800 × 600 × 100 Hz and recording digital surround video information in a compressed form. It uses line-by-line scanning without backward strokes of lines, frame-sweep without backward strokes. The stereopair is formed by two photoelectric converters, transmitted digitally via a multicore cable to the receiving part. In the receiving side, the number of samples per line is doubled from 400 to 800, the number of lines is doubled from 300 to 600, and stereo pairs are reproduced by electron-optical scanning on a matte screen. The perception of the stereo effect by the viewer is carried out through electronically controlled 3D glasses [3, p. 588, 565]. Video information is recorded in a compressed form, its playback is performed by the receiving side. The essence of the claimed system is that in an applied television system containing a transmitting side, including a photoelectric converter of two images, horizontal and vertical scanning units, 1-6 ADCs, a trigger and two keys, and a receiving side, including a frequency synthesizer, three channels of video signals R , G, B, each of which contains a register connected in series, a code processing unit, a first delay unit and an adder, and a second delay unit, 1-6 pulse amplifier units, a radiation modulation unit, a line and frame blocks azvertok, the first amplifier and the first piezoelectric deflector with a reflector at the end, the second amplifier and the second piezoelectric deflector with a reflector at the end, four reference voltage sources, a projection optical system, a matte screen and an IR emitter, 3D glasses with an IR receiver are introduced on the receiving side, codec unit and code storage unit, the transmitting side with the receiving side is connected by a multicore connecting cable.

Functional diagram of the transmitting side - figure 1, the receiving side - figure 2, the scan raster and the shape of the control voltage - figure 3, the ADC of the video signal - figure 4, the design of the piezoelectric deflector - figure 5, the code processing unit - figure 6, the first delay unit - Fig. 7, radiation modulation unit - Fig. 8, summing amplifier-Fig. 9, codec and code storage units - Fig. 10, video compression process diagrams - Fig. 11, encoder circuit - Fig. 12, decoder circuit - Fig.13.

выдают их по сигналу выдачи U_выд, блок 122 производит задержку кодов на 17,5 нс

. Первые блоки 61, 62, 63 задержек идентичны /фиг.7/, каждый содержит элемент И 124, первый 125, второй 126 ключи, первый 127, второй 128 распределители импульсов и восемь регистров 129₁-129₈. Каждый из блоков принимает 800 кодов строки и производит задержку их на длительность строки 33,3 мкс:

. Блок 76 модуляции излучений включает /фиг.8/ первый излучатель 130 трех основных цветов, второй излучатель 131 трех основных цветов R, G, В и оптическую систему 132. Каждый излучатель представляет матрицу из 36 светодиодов, в которую входят 12 светодиодов красного цвета излучения R, 12 зеленого цвета излучения G, 12 синего цвета излучения В. Излучающая плоскость находится в задней фокальной плоскости оптической системы 132, в передней фокальной плоскости которой расположен отражатель первого пьезодефлектора 78. Излучатели через оптическую систему 132, отражатели пьезодефлекторов 78, 82 и проекционную оптическую систему 85 оптически соединены с экраном 86. Суммирующие усилители 22, 91 идентичны, каждый включает /фиг.9/ 10-разрядный счетчик 133 импульсов, дешифратор 134, первый 135, второй 136 ключи, первый 137, второй 138 формирователи импульсов и выходной усилитель 139. Первым информационным входом является первый вход выходного усилителя 139, вторым - счетный вход счетчика 133 импульсов. Управляющим входом является объединенный, вход управляющих входов ключей 135, 136 и управляющий вход счетчика 133 импульсов. Выходом суммирующего усилителя является выход выходного усилителя 139. Инфракрасный /ИК/ излучатель 92 включает импульсный инфракрасный светодиод, вход которого подключен к второму выходу синтезатора 54 частот /50 Гц/, на вход ИК-излучателя поступают импульсы 50 Гц, передний фронт которого соответствует началу развертки первой строки правого кадра в стереопаре. Объемное восприятие изображения с экрана зрителем воспринимается через 3Д-очки с малогабаритным ИК-приемником 94, принимающим сигнал от ИК-излучателя 92 [3, c.563-568]. При воспроизведении на экране последовательно правой и левой частей стереопары стекла очков 3Д-очков поочередно теряют прозрачность, каждый глаз видит только свою часть стереопары, это и дает стереоэффект. Стекла 3Д-очков выполнены по технологии ЖК-ячейки просветного типа, используемые в качестве электронно-управляемых фильтров /затворов/. Прозрачность ЖК-ячеек изменяется синхронно со сменой изображения кадров стереопары. С приходом в ИК-приемник импульсного излучения ИК-приемник первым сигналом затемняет прозрачность ЖК-ячейки в правом стекле на 0,01 с, затем вторым управляющим сигналом затемняет прозрачность ЖК-ячейки в левом стекле на 0,01 с. Блок кодека 95 /фиг.10/ содержит блок 140 компрессии, включающий три кодера 142_1-3, и блок декодера 141, включающий три декодера 143_1-3. Кодеры 142_1-3 идентичны, каждый содержит /фиг.12/ последовательно соединенные регистр 144, схему 145 сравнения /компаратор/, счетчик 146 импульсов, дешифратор 147, блок 148 ключей и блок 150 буферной памяти /флэш-память/, и блок 149 задержек.The transmitting side includes / Fig. 1 / a photoelectric converter 1, which is a video sensor of two images of one object: the right and left, including the first lens 2 / right /, the first piezoelectric reflector 3 with a reflector at the end, located in the rear focal plane of the first lens 2, the first a source of positive reference voltage 4, a second source of 5 negative reference voltage, a first amplifier 6, a second piezoelectric deflector 7, the front end of which has two faces located at an appropriate angle dr angle to each other and with a reflector on each face, the second, amplifier 8, the third source of positive reference voltage 9, the fourth source of negative reference voltage 10, the second lens 11 / left /, the third piezoelectric deflector 12 with a reflector at the end located in the rear focal plane the second lens 11, the third amplifier 13, the fifth source 14 of the positive reference voltage, the sixth source 15 of the negative reference voltage, block 16 line scan from the master oscillator 17 and the output stage 18, block 19 frame time vertices from the And 20 element, the master oscillator 21 and the summing amplifier 22, the first 23 and second 24 dichroic mirrors, the first 25, the second 26, the third 27 micro lenses, the first 28, the second 29, the third 30 photodetectors, the first. 31, second 32, third 33 pre-amplifiers, third 34 and fourth 35 dichroic mirrors, fourth 36, fifth 37, sixth 38 micro lenses, fourth 39, fifth 40, sixth 41 photodetectors, fourth 42, fifth 43 and sixth 44 pre-amplifiers. The photoelectric converter 1 is the main part of the transmitting side / transmitting camera /, which includes the first ADC 45, the second ADC 46, the third ADC 47, the fourth ADC 48, the fifth ADC 49, the sixth ADC 50. The second lens 11 is located to the left of lens 2, optical its axis is parallel to the optical axis of the lens 2, the distance between them corresponds to the optimal stereo effect. The transmitting side includes a trigger 51, the first 52 and the second 53 keys, the receiving side includes a frequency synthesizer 54, a video signal channel R including a series-connected register 55, a code processing unit 58, a first delay unit 61 and an adder 64, and a second a delay unit 65, a video signal channel G including a register 56, a code processing unit 59, a first delay unit 62 and an adder 66, and a second delay unit 67, a video signal channel B including a register 57, a code processing unit 60, a first delay unit 63 and an adder 68, and the second block 69 delays, includes 1-6 bl ki 70, 71, 72, 73, 74, 75 pulse amplifiers, a radiation modulation unit 76, a first amplifier 77 and a first piezoelectric deflector 78 with an end reflector, a first source of positive reference voltage 79, a second source of negative reference voltage 80, a second amplifier 81 and a second piezoelectric deflector 82 with a reflector at the end; a third source of positive reference voltage 83; a fourth source of negative reference voltage 84; a projection optical system 85 and a matte screen 86; a horizontal scanning unit 87 identical to the horizontal scanning unit 16 , a frame scan unit 88, identical to the frame scan unit 19 and including a series-connected element And 89, a driver 90 and a summing amplifier 91, an IR emitter 92, 3D glasses 93 with an IR receiver 94, includes a codec unit 95 and a storage unit 96 codes. The ADCs 45-50 are identical (Fig. 4/), each containing a series-connected video amplifier 97 and a piezo deflector 98 with a reflector at the end, a source of positive reference voltage 99, a source of negative reference voltage 100, an emitter from a pulsed LED 101, aperture diaphragm 102, and a micro lens 103 , line 104 of a multi-element photodetector and encoder 105. All piezoelectric deflectors 3, 7, 12, 78, 82, 98 are end bimorph piezoelectric elements with a light reflector on the free end, structurally executed / Fig. 5/ the same [4, p.1 18] from the first 106 and second 107 piezoelectric plates, the inner electrode 108, the first 109 and second 110 external electrodes. One end of the piezoelectric plates is fixed in the holder 111, a light reflector 112 is located on the free end. The projection optical system 85 includes / Fig. 1 / a spherical mirror in series, in the focal plane of which there is a reflector of the second piezoelectric deflector 82, a flat mirror with an inclination of 45 ° relative to the optical axis a spherical mirror and a corrective lens [1, p.370], a flat mirror allows you to reduce the direct distance in a straight line to the screen and change the direction of the rays. An opaque screen 86 is located in the external focal plane of the projection optical system. The code processing units 58, 59, 60 are identical, each includes a trigger 113, first 114 and second 115 key blocks, first 116, second 117, third 118, fourth 119 registers, fifth 120 and sixth 121 registers, delay block 122, adder 123 and 16 diodes. The information input of the block is the bitwise integrated inputs of the key blocks 114, 115, the control input is the input of the trigger 113, the output is the bitwise combined outputs of the blocks 120, 121, 122 of the delays, the registers 120, 121 perform a code delay of 83 ns

give them out according to the signal U _iss , block 122 delays the codes by 17.5 ns

. The first delay blocks 61, 62, 63 are identical (Fig. 7/), each contains an AND 124 element, the first 125, the second 126 keys, the first 127, the second 128 pulse distributors and eight registers 129 ₁ -129 ₈ . Each of the blocks accepts 800 line codes and delays them for a line duration of 33.3 μs:

. The radiation modulation unit 76 includes / Fig. 8/ the first emitter 130 of the three primary colors, the second emitter 131 of the three primary colors R, G, B and the optical system 132. Each emitter is a matrix of 36 LEDs, which includes 12 red LEDs of the radiation R 12 green emission G, 12 blue emission B. The emitting plane is in the rear focal plane of the optical system 132, in the front focal plane of which is the reflector of the first piezoelectric deflector 78. Emitters through the optical system 132, neg the piezoelectric deflectors 78, 82 and the projection optical system 85 are optically connected to the screen 86. The summing amplifiers 22, 91 are identical, each includes a / 9/10-bit pulse counter 133, decoder 134, first 135, second 136 keys, first 137, second 138 pulse shapers and output amplifier 139. The first information input is the first input of the output amplifier 139, the second is the counting input of the pulse counter 133. The control input is combined, the input of the control inputs of the keys 135, 136 and the control input of the counter 133 pulses. The output of the summing amplifier is the output of the output amplifier 139. The infrared / IR / emitter 92 includes a pulsed infrared LED, the input of which is connected to the second output of the synthesizer 54 frequencies / 50 Hz /, 50 Hz pulses are received at the input of the IR emitter, the leading edge of which corresponds to the beginning of the sweep first line of the right frame in a stereo pair. The volumetric perception of the image from the screen by the viewer is perceived through 3D glasses with a small infrared receiver 94, receiving a signal from an infrared emitter 92 [3, p.563-568]. When the right and left parts of a stereo pair are played on the screen, the glasses of 3D glasses alternately lose transparency, each eye sees only its part of the stereo pair, this gives a stereo effect. The glasses of 3D glasses are made using the technology of the LCD cell of the translucent type, used as electronically controlled filters / shutters /. The transparency of the LCD cells changes synchronously with the change of the image of the frames of the stereo pair. When pulsed radiation arrives at the infrared receiver, the infrared receiver first darkens the transparency of the LCD cell in the right glass for 0.01 s, then the second control signal darkens the transparency of the LCD cell in the left glass for 0.01 s. The codec block 95 / Fig. 10/ contains a compression block 140, including three encoders 142 _1-3 , and a decoder block 141, including three decoders 143 _1-3 . Encoders 142 _{1-3 are} identical, each contains / Fig. 12/ connected in series register 144, comparison circuit 145 / comparator /, pulse counter 146, decoder 147, key block 148 and buffer memory block 150 / flash memory /, and block 149 delays.

The decoders 143 _{1-3 are} identical, each includes / Fig. 13/ connected in series the first register 151, the first, the key block 152 and the second register 153, the second key block 154 connected in series, subtracting the pulse counter 155 and the decoder 156, as well as the first 157 and second 158 keys. Block 96 of the code store / Fig. 10/ includes a drive 159 R codes, a drive 160 G codes, a drive 161 codes B, a first 162, a second 163 and a third 164 keys. The information inputs of block 96 are the inputs of drives 159, 160, 161 of codes R, G, B. The outputs are the outputs of drives 159, 160, 161 of codes R, G, B, the control input is the combined key inputs 162, 163, 164, it is connected to the fourth output of the synthesizer 54 frequencies. A frequency synthesizer 54 implements a coordinated operating procedure for the applied television system and outputs: from the first output, 15 kHz pulses to the first input in the transmitting side / to block 16 / and to the input of the receiver side horizontal scan unit 87, from the second output 50 Hz pulses to the second control input the transmitting side / block 19 /, to the second control input of the vertical scanning unit 88 and to the input of the infrared emitter 92 of the transmitting side, from the third output pulses of 30 kHz to the third control input of the transmitting side, to the first input of block 88 and to the second control the input inputs of the first blocks of 61-63 delays, from the fourth output pulses of 12 MHz to the fourth control input of the transmitting side, to the control input of the codec block 95, to the control input of block 96 of the code store, to the control inputs of registers 55, 56, 57 and to the control inputs blocks 58, 59, 60, from the fifth output pulses of 100 Hz to the fifth control input of the transmitting side and to the first control inputs of the first delay blocks 61-63, from the sixth output pulses of 24 MHz to the control inputs of adders 64, 66, 68 and to the third control the inputs of the first blocks 61-63 delays. The code repetition rate / sampling rate / from the transmitting side to registers 55-57 is:

300 _lines × 100 Hz × 400 _counts = 12 MHz,

where: 300 - the number of encoded lines in the frame,

100 Hz - frame rate,

400 is the number of encoded samples per line.

The photoelectric Converter 1 generates six analog video signals of two images / stereo pair /, which come from the pre-amplifiers 31-33 in the ADC 45, 46, 47, from the pre-amplifiers 42-44 in the ADC 48-50. Photoelectric converter 1 and six ADCs 45-50 are structurally placed in the transmitting television camera / transmitting side /, the output of which is six binary codes of video signals: the right image codes R, G, B and the left image codes R, G, B. The ADC converts analog video signals into 8-bit codes. Alternate issuance of codes with ADC 45-47 and ADC 48-50 is performed by trigger 51 and keys 52, 53. Pulses of 100 Hz from the fifth output of the synthesizer 54 frequencies are fed to the input of trigger 51, the signal from the first output of which opens the key 52, passing through the right frame / 0.01 s / 12 MHz pulses to the ADC 45-47 clock inputs, the codes from which are sent in parallel to the registers 55, 56, 57. The ADC 48, 49, 50 do not issue codes, 12 MHz pulses to their clock inputs do not arrive. With the arrival of the second 100 Hz pulse to trigger 51, the key 52 is closed, the key 53 is opened, which transmits 12 MHz pulses to the ADC clock inputs 48, 49, 50, the codes from which enter the registers 55 during the left frame / 0.01 s / , 56, 57. The ADC 45-47 does not issue codes at this time. Lens 2 / Fig. 1/ creates a right color image in the focal plane in which the reflector of the first piezoelectric deflector 3 is located. The reflector has a width of at least 0.02 mm and a length of at least 6 mm: 0.02 mm × 300 _lines . According to the control voltages (Fig. 3/) from the amplifier 6, the piezoelectric deflector 3 vibrates the end face with the reflector relative to the first reflector at the end of the second piezoelectric deflector 7, scanning a row of the right image. The lens 11 creates a left color image in the focal plane in which the reflector of the third piezoelectric deflector 12 is located. Its reflector has the dimensions of the reflector of the piezoelectric deflector 3. According to the control voltages from the amplifier 13, the piezoelectric deflector 12 vibrates the end face with the reflector relative to the second reflector of the piezoelectric deflector 7, scanning a line of the left image . Block 16 line scan produces a linearly varying voltage output / 3 / in the form of an isosceles triangle. The voltage first increases in proportion to time, the reflectors of piezoelectric deflectors 3 and 12 at a uniform speed synchronously and in-phase rotate from left to right, upon reaching the edge of the raster, the scan voltage decreases in proportion to time, the reflectors return at the same speed. The control voltage period is equal to the duration of two lines, therefore, to build a raster of 300 lines at 100 frames per second, the piezo-deflectors 3 and 12 oscillate with a frequency of 15 kHz, two lines unfold in one oscillation period. Line frequency 30 kHz. line scan line by line, without reverse moves. Block 16 from the master oscillator 17 and the output stage 18. The signal from the amplifier 6/13 / is supplied to the internal electrode 108 of the piezoelectric deflector / Fig.5/, the voltage from the source 4/14 / of the positive reference voltage is applied to the external electrode 109, and to the external electrode 110 voltage is applied from the source 5/15 / of the negative reference voltage, when the control voltage is applied to the internal electrode 108, the piezoelectric plates 106, 107 [4, p.122] are deformed, a bending moment of forces occurs, the end face with the light reflector 112 rotates and deflects vertically single line of the image. Images of two vertical lines are fed to the first and second reflectors of the second piezoelectric deflector 7, which performs vertical scanning / when scanning the frame, the odd / right / frames go down; when the scan is up, even frames / left / go. The width of the reflector of the piezoelectric deflector 7 is not less than 0.02 mm, the length of each is not less than 8 mm: 0.02 mm × 400 _counts . The piezoelectric deflector 7 oscillates at a frequency of 50 Hz, which is 100 frames per second. Frame scan without reverse moves. From the output of the summing amplifier 22/91 /, a linearly varying and stepwise control voltage is output, amplified to the required value by the amplifier 8/81 /. The summing amplifier 22 sums the line voltage from the master oscillator 21/90 / with 30 kHz pulses from block 54. Each pulse of the line moves it at the end of the step by one step in a row / piezoelectric deflector 7 / on both sides, 300 lines are obtained / all active / , one step in two lines with a piezoelectric deflector 82. The purpose of the blocks / Fig. 9/ from 133 to 138 is to send to the second input of the output amplifier 139, at the right time, negative pulses with the right frames and positive pulses with the left frames of the desired amplitude and duration, before the frame scan whitefish cash U ₀ from the element And 20/89 / resets the digits of the counter 133. The 10-bit counter counts the horizontal pulses 30 kHz, the cycle counts 600 pulses. The signal U ₀ opens the first key 135, which transmits horizontal pulses to the input of the first 137 pulse shaper, which generates negative pulses of the corresponding amplitude and duration, and feeds them to the second input of the output amplifier 139. The right-frame sweep / down / follows. With the arrival of the 300th pulse, the decoder 134 provides a signal that closes the key 135, opens the key 136, followed by a sweep of the left frame / up /. Mixed rays reflected from the first reflector of the piezoelectric deflector 7 are directed: red are reflected from the first dichroic mirror 23, collected by the lens 25 into the photodetector 28, blue pass the first dichroic mirror 23, reflected from the second 24 and the lens 26 are collected in the photodetector 29, both pass green the mirrors 23 and 24 and the lens 27 are collected in the photodetector 30. The analog video signals of the right frame from the photodetectors are fed to preamplifiers 31, 32, 33. Rays from the second reflection pass a similar process eating the piezoelectric deflector 7, and the analog video signals of the left frame are fed to the preamplifiers 42, 43, 44. From the preamplifiers the analog video signals are received: the right image to the inputs of the ADC 45, 46, 47, the left image to the inputs of the ADC 48, 49, 50. The ADCs have one principle of conversion, which consists in scanning the beam (Fig. 4/) from the LED 101 by the reflector of the piezoelectric deflector 98 along the plane of the entrance pupils of the photodetectors of the line 104 of the multi-element photodetector. The light pulse is converted into an electrical signal that excites one of the input buses of the encoder 105, which gives a code for the instantaneous value of the input video signal, the conversion is performed with a sampling rate of 12 MHz. The sampling pulses are fed to the input of the LED 101. The slit aperture 102 and the micro lens 103 form a beam with an aperture equal to the size of one input window of the photodetector line 104. A pulsed LED AL402A with a pulse rise time of 25 ns, with a margin satisfying the sampling rate of 12 MHz / 83 ns, is accepted as a radiation source. /. The photodetectors in the line are the avalanche photodiodes of the APD with a response time of 10 ns. Line 104 contains 255 photodetectors for encoding video signals with an 8-bit code. The output of each photodetector is connected to the corresponding input of the encoder 105. The encoder is represented by K155IV1 microcircuits with a response time of 20 ns. The encoder generates codes from 00000001 to 11111111. The first photodetector in line 104 corresponds to the code 00000001, the second to 00000010, the third to 00000011, etc., the 255th to code 11111111. The conversion time is 30 ns, with a margin of 12 MHz / 83 ns /. The ADC 45-47 and the ADC 48-50 issue, alternating, the right and left frames of the stereo pair. Information creation speed 12 MB / s. Codes of the right frame of the stereopair with the ADC 45, 46, 47 in a parallel form coming respectively into the registers 55, 56, 57, of which outputs signals U _vyd in blocks 58, 59, 60 code processing, which are identical and produce a doubling of the number of samples in each row from 400 to 800 obtaining intermediate / average / values of samples between each passing code and the one following it. Blocks perform the addition of the previous and subsequent codes and the division of the sum code in half.

The operation of the block 58/59, 60 /, Fig.6.

The period of the codes in block 58 is 83 ns / 12 MHz /, at the output of block 58 is 41.5 ns / 24 MHz /. Each code is used twice: the first time as the next, the second as the previous. For this, block 58 has four registers 116, 117, 118, 119. Adder 123 adds two 8-bit codes in 24 ns. As an adder, K555IM6 microcircuits were used [5, p. 258] with a response time of 24 ns. When the first 12 MHz pulse arrives at the input of the trigger 113 from its first output, the signal U _vyd1 simultaneously generates a "code 0" from register 118 / when the contents are output, the registers are reset to zero / from register 117. The code "code 0" from register 117 goes to the first inputs adder 123, the code "code 0" from register 118 enters the register 121 and through diodes to the second inputs of the adder 123. The signal U _vyd1 opens the keys in block 114, through which the first code "code 1" enters the registers 116 and 117. In this time adder 123 performs the addition of codes "code 0 + code 0". Dividing the sum of codes by 2 is performed without spending time by dropping the least significant bit in the sum code, similar to dividing the decimal number by ten. To perform the division in this way, the outputs of the adder 123 are connected to the inputs of the delay unit 122 as follows:

adder outputs 123 0 one 2 3 four 5 6 7 8 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ block inputs 122 one 2 3 four 5 6 7 8

следует с блока 58 через 41,5 нс. Код с регистра 118 поступил на хранение в регистр 121, который выполняет хранение "код 0" 83 нс, но первая половина хранения 41,5 нс приходится на сложение в сумматоре и задержку в блоке 122 задержек.Bit 0 means carry bit when the sum of the codes. When doubling the samples in a row from 400 to 800, the code repetition rate corresponds to 24 MHz, the repetition period is 41.5 ns. The addition process takes 24 ns, therefore, the delay unit 122 must delay the code an additional 17.5 ns after the adder 123 / 41.5 ns - 24 ns /. After the adder and block 122 code number 1

follows from block 58 through 41.5 ns. The code from register 118 was stored in register 121, which stores the “code 0” 83 ns, but the first half of the storage 41.5 ns is the addition in the adder and the delay in the delay block 122.

. Одновременно сигнал U_выд2 открывает ключи в блоке 115, и следующий "код 2" поступает в регистры 118, 119. Через блок 114 следуют только нечетные коды, через блок 115 только четные коды. С приходом 3-го импульса в триггер 113 сигнал U_выд3 выдает из регистра 120 "код 1", являющийся кодом №4 и следующий за кодом №3 через 41,5 нс, выдает "код 2" из регистра 118 в регистр 121 и через диоды в сумматор 123 и выдает "код 1" из регистра 117 в сумматор, сигнал U_выд3 открывает ключи в блоке 114, следующий "код 3" поступает в регистры 116, 117. Идет сложение, деление, и код №5

следует с блока 122. С приходом 4-го импульса в триггер 113 сигнал U_выд4 выдает код №6 "код 2" с регистра 121 на выход, выдает с регистра 116 "код 3" в регистр 120 и через диоды в сумматор 123, выдает с регистра 119 "код 2" в сумматор, сигнал U_выд4 открывает ключи в блоке 115, и следующий "код 4" поступает в регистры 118, 119. Идет сложение в сумматоре 123 "код 3 + код 2", деление на 2, и с блока 122 на выход следует код №7

.With the arrival of the second pulse in trigger 113, the signal U _vy2 from its second output generates code No. 2 "code 0" from register 121 to the output of block 58, which follows code No. 1 after 41.5 ns. The signal U _vy2 from the register 116 "code 1" to the register 120 for storage / 83 ns / and through the diodes to the first inputs of the adder 123, generates from the register 119 "code 0" to the second inputs of the adder 123. Addition "code 1 + code 0 ", when exiting from the adder to block 122, dividing by 2, and code No. 3 follows from the output of block 122

. At the same time, the signal U _vy2 opens the keys in block 115, and the next "code 2" enters the registers 118, 119. Only odd codes follow through block 114, only even codes through block 115. With the arrival of the third pulse in trigger 113, the signal U _vy3 generates from the register 120 "code 1", which is code No. 4 and following code No. 3 after 41.5 ns, issues a "code 2" from register 118 to register 121 and through diodes to the adder 123 and generates a "code 1" from register 117 to the adder, the signal U _iss3 opens the keys in block 114, the next "code 3" goes to the registers 116, 117. Addition, division, and code No. 5 are in progress

it follows from block 122. With the arrival of the 4th pulse in trigger 113, the signal U _vy4 generates code No. 6 "code 2" from register 121 to the output, issues from code 116 "code 3" to register 120 and through diodes to adder 123, issues from register 119 "code 2" to the adder, the signal U _vy4 opens the keys in block 115, and the next "code 4" goes to registers 118, 119. Addition is in progress in adder 123 "code 3 + code 2", division by 2, and from block 122 to exit follows code No. 7

.

следует на выход. Одновременно сигнал U_выд5 открывает ключи в блоке 114, "код 5" поступает в регистры 116, 117, и далее процессы повторяются. С блока 58 /59, 60/ удвоенное число отсчетов 800 поступает код за кодом /24 МГц/ на входы второго блока 65 /67, 69/ задержек и на первые входы сумматора 64 /66, 68/. Сумматоры 64, 66, 68 формируют промежуточные строки, выполняя сложение кодов текущей строки с выхода блока 58 с кодами тех же отсчетов прошедшей строки с выхода блока 61, задержанные на длительность строки 83 нс. Сумматоры 64, 66, 68 идентичны сумматорам 123 и выполнены из микросхем К555ИМ6 с временем срабатывания 24 нс. Деление суммы кодов на 2 выполняется также подключением выходов сумматоров 64, 66, 68 к входам своих блоков 70, 72, 74 импульсных усилителей. Блоки 61, 62, 63 участвуют в формировании отсчетов промежуточных строк, задерживая коды на длительность строк /83 мкс/. Так как развертка четных и нечетных строк в растре идет встречно /фиг.7/, то для получения нечетных промежуточных строк необходимо выдавать в сумматор 64 коды в последовательности, начиная с последнего кода /800-го/ в строке к первому, а при получении четных промежуточных строк выдавать коды с блока 61, начиная с первого кода к последнему. При развертке первой строки растра в блоке 61 /62, 63/ открывается ключ 125, импульсы двойной частоты дискретизации 24 МГц поступают в первый распределитель 127 импульсов, выдающий с выхода тактовые импульсы последовательно с первого по 800-й разряды. При развертке 1-й строки кадра регистры 129_1-8 заполняются кодами первой строки. 800 первых разрядов поступают в регистр 129₁, 800 вторых разрядов кодов поступают в регистр 129₂, 800 третьих разрядов кодов поступают в регистр 129₃..., 800 восьмых разрядов кодов поступают в регистр 129₈. Импульс с последнего 800-го выхода блока 127 закрывает ключ 125, открывает ключ 126, и на вход второго распределителя 128 поступают импульсы 24 МГц. Выходы с распределителя 128 импульсов подключены к первым управляющим входам разрядов регистров 129_1-8 в обратном порядке, начиная с 800-го разряда к первому, при развертке второй строки /текущей/ кадра тактовые импульсы с выходов второго распределителя 128 выдают на первые входы сумматора 64 коды задержанной 1-й строки в последовательности с 800-го кода к первому соответственно следованию отсчетов при развертке второй текущей строки, и сумматор 64 формирует первую промежуточную строку. Освобождающиеся разряды регистров 129_1-8 сразу же заполняются отсчетами второй /текущей/ строки в порядке с 800 кода к первому. Импульс с последнего выхода распределителя 128 закрывает ключ 126, открывает ключ 125. Следует развертка 3-й текущей строки, при которой коды второй строки выдаются из регистров 129_1-8 в сумматор 64, начиная с первого кода к 800-у. Сумматор 64 формирует вторую промежуточную строку. Далее процессы, чередуясь, повторяются. Коды с выходов сумматоров 64, 66, 68 являются кодами 300 промежуточных строк. Вторые блоки 65, 67, 69 задержек выполняют задержку кодов текущих строк кадра на время 24 нс на время срабатывания сумматоров 64, 66, 68, чтобы коды текущих и промежуточных строк приходили на входы блоков 70-75 импульсных усилителей синхронно. Блоки импульсных усилителей представляются микросхемами 533АП6 с временем срабатывания 18 нс [5, c.128]. Каждый блок 70-75 имеет по 12 импульсных усилителей. Блок 76 модуляции излучений выполняет яркостную модуляцию излучений двумя излучателями 130, 131 /фиг.8/ соответственно значениям кодов видеосигналов текущих и промежуточных строк, первый излучатель 130 модулированным по яркости лучом воспроизводит 300 текущих строк, кодированных в передающей стороне. Второй излучатель 131 модулированным по яркости лучом воспроизводит 300 промежуточных строк, сформированных сумматорами 64, 66, 68. Воспроизводимый кадр содержит 600 активных строк с 800 отсчетами в каждой, разрешение элементов в кадре 480000. В излучателях применяются светодиоды HLMP компании "Хьюлетт-паккард" [6, c.71]. Для красного излучения приняты светодиоды HLMP-AL00 с силой света 0,4 кд, длиной волны 0,59 мкм при токе 0,02 А, для зеленого излучения приняты светодиоды HLMP-АМ00 с силой света 0,8 кд, длиной волны 0,526 мкм при токе 0,02 А, для синего излучения - светодиоды HLMP-АВ00 с силой света 0,3 кд, длиной волны 0,475 мкм при токе 0,02 А. Суммарное излучение светодиодов трех цветов каждого излучателя смешивается оптической системой 132 при фокусировке в цветовое пятно на отражателе первого пьезодефлектора 78. Яркостная модуляция производится включением на излучение светодиодов в матрице соответственно весу разряда по таблице 1. Распределение светодиодов одного цвета по весам разрядов в таблице 1.With the arrival of the 5th pulse in trigger 113, signal U _vyd5 from the first output of the trigger gives code No. 8 “code 3” from register 120 to the output, issues “code 4” from register 118 to register 121 and to adder 123 and “code 3” from register 117 to the adder. Follows addition, division, and code number 9

should exit. At the same time, the signal U _vyd5 opens the keys in block 114, the "code 5" enters the registers 116, 117, and then the processes are repeated. From block 58/59, 60 / doubled the number of samples 800, the code for the code / 24 MHz is supplied to the inputs of the second block 65/67, 69 / delays and to the first inputs of the adder 64/66, 68 /. Adders 64, 66, 68 form intermediate lines by adding the codes of the current line from the output of block 58 with the codes of the same samples of the past line from the output of block 61, delayed by a line length of 83 ns. Adders 64, 66, 68 are identical to adders 123 and are made of K555IM6 microcircuits with a response time of 24 ns. The division of the sum of codes by 2 is also carried out by connecting the outputs of the adders 64, 66, 68 to the inputs of their blocks 70, 72, 74 of pulse amplifiers. Blocks 61, 62, 63 are involved in the formation of samples of intermediate lines, delaying the codes for the duration of the lines / 83 μs /. Since even and odd lines in the raster are scanned in the opposite direction (Fig. 7/), to obtain odd intermediate lines, it is necessary to output 64 codes to the adder in the sequence starting from the last code / 800th / in the line to the first, and when receiving even intermediate lines give codes from block 61, starting from the first code to the last. When the first line of the raster is scanned in block 61/62, 63 /, the key 125 is opened, the pulses of the double sampling frequency 24 MHz go to the first pulse distributor 127, which outputs clock pulses sequentially from the first to the 800th bits. When scanning the 1st line of the frame, registers 129 _1-8 are filled with the codes of the first line. 800 first digits go to register 129 ₁ , 800 second digits of codes go to register 129 ₂ , 800 third digits of codes go to register 129 ₃ ..., 800 eighth digits of codes go to register 129 ₈ . The pulse from the last 800th output of block 127 closes the key 125, opens the key 126, and 24 MHz pulses arrive at the input of the second distributor 128. The outputs from the 128 pulse distributor are connected to the first control inputs of the bits of the registers 129 _1-8 in the reverse order, starting from the 800th digit to the first, when the second line / current / frame is scanned, the clock pulses from the outputs of the second distributor 128 are output to the first inputs of the adder 64 codes of the delayed 1st row in sequence from the 800th code to the first respectively following samples when the second current row is scanned, and adder 64 forms the first intermediate row. The freed bits of registers 129 _{1-8 are} immediately filled with samples of the second / current / line in the order from 800 code to the first. The pulse from the last output of the distributor 128 closes the key 126, opens the key 125. A scan of the 3rd current line follows, in which the codes of the second line are issued from registers 129 _1-8 to the adder 64, starting from the first code to 800. The adder 64 forms a second intermediate line. Further, the processes, alternating, are repeated. The codes from the outputs of the adders 64, 66, 68 are codes 300 intermediate lines. The second delay blocks 65, 67, 69 perform a delay of the codes of the current frame lines for 24 ns for the response time of the adders 64, 66, 68, so that the codes of the current and intermediate lines arrive at the inputs of the blocks 70-75 of the pulse amplifiers synchronously. Blocks of pulse amplifiers are represented by 533AP6 microcircuits with a response time of 18 ns [5, p. 128]. Each 70-75 unit has 12 pulse amplifiers. The radiation modulation unit 76 performs luminance modulation of the radiation by two emitters 130, 131 (Fig. 8/), respectively, of the codes of the video signals of the current and intermediate lines, the first emitter 130 reproduces 300 current lines encoded in the transmitting side by a modulated beam. The second emitter 131, with a brightness-modulated beam, reproduces 300 intermediate lines formed by adders 64, 66, 68. The reproduced frame contains 600 active lines with 800 samples in each, the resolution of the elements in the frame is 480000. The emitters use HLMP Hewlett-Packard LEDs [ 6, p. 71]. For red radiation, HLMP-AL00 LEDs with a light intensity of 0.4 cd, a wavelength of 0.59 μm at a current of 0.02 A were adopted, for green radiation, HLMP-AM00 LEDs with a light intensity of 0.8 cd, a wavelength of 0.526 μm at at a current of 0.02 A, for blue radiation - HLMP-AB00 LEDs with a light intensity of 0.3 cd, a wavelength of 0.475 μm at a current of 0.02 A. The total emission of the three-color LEDs of each emitter is mixed by the optical system 132 when focusing in a color spot on reflector of the first piezoelectric deflector 78. Luminance modulation is performed by switching on the LEDs atritse discharge weight respectively of Table 1. The distribution of the LEDs of the same color weights discharges in Table 1.

Table 1 Discharge number one 2 3 four 5 6 7 8 in code senior level low order LEDs per discharge four 2 one one one one one one Multiplicity of the filter - - - 2 ^x 4 ^x 8 ^x 16 ^x 32 ^x

The brightness, saturation and hue of the resulting color on the screen is determined by the total energy and the mutual ratio of the three colors R, G, B of the emitter. The resolving element on the reflector of the first piezoelectric deflector adopted 0.02 × 0.02 mm The width of the reflector of the first piezoelectric deflector 78 is not less than 0.04 mm / 0.02 mm × 2 /, length 4 mm / to facilitate alignment /. The resolving element on the reflector of the second piezoelectric deflector 82 adopted 0.03 × 0.03 mm The width of the reflector is at least 0.06 mm / 0.03 mm × 2 /, the length is at least 0.03 mm × 800 = 24 mm.

The magnification of the image enlargement by the projection optical system 85 on the screen 86 is adopted 15 ^x / fold /, while the image size on the screen 86 will be:

horizontal 15 × / 0.03 mm × 800 / = 360 mm,

vertical 15 × / 0.03 mm × 600 / = 270 mm,

Diagonally 450 mm or 17.7 inches.

The total luminous intensity of a single emitter 130/131 /, taking into account that the LEDs of all colors have a light intensity of 0.3 cd blue LEDs, is:

3 × 0.3 cd / 4 + 2 + 1 + 0.5 + 0.25 + 0.125 + 0.0625 + 0.03125 / = 0.9 cd × 7.968 = 7.17 cd

where 3 is the number of colors in the emitter,

0.3 cd - light intensity of the blue LED,

4 ... 0,03125 - coefficients of binary bits in the code.

The attenuation of the radiation force from one emitter in the projection is taken 20 times. The maximum possible brightness of the deploying element with an area of 0.25 mm ² / 0.5 × 0.5 / mm on the screen 86 is:

,

,

where 7.17 cd is the radiation power of one emitter,

20 - the frequency of attenuation of radiation during projection,

0.25 · 10 ^-6 m ² - the area of the deploying light element.

The piezoelectric deflector 78, according to the control voltages from the amplifier 77, performs a horizontal scan of two lines on the reflector of the second piezoelectric deflector 82, which performs a vertical scan in the focal plane of the spherical mirror of the projection optical system 85, which projectes a frame image onto a matte screen with a magnification of 15 ^x 86. Synchronously with the start of scanning the first line of the right frame, the IR emitter 92 emits a pulse of 100 ns duration received by the IR receiver 94 located at the body of 3D glasses 93. With a pulse, the IR receiver emits a control signal lasting 9.9 ms in the LCD cell of the left glass, dimming it for 0.01 s, after which the IR receiver issues a second control signal lasting 9.9 ms in LCD cell of the right glass, dimming its transparency by 0.01 s. Glasses of 3D glasses alternately lose transparency, and each eye sees only its part of the stereo pair, which gives a stereo effect. Codes of color signals R, G, B separately from the ADC 45, 46, 47 / 48-50 / are received in block 95 of the codec / Fig. 10/, in it in compression block 140 for compressing digital video information before writing to block 96 of the code store. Compression unit 140 includes three identical encoders 142 _1-3 , each compressing a 12 MB / s stream of its color signal. The compression method consists of a sequence of the following operations.

1. Comparison of the values of the stream codes in size to determine codes equal in value and following each other.

2. Counting the number of codes, equal in magnitude, starting from the second code of the sequence, and the formation of the binary code of this number.

3. Maintaining the code of the number in the stream after the first code of its sequence.

4. Recording the compressed stream of video data into the buffer memory before issuing them for recording in compressed form.

To restore the video stream during playback, the following operations are performed.

5. Determination in the compressed code stream of a number equal in value to the codes by the presence of a signal in the 9th digit of the code.

6. Decoding code number equals the code to generate a number of signals U _vyd issuing a first code according to the number of seized under compression codes.

7. The definition of the first code of the sequence and its issuance, respectively, to the number of seized codes during compression.

A diagram of the process of compressing a data stream and restoring it before playback in Fig.11. The number of equal successive codes varies, so the compression ratio will be floating. The more equal codes in a row, the higher the compression ratio. At the input of the encoder 142/12 / receives 8-bit codes from the output of the ADC 45 / 46-50 /. The code enters register 144, at the first inputs of the comparison circuit 145, and at the inputs of the delay unit 149. The initial state of the keys in block 148 is open. Block 149 delays the code for 18 ns for the duration of the operation of circuit 145. Through the public keys of block 148, the code enters block 150 of the buffer memory, while there is no signal at the input of the 9th digit, codes from 8 bits. When following unequal-sized codes, the keys of block 148 remain open, the codes go to block 150 of the buffer memory. The comparison circuit 145 compares the magnitude of each previous and each subsequent code to identify their equality. As a comparison circuit 145, two 530SP1 microcircuits with a response time of 18 ns are used [5, p. 279]. Scheme 145, with the inequality of codes A> B, gives a signal at output 2 / in a microcircuit, output 5 / [5, p.272 Fig. 2.190], if the codes A = B are equal, it gives a signal from output 1 / in a microcircuit, output 6 /, and when a <B outputs a signal from the output 3 / output 7 in the chip /, with equal code signal from the output 1 of the circuit 145 closes the keys at block 148, receives a countable pulse on counting 146 pulses of the counter input and the first control register input 144 as a U _vyd signal . The counter 146 counts the pulses while the codes of equal magnitude go in the stream. With the inequality of codes / A> B or A <B / c of circuit 145, a signal from output 2 or 3, which are combined, follows. Signals from these are used as control: U _of the register 144 to zero, U _of keys for opening at block 148, U _vyd code for issuing from the counter 146. When the identification codes equal in magnitude the counter 146 / chip K531IE17P operating time 12 ns [5 , p.156] / produces an account of the number of equal codes. The counter 146 pulses is 8-bit, the maximum code in it is 11111111. When comparing unequal codes, the signal from the output 2/3 / generates a code from the counter 146, opens the keys in block 148 and resets the register 144. The code from the counter is 8-bit, and for identification code from the counter, a signal is added to it in the 9th bit, which arrives with the first pulse in the counter 146 in the ninth bit of block 150. With the appearance of equal but larger codes, the first one goes to block 150 and is the first code in its sequence / diagram 11 figure 11 /. Codes of equal size following it are counted by a counter 146 and excluded from the code stream. Behind the first code of the sequence of equal codes, a code is sent to block 150 from the counter 146 pulses, which is 9-bit in block 150 to identify it during data recovery; when 255 equal codes are followed in succession, the decoder 147, when the code 11111111 issues a signal, resetting the counter 146, resetting register 144, issuing the contents of the counter 146 and opening the keys in block 148. At the input of block 150, the code stream has the form of a diagram 11/11 /. Block 150 of the buffer memory performs the accumulation of codes, storing byte by byte in the memory, diagram 111. From block 150, the compressed code stream is transferred to block 96 of the code store / 10 /. Solid state media, for example, PC Card, xD Picture Card [7, p.328], optical media DUD with a drive [7, p.336] and tape drives [7, p.340] can be used as a code drive in block 96.

The speed of the encoder 142 is determined by the response time of the comparison circuit 145/18 ns /, provides the bandwidth of the encoder 55 MB / s. The volume of the stream to be compressed is 12 MB / s: 300 _lines × 100 Hz × 400 _counts . Encoder 142 provides a stream of compressible video information with a margin. To restore the compressed video information, each color signal has its own decoder 143. The 8-bit code enters the register 151 / Fig. 13/, from which it is issued a signal U _vy / 12 MHz /. The initial state of the keys in block 152 is open, in block 154 is closed. The code through the keys in block 152 enters the register 153, from which they are issued by the signal U _exp1 to the output of the decoder with resetting the register 153. So far, codes from 8 bits are received in the register 151, this process is repeated. With the advent of the register 151 a code of 9-bits signifying the number equals the code signal from the 9th register discharge 151 closes the keys U _z in block 152, opens the U _of keys at block 154, closes the U _of the key 157, opens a U _from the key 158 and closes the key 162 / Fig.10/ in block 96 of the code store. The code of the number of equal codes through the public keys of block 154 enters the subtracting counter 155 pulses. The pulses from the key 158 go to the counting input of the subtracting counter 155 / chip 100IE137 with a response time of 10.5 ns [5, p. 428] / and at the same time comes as a signal U _vy2 to register 153. The signal U _vy2 gives a code from register 153, but Don't reset it. While the counter 155 is working on subtraction, until the code 00000000 appears in it, the same code is issued from register 153. It represents codes seized during video compression. The recovered data stream is shown in diagram IV of FIG. 11. When the code 00000000 is received in the decoder 156, it gives a signal that closes the keys in block 154, opens the keys in block 152, closes the key 158, opens the key 157 and comes from the output 2 of decoder 143/10 / as signal U _from to open the key 162. The signals U _vyd / 12 MHz / resume the issuance of codes from block 159 drive code R in block 143 ₁ . Decoders 143 ₂ , 143 ₃ work identically. To view video data from storage unit 96 codes comprising supplying at its input signals U _vyd 12 MHz from the 4th output synthesizer 54 frequencies. The codes of the three color signals of the same line samples are synchronously transmitted to decoders 143 _1-3 , where the information is restored to its original form and issued to the registers 55, 56, 57. Then the described process of image formation on the screen 86 follows.

System operation.

The photoelectric converter 1 / Fig. 1 / generates six analog video signals of two images, which are fed to the ADC 45-47 / the right image of the stereo pair /, to the ADC 48-50 / the left image of the stereo pair /. The ADCs convert the analog video signals into 8-bit codes, which in parallel form through a multi-core cable of the corresponding length enter the receiving side (Fig. 2/), in which the video signal codes R are sent to register 55, the video signal codes G to register 56, and the video signal codes B - to the register 57. The frame codes of the right and left images follow one after another. The sequence is performed by trigger 51 and keys 52, 53 / Fig. 1/, from which clock signals are fed in an odd frame to the control inputs of the ADC 45-47, in an even frame to the ADC 48-50.

From registers 55-57, the codes are sent in parallel to blocks 58-60 / Fig. 2/, which double the samples in a row from 400 to 800, then the adders 64, 66, 68 form intermediate lines, doubling the number of lines in a frame from 300 to 600. Codes of current and intermediate lines are simultaneously sent to their blocks 71, 73, 75 and 70, 72, 74 of pulse amplifiers. The code signals in them are amplified to the required value, and are fed to power the corresponding LEDs in the first 130 and second 131 emitters / Fig.8/. The emitters translate the code values into the luminance modulation of the LED emissions. The lens 132 focuses the radiation of two emitters on the reflector of the piezoelectric deflector 78/2 /, simultaneously scans two lines (current and intermediate) on the reflector of the second piezoelectric deflector 82, which performs a vertical scan of the image in the focal plane of the spherical mirror of the projection optical system 85, which projects the image of the frame with increasing ^x 15 on the screen 86. The screen 86 right and left images alternately follow one another at 0.01 to 50 times a second right frame picture 50 times per second images Agen left frame. The viewer perceives the three-dimensional image through 3D glasses 93/2 /, the glass of which is darkened in accordance with the projected image of the stereo pair on the screen. With the right frame, the left glass of glasses is darkened on the screen, with the left - the right one. The dimming of the glasses is performed by the LCD cells according to the control signals from the IR receiver 94 located on the glasses, which generates control signals from the IR pulses from the IR emitter 92. In parallel, the video information codes are fed to the inputs of the codec block 95 (Fig. 2/).

Three encoders 142 separately by color signals compress the video information, which is recorded on the block 96. To view the video information on the control input of the block 96, signals _Ud 12 MHz are supplied. From block 96, the information in compressed form enters block 141 decoders. Decoders 143 _1-3 restore information to its original form. From decoders 143, the codes enter the registers 55-57 / Fig. 2/, followed by the processes of doubling samples and doubling the lines, converting the code values into the luminous radiation of the emitters 130, 131, scanning the frame in two lines at the same time, projecting a 15- ^x image frame onto the screen 86. The transmitting side is connected to the receiving multicore cable, in which 5 lines of control signals / 15 kHz, 50 Hz, 30 kHz, 12 MHz, 100 Hz / and 24 information lines: 8 lines × 3 / from the ADC 45, 46, 47 / . The inventive system can be used for external and internal observations in everyday life, industry, in the army for driving armored vehicles with the driver's inspection hatch closed in a three-dimensional image of the space on the screen.

Sources of Information

1. V.F. Samoilov, B.P. Khromoi. The television. M., 1975, p. 367, 370, 384.

2. Patent No. 2246801, cl. H 04 N 15/00, bull. 5, 2005, prototype.

3. Kolesnichenko OV, Shishigin OV PC hardware. 5th edition, St. Petersburg., 2004, p. 588, 563, 565.

4. Fridland M.V., Soshnikov V.G. Automatic control systems in video recording devices. M., 1988, p. 118 fig. 5.5, fig. 5.10, p. 122.

5. Digital integrated circuits. Minsk, 1991, p. 128, 156, 258, 272, 279, 428.

6. Radio, No. 7, 1998, p. 71.

7. V.I. Murakhovsky. Computer device. M., 2003, p. 328, 336, 340.

Claims (1)

An applied television system containing a transmitting side including a photoelectric converter, 1-6 ADCs, the inputs of which are connected to the corresponding outputs of the photoelectric converter, a trigger, the first and second keys, the output of the first key is connected to the clock inputs 1-3 of the ADC, the output of the second key is connected to clock inputs 4-6 of the ADC, the first control input of the first key and the second control input of the second key are connected to the first output of the trigger, the second control input of the first key and the first control input of the second cha are connected to the second output of the trigger, a horizontal scan unit from a serially connected master oscillator and an output stage, a frame scan unit from a series-connected element And, a master oscillator and a summing amplifier, the second input of which is connected to the first input of the And element, the control input of the summing amplifier is connected to the output of the element And, the first and second inputs of the element And are the inputs of the frame scanning unit, the photoelectric converter contains a first lens, a first piezoelectric a torus with a reflector at the end located in the focal plane of the first lens, a second piezoelectric deflector, the free end of which of two faces at an appropriate angle to each other and a reflector on each face contains a second lens and a third piezoelectric reflector at the end, located in the focal plane of the second lens and optically connected to the second reflector of the second piezoelectric deflector, to the first reflector of which the reflector of the first piezoelectric deflector is optically connected, the first antenna is connected in series a starter, whose input is connected to the output of the horizontal scanning unit, and the first piezoelectric deflector, the first source of positive reference voltage, the output of which is connected to the second inputs of the first amplifier and the first piezoelectric deflector, the second source of negative reference voltage, the output of which is connected to the third inputs of the first amplifier and the first piezoelectric deflector connected in series to a second amplifier, the input of which is connected to the output of the vertical scanning unit, and a second piezoelectric deflector, a third source of positive reference voltage, the output of which is connected to the second inputs of the second amplifier and the second piezoelectric deflector, a fourth source of negative reference voltage, the output of which is connected to the third inputs of the second amplifier and the second piezoelectric deflector, a third amplifier connected in series, the input of which is connected to the output of the horizontal scanning unit, and the third piezoelectric deflector , the fifth source of positive reference voltage, the output of which is connected to the second inputs of the third amplifier and the third piezoelectric deflector, the sixth source is negative The reference voltage, the output of which is connected to the third inputs of the third amplifier and the third piezoelectric deflector, contains the first and second dichroic mirrors located one after the other and against the first reflector of the second piezoelectric deflector, 1-3 micro lenses, 1-3 photodetectors, 1-3 preliminary amplifiers, the outputs of which are the outputs of the photoelectric converter and are connected to the inputs of 1-3 ADCs respectively, the input window of the first photodetector is optically connected through the first micro lens and the first dichroic mirror with as the first reflector of the second piezoelectric deflector, the input window of the second photodetector is optically connected through the second micro-lens and through both dichroic mirrors to the first reflector of the second piezoelectric reflector, the input window of the third photodetector is optically connected through the third micro-lens, the second dichroic mirror and through the first dichroic mirror to the first reflector of the second piezoelectric deflector and the fourth dichroic mirror, located one after another and against the second reflector of the second piezoelectric deflector, 4-6 micro lenses, 4-6 photodetectors, 4-6 preamplifiers, the outputs of which are the outputs of the photoelectric converter and are connected to the inputs of a 4-6 ADC, the input window of the fourth photodetector is optically connected through the fourth micro lens and the third dichroic mirror with the second reflector of the second piezoelectric deflector, the input window of the fifth photodetector is optically connected through the fifth micro lens and through both dichroic mirrors with the second reflector of the second piezoelectric deflector, the input window of the sixth photodetector is optically connected о through the sixth micro-lens, the fourth dichroic mirror and through the third dichroic mirror with the second reflector of the second piezoelectric deflector, the outputs of 4-6 photodetectors are connected respectively to the inputs of 4-6 pre-amplifiers, the outputs of which are connected to the inputs of 4-6 ADCs respectively, the summing amplifier of the frame scan unit includes a pulse counter and a decoder connected in series, first and second keys, first and second pulse shapers and an output amplifier, signal inputs of keys and a counting input counter and the pulses are combined and are the second input of the summing amplifier, the first input of which is the first input of the output amplifier, the first control input of the first key, the second control input of the second key and the control input of the pulse counter are combined and are the control input of the summing amplifier, the second control input of the first key and the first the control input of the second key is combined and connected to the output of the decoder, the output of the first key is connected to the input of the first pulse shaper, the output of the second key is connected is input to the second driver, the outputs of the pulse shapers are combined and connected to the second input of the output amplifier, the output of which is the output of the summing amplifier, 1-6 ADCs are identical, the outputs 1 and 4, 2 and 5, 3 and 6 of the ADC are combined and are, respectively, 1-3 outputs of the transmitting side, while each ADC includes a series-connected video amplifier and a piezoelectric deflector with a reflector at the end, a source of positive reference voltage, the output of which is connected to the second inputs of the video amplifier and piezoelectric deflector, sources negative reference voltage, the output of which is connected to the third inputs of the video amplifier and piezoelectric deflector, an emitter from a pulsed LED, a slit diaphragm, and a micro lens, a multi-element photodetector line, and an encoder, the outputs of which are ADC outputs, the ADC input is a pulse LED input, and contains the receiving side, including the receiving side three identical channels of video signals R, G, B, each of which contains a register connected in series, a code processing unit, a first delay unit and a sum a torus, and a second delay block, the inputs of which are connected to the outputs of the code processing block, to which the first inputs of the adder are connected, the second inputs of which are connected to the outputs of the first delay block, includes 1-6 blocks of pulse amplifiers, the inputs of the first three blocks of pulse amplifiers are connected to the outputs of the respective adders, the inputs of the second three blocks of pulse amplifiers are connected to the outputs of the corresponding second blocks of delays, the radiation modulation block, the inputs of which are connected to the outputs of six blocks of pulse amplifiers leu, serially connected horizontal scanning unit identical to the horizontal scanning unit of the transmitting side, the first amplifier and the first piezoelectric deflector with a reflector at the end, the first source of positive reference voltage, the output of which is connected to the second inputs of the first amplifier and the first piezoelectric deflector, the second source of negative reference voltage, output which is connected to the third inputs of the first amplifier and the first piezoelectric deflector, connected in series frame scan unit, identical to the frame block scanning of the transmitting side, the second amplifier and the second piezoelectric deflector with a reflector at the end, the third source of positive reference voltage, the output of which is connected to the second inputs of the second amplifier and the second piezoelectric deflector, the fourth source of negative reference voltage, the output of which is connected to the third inputs of the second amplifier and the second piezoelectric deflector, includes a projection optical system containing a spherical mirror arranged in series, in the focal plane of which a reflector is located in of the second piezoelectric deflector, a flat mirror with an angle of 45 ° relative to the optical axis of the spherical mirror and a corrective lens, in the external focal plane of the projection optical system there is a matte screen, which is optically connected to the radiating side of the radiation modulation unit through the projection optical system, reflectors of the second and first piezoelectric reflectors, block code processing includes a trigger, the input of which is the control input of the block, 1-4 registers, fifth and sixth registers, delay block, 16 diodes and the adder, the control input of which is connected to the input of the trigger, the first output of which is connected to the control inputs of the second, third, fifth registers, the second output of the trigger is connected to the control inputs of the first, fourth and sixth registers, the output of the first register is connected to the inputs of the fifth register and through diodes to the first inputs the adder, the outputs of the second register are connected to the first inputs of the adder, the outputs of the third register are connected to the inputs of the sixth register and through diodes to the second inputs of the adder, the outputs of the fourth register are connected the second inputs of the adder, the outputs of which are connected to the inputs of the delay unit, the outputs of which are bitwise combined with the outputs of the fifth and sixth registers and are the outputs of the code processing unit, the first delay unit includes an And element connected in series with the first switch and the first pulse distributor, the second switch and the second distributor pulses, and eight registers, the information inputs are: 1-8 inputs of the first block of delays connected to the second (information) inputs of the bits, respectively: the first input is parallel of bits to second inputs of the first register, a second input in parallel to the second inputs of the second register bits. . . , the eighth input is parallel to the second inputs of the bits of the eighth register, the output of the first delay block is 1-8 combined outputs of the bits of each of 1-8 registers, the first and second control inputs are the first and second inputs of the element And, the output of which is connected to the first control input of the first key and the second control input of the second key, the signal inputs of the first and second keys are combined and are the third control input of the first block of delays, the outputs of the first pulse distributor are sequentially connected They are connected to the first (clock) inputs from the first to the last (800th) bits of 1-8 registers, the last output is connected to the second control input of the first key, to the first control input of the second key and through the diode is connected to the first inputs of the last bits 1-8 registers, the outputs of the second pulse distributor are connected, starting from the last output to the first, to the first (clock) inputs of bits 1-8 of the registers, the last (800th) output through a diode is connected to the first inputs of the first bits of 1-8 registers and is connected through a diode to the first control input p of the first key and to the second control input of the second key, the radiation modulation unit contains the first and second emitters of three primary colors and an optical system, each of the emitters includes 36 LEDs of 12 LEDs of each of the three colors R, G, B, the inputs of the emitters are connected to the outputs of the corresponding blocks of pulse amplifiers, the outputs of the emitters through the optical system are optically connected to the reflector of the first piezoelectric deflector, includes an IR emitter and a frequency synthesizer, characterized in that the outputs of the frequency synthesizer are sub obtained: the first output is connected to the first input of the transmitting side and to the input of the horizontal scanning unit of the receiving side, the second output is to the second input of the transmitting side, to the infrared emitter and to the second input of the vertical scanning unit of the receiving side, the third output is to the third input of the transmitting side to the second control inputs of the first delay blocks and to the first input of the receive side frame scan unit, the fourth output to the fourth input of the transmitting side, to the control inputs of the channel registers of the video signals R, G, B, to the control inputs odes of the code processing blocks, to the control inputs of the codec block and the drive side code storage block, the fifth output to the fifth input of the transmitting side, to the first control inputs of the first delay block of the receiving side, the sixth to the third control inputs of the first delay blocks and to the control inputs of the receive adders side, 1-3 outputs of the transmitting side through diodes are connected to the inputs of the channel registers of the video signals R, G, In the receiving side, the inputs and outputs of the receiving side are connected to the outputs and inputs of the transmitting side cable, on the receiving side a codec block, a code storage block and 3D glasses with an IR receiver on the spectacle frame are inserted, the codec block includes a compression block including the first, second, third encoders, and a decoder block including the first, second, third decoders , the information inputs of 1-3 encoders are connected respectively to the first, second, third outputs of the transmitting side, the outputs of 1-3 decoders are connected to the inputs of the corresponding channel registers of the video signals R, G, B, the control inputs of the decoders are combined and connected to the fourth output synt frequency jam, the code storage unit includes the first key and the code store R, the second key and the code store G, the third key and the code store B, the information inputs of the code stores R, G, B are connected to the outputs of the corresponding encoders in the codec block, the outputs of the drives codes R, G, B are connected to the information inputs of the respective decoders in the codec block, the first and second control inputs of the first, second and third keys are connected respectively to the first and second control outputs of the first, second and t There are three decoders in the codec block, the signal inputs of the keys are combined and connected to the fourth output of the frequency synthesizer, 1-3 encoders are identical, each includes a series-connected register, a comparison circuit, a pulse counter and a decoder, series-connected delay block, a key block and a buffer memory block, information inputs of the register, the first information comparison circuits and the inputs of the delay block are bitwise combined and are information inputs of the encoder, the second information inputs of the comparison circuit are connected to register outputs, the first output of the comparison circuit is connected in parallel to the counting input of the pulse counter and to the 9th input of the buffer memory block, to 1-8 inputs of which are connected 1-8 outputs of the key block, the first output of the comparison circuit is connected to the first control input of the register and the second control input of the key block, the second and third outputs of the comparison circuit are combined and connected to the second control input of the register, the first control input of the key block and the first control input of the pulse counter, 1-8 outputs of the pulse counter connected to the inputs of the decoder and through diodes to 1-8 inputs of the buffer memory block, the decoder output is connected to the second control input of the pulse counter and through the diode to the first control input of the key block, 1-9 outputs of the buffer memory block are encoder outputs, 1-3 decoders identical, each includes series-connected first register, 1-9 inputs of which are information inputs of the decoder, first block of keys and second register, 1-8 outputs of which are outputs of decoder, series-connected second block of key her, a subtracting pulse counter and a decoder, the first and second keys, the decoder control input is the combined control input of the first register and the signal inputs of the first and second keys, 1-8 outputs of the first register are connected in parallel to the inputs of the first and second block of keys, 9th output the first register is connected to the first control input of the second key, to the second control input of the first key, to the first control input of the second block of keys, and to the second control input of the first block of keys and is the first control the decoder output, the decoder output is connected to the first control input of the first key, to the second control input of the second key, to the first control input of the first key block, to the second control input of the second key block and is the second control output of the decoder, the output of the first key is connected to the first control the input of the second register, the output of the second key is connected to the second control input of the second register and to the counting input of the subtracting pulse counter, the first and the second key blocks, the inputs of which are bitwise combined and are the information input of the code processing block, the outputs of the first key block are connected to the inputs of the first and second registers, the outputs of the second key block are connected to the inputs of the third and fourth registers, the control input of the first key block is connected to the first output of the trigger , the control input of the second block of keys is connected to the second output of the trigger.

Images