RU2246799C1 - Stereo television system - Google Patents

Abstract

FIELD: radio communications engineering.

SUBSTANCE: proposed system designed for use in digital telecasting by ground television networks within ultrahigh frequency band and over satellite communication systems has sending and receiving ends. Novelty is introduction of second photoelectric converter, three video signal analog-to-digital converters, second audio signal analog-to-digital converter, three code shapers, pulse counter, flip-flop, two switches, and two channels in radio signal transmitter on sending, end as well as second and third video signal code reception and processing channels, second audio channel, radiator, and separate frame viewing unit on receiving end. Effective frequency band is 356 Hz, clock frequency, 54 MHz, line repetition frequency, 31.25 kHz, frame repetition frequency, 50 Hz; raster scanning is progressive.

EFFECT: provision for stereo effect in viewing television programs.

1 cl, 16 dwg, 1 tbl

Description

The invention relates to radio communications technology and can be used for broadcasting in the decimeter range of terrestrial TV networks.

The prototype adopted a digital television system [1], containing on the transmitting side a photoelectric converter, three ADCs of a video signal, an ADC of a sound signal, a sinusoidal oscillation generator, a frequency divider, a self-propelled pulse distributor, a group signal shaper, a radio signal transmitter including a carrier frequency generator, amplitude-connected a modulator and an output amplifier, at the receiving side comprising an antenna, a touch control unit, a path for receiving and processing video signal codes, switching unit for receiving a radio signal, radio frequency amplifier, bipolar amplitude detector, first and second pulse generators, luminance signal channel, channels of the first and second color-difference signals, each of which includes keys, four registers, four blocks of delay elements, three triggers, an adder and a digital-to-analog converter (DAC), includes a sound channel, including two keys, two register blocks and a DAC, a channel for generating control signals, including a sequentially connected line sync selection block pulse generator, a sampling pulse generator and a self-propelling pulse distributor and a series-connected key, a pulse counter, a decoder, a pulse shaper and a trigger, and containing a video amplifier, a sync pulse selector, a horizontal and vertical scanning unit, a color picture tube, a decoding matrix, three output video amplifiers of the primary colors R, G, B, sound box and loudspeaker. The information of the codes of the brightness signal Е _у and two color-difference signals Е _Ry , Е _в-у is transmitted on one radio channel by the upper side frequency of the carrier frequency. At the receiving side, a radio signal is received, amplified, detected, unit symbols in codes are converted from half-sine waves to pulses, video signal codes are distributed over the channels of the luminance signal and two color-difference signals, the number of samples per line is doubled, the codes are converted into analog video signals, and a color image is reproduced with a color picture tube. The disadvantage of the prototype is the lack of a stereoscopic image in the system.

The aim of the invention is to create conditions for a stereoscopic effect on the transmitting side and reproducing it on the receiving side.

The technical result of the claimed system is to obtain on the transmitting side two images of the same object from two different positions and playing them with a tube on the receiving side. Technical parameters of the system in table 1.

The transmitting side generates three streams of codes of alternately right and left images of one object, following each other after 0.02 s, the frequency of each image is 25 frames per second, the total frequency is 50 frames per second. Two carrier frequencies are used. The transmission of the video signal codes E _RП (image from the right photoelectric converter) and Е _RЛ (image from the left photoelectric converter) is performed by the upper side frequency of the first carrier, codes E _GP and E _GL are _transmitted by the upper side frequency of the second carrier, transmission of codes E _VP and E _VL performed by the lower lateral frequency of the first carrier. The sampling frequency of video signals is 13.5 MHz. Information on the color tone is carried by the side frequency of the carrier, and on the color brightness is the code of the amplitude of the video signal. The color saturation is set by the spectral band of the phosphors used in the picture tube on the receiving side. Sound codes are transmitted two codes at the end of each line. The line frequency is 31.25 kHz, the frame rate is 50 Hz, including 25 frames of the right image and 25 frames of the left image, alternating one after another. The number of lines in the frame is 625, the line scan in the frame is line-by-line. Line duration 32 μs, blanking frame duration 750 μs, active lines in frame 601. The receiving side receives three radio signals with three paths for receiving and processing video signal codes, detects them, converts unit symbols from half-sine waves to pulses, extracts horizontal and frame sync pulses, doubles the number encoded samples in a line from 432 to 864, converts the codes of video signals into analog video signals and reproduces, with a color tube, the right and left images of one object, observed by the viewer, alternately azdelno: right - the right eye,

Technical parameter Value Note Transmission side Color coding 2: 2: 2 E _R , E _G , E _B Range used 480-790 MHz Carrier frequencies (option) 540 MHz, 648 MHz 5410, 5412 Transmitting Video Signal Codes E_RP, E_RL
E_GP, E_GL
E_VP, E_VL 594 MHz
702 MHz
486 MHz upper side f₁
upper side f₂
bottom side f₁ System Clock 54 MHz

·8625 50

·8 Occupied band on air 356.4 Hz Number of lines / number of frames 625/50 Hz Line scan in frame line by line Total encoded samples per line 432 864: 2 The number of samples of each color 360 720: 2 Video Sampling 13.5 MHz 31.25 × 432 Following codes on the air 6.75 MHz Line scan 31.25 kHz 625 × 50 Line length 32 μs 1: 31.25 kHz Coding method separate, linear PCM Quantization levels of the video signal 255 levels, 8 bits 2 ⁸ Sequence code length 148 ns Audio Sampling 62.5 kHz 31.25 × 2 Sound coding 65536 level, 2 ¹⁶ 16 bit Information transfer rate 324 Mbps 108 × 3 Receiving side Color coding 4: 4: 4 E _R , E _G , E _B Number of lines / number of frames 625/50 Hz Coded samples per line 864 432 × 2 The number of samples of each color 720 360 × 2 Video Signal Code Frequency 27 MHz 13.5 × 2 Information playback speed 648 Mbps 324 × 2 Frame resolution 432,000 ale. 720 × 600 Frame format 1.2: 1 720: 600

left - with the left eye, the frequency of which 25 times per second.

The essence of the claimed system is that in a stereo television system containing a photoelectric converter on the transmitting side, three ADCs of a video signal, ADC of a sound signal, a sinusoidal oscillation generator, a frequency divider, a self-propelled pulse distributor, a radio signal transmitter from one channel including a carrier frequency generator connected in series, an amplitude modulator and an output amplifier, on the receiving side including an antenna, a touch control unit, a first path for receiving and processing video signal codes alov, containing a radio signal receiving unit, a radio frequency amplifier, a bipolar amplitude detector, a first and second pulse shaper, including three DACs, a control signal generation channel containing a horizontal sync pulse allocation unit and a key in series, a pulse counter and a decoder, a sound channel containing two keys , two blocks of registers and a DAC, and including a series-connected video amplifier, a clock selector, a horizontal and vertical scan unit, and a color picture tube, three output signals the primary color amplifier R, G, B, a sound unit and a loudspeaker, a second photoelectric converter, a fourth, fifth and sixth ADC of a video signal, a second ADC of a sound signal, three code drivers, a second self-propelled pulse distributor, a pulse counter, a trigger and two keys, a second channel from a series-connected carrier frequency generator, an amplitude modulator and an output amplifier is inserted into the radio signal transmitter, a third channel from amplitudes connected in series of a tedious modulator and an output amplifier, on the receiving side, a video signal processing channel E _R containing the first and second video signal registers E _R and a code processing unit is entered in the first path for receiving and processing video signal codes, a second channel for receiving and processing video signal codes containing a series-connected block is introduced receiving a radio signal, a radio frequency amplifier and a bipolar amplitude detector, the first and second pulse shapers, and codes the video signal processing channel E _G, comprising first and second registers ve eosignala E _G and the block code processing, entered the third path for receiving and processing video code comprising a series-connected unit receiving the radio signal, the radio frequency amplifier and a bipolar amplitude detector, the first and second pulse shapers and code channel for processing a video signal _EV comprising first and second registers video E _B and a code processing unit, a frequency synthesizer and a frame sync extraction block are introduced into the control signal generation channel, a second sound channel from two keys, two blocks of registers and DACs, a second sound accompaniment unit and a second loudspeaker, and an emitter and a unit for separate observation of frames are introduced.

The block diagram of the transmitting side in figure 1, the structure of digital streams in figure 2, the ADC of the video signal in figure 3, the ADC of the video signal E _In figure 4, the design of the piezoelectric deflector in figure 5, the ADC of the sound signal in figure 6, the code generator the video signal Е _R (Е _G ) in Fig. 7, the encoder of the video signal Е _В in Fig. 8, the block diagram of the receiving side in Fig. 9, the circuit diagram of the bipolar amplitude detector in Fig. 10, the block for extracting the horizontal sync pulse of the SSI in Fig. 11 , CSI frame sync selection block in FIG. 12, code processing block in FIG. 13, the unit for separate observation of frames in Fig. 14, the frequency spectrum of the signals of the transmitter in Fig. 15, timing diagrams of the operation of the system in Fig. 16.

The transmitting side includes (Fig. 1) a first photoelectric converter 1, which is a sensor of three video signals of primary colors R, G, B in the right image E _RP , E _GP , E _BP , a second photoelectric converter 2, which is a sensor of three video signals E _RL , E _GL E _{VL of the} left image of the same object. The lens of the photoelectric transducer 2 is located to the left of the lens of the photoelectric transducer 1, the optical axes of the lenses are parallel, the distance between them corresponds to the optimal stereoscopic effect. The transmitting side includes the first ADC 3 (video signal E _RP ), the second ADC 4 (video signal E _GP ), the third ADC 5 (video signal E _VP ), the fourth ADC 6 (video signal E _RL ), the fifth ADC 7 (video signal E _GL ), the sixth ADC 8 (video signal E _VL ), the first ADC 9 sound signal (E _Sv1 ), the second ADC 10 sound signal (E _Sv2 ), a sinusoidal oscillation generator 11 and a frequency divider 12 connected in series, the first shaper 13 codes (video signals E _RP and E _RL ) , the second shaper 14 codes (video signals E _GP and E _GL ), the third shaper 15 codes (video signals E _VP and E _VL ), p the first self-propelled distributor of 16 pulses, the second self-propelled distributor of 17 pulses, a pulse counter 18, a trigger 19, a first key 20 and a second key 21, a radio signal transmitter 22 including three channels. The first channel includes a series-connected generator of the first carrier frequency, an amplitude modulator 24 and an output amplifier 25, the second channel includes a generator 28 of a second carrier frequency, an amplitude modulator 29 and an output amplifier 30, the third channel includes an amplitude modulator 26 and an output amplifier 27. Each of the amplitude modulators 24, 26, 29 includes a series-connected ring modulator that suppresses the carrier frequency, and a band-pass filter that filters out the unnecessary side frequency in the amplitude-modulated spectrum signal [2, p.234].

The ADCs 3, 4, 6, 7 are identical (Fig. 3), each includes a series-connected video amplifier 31 and a piezoelectric deflector 32 with a light reflector at the end, the first source of positive reference voltage 33, the second source of negative reference voltage 34, an emitter including a pulsed LED 35, the slotted aperture 36 and the lens 37, the line 38 of the multi-element photodetector and encoder 39. All piezoelectric deflectors 32 (42, 61) are end bimorph piezoelectric elements with a light reflector at the end, structurally made (figure 5) one ovo [3, p.118] 50 of the first and second piezoelectric plates 51, 52 of the first inner electrode 53 and second external electrodes 54. One end of the piezoelectric plates is fixed in the holder 55, at the free end there is a light reflector 56.

The ADCs 5 and 8 are identical (Fig. 4), each includes a series-connected video amplifier 40, a summing amplifier 41, to the second input of which a synchronization signal E _SI , a piezoelectric deflector 42 with a light reflector at the end, the first source of positive reference voltage 43, the second source 44 of a negative reference voltage, an emitter comprising a pulsed LED 45, a slit aperture 46, and a lens 47, an array 48 of a multi-element photodetector, and an encoder 49.

The ADCs 9, 10 are identical (Fig. 6), each containing a serially connected controlled voltage divider 57, a key block 58, a matching amplifier 59, an audio frequency amplifier 60 and a piezo deflector 61 with a light reflector at the end, the first source of positive reference voltage 62, the second a negative reference voltage source 63, an emitter from a pulsed LED 64, a slit aperture 65 and a lens 66, a multi-element photodetector line 67, a first decoder 68, an encoder 69, a second decoder 70, connected in series e counter 71 pulses, the third decoder 72 and the block 73 registers.

The first 13 and second 14 code generators are performed identically (Fig. 7), each of which includes a trigger 74 and a switching unit 75 and four channels connected in series. The first channel includes a series-connected block of 76 AND elements, the first 77, the second 78 OR elements and the first output switch 79, and the first self-propelled pulse distributor 80, the second channel includes a second block 81 of the AND elements, the third 82 and the fourth 83 OR elements and the second output key 84, and a second self-propelled pulse distributor 85, the third channel includes a third block of 86 AND elements, a fifth OR element 87 and a third self-propelled pulse distributor 88, the fourth channel includes a fourth block of 89 AND elements, a sixth OR element 90 and a fourth self-propelled 91 pulse distributor. The code generator includes the first 92 and second 93 keys and the pulse counter 94 and the decoder 95 connected in series. In the first code generator 13, the decoder 95 has first and second outputs connected to the corresponding key control inputs 92, 93. In the second code generator 14, the decoder 95 has and a third output, which is the second output of the code generator 14. The first and second information inputs of the shapers 13, 14 are the inputs of the switching unit 75 and the inputs of the blocks 86, 89 of AND elements, the third and fourth information inputs are the third inputs of the second 78 and fourth 83 OR elements, the control inputs are: the first is the trigger input 74, the second - combined inputs of the counter 94 pulses, keys 92, 93, the third - the signal inputs of the output keys 79, 84, the fourth - the control input of the counter 94 pulses. The output is the combined outputs of the output keys, in the second shaper 14 the second output is the third output of the decoder 95. The third shaper 15 codes (Fig. 8) contains a trigger 74, a switching unit 75 and two channels. The first channel includes series-connected the first block of 76 AND elements, the first 77, the second 78 OR elements and the output switch 79, and the first self-propelled pulse distributor 80, the second channel includes the second block 81 of the AND elements, the third 82, the fourth 83 OR elements and the output key 84 , and a second self-propelled distributor of 85 pulses. The first information input is the inputs of the switching unit 75, the second and third information inputs are the second inputs of the second 78 and fourth 83 OR elements. The first control input is the trigger input 74, the second is the combined input of the self-propelled distributors 80, 85 pulses, the third is the signal inputs of the output keys 79, 84. The output is the combined outputs of the output keys 79, 84. The receiving side (Fig. 9) is a digital television receiver comprises an antenna, a sensor control unit 96, first, second and third paths for receiving and processing video signal codes, a channel for generating control signals and two channels for an audio signal. The first path for the reception and processing of codes of video signals receives and processes the codes of video signals E _RP and E _RL , includes a series-connected radio signal receiving unit 97, a radio frequency amplifier 98 and a bipolar amplitude detector 99, a first 100, a second 101 pulse shaper and a channel for processing video signal codes E _R including the first 102, the second 103 registers of the video signal E _R , the processing unit 104 codes and the first DAC 105. The second path for receiving and processing codes of video signals receives and processes the codes of video signals E _GP and E _GL , including includes a series-connected radio signal reception unit 106, a radio frequency amplifier 107 and a bipolar amplitude detector 108, a first 109, a second 110 pulse shapers and a video signal processing channel E _G , including the first 111 and second 112 video signal registers E _G , the code processing unit 113 and the second DAC 114. The third path for the reception and processing of codes of video signals receives and processes the codes of video signals E _VP and E _VL , includes a series-connected radio signal receiving unit 115, a radio frequency amplifier 116 and bipolar amplitude first detector 117, the first 118, second 119 pulses conditioners and video processing channel code _EV, including a first 120, second 121 video registers _EV, code processing unit 122 and the third DAC 123.

The first channel of the audio signal includes the first 124, second 125 keys, the first 126, the second 127 register blocks, the DAC 128, the audio block 129 and the speaker 130. The second channel of the audio signal includes the first 131, second 132 keys, the first 133, the second 134 register blocks , DAC 135, sound accompaniment block 136 and speaker 137.

The coordinated operating procedure of the receiving side determines the control signal generation channel, which contains a horizontal sync pulse allocation block (SSI) 138, a frequency synthesizer 139, a key 140, a pulse counter 141, a decoder 142, and a frame clock (PSI) block 143. The receiving side includes a radiator 144, a block 145 for separate observation of frames, a series-connected video amplifier 146, a clock selector 147, a line and frame scan unit 148 and a color picture tube 149, and output video amplifiers 150, 151, 152 of video signals of three primary colors, respectively, U _R , U _G , U _At. Block 138 selection horizontal clock (11) includes the first 153, second 154, third 155 pulse counters, the first 156, second 157 elements And, the first 158, second 159, third 160 elements NOT and a diode. The information inputs of the block are the counting inputs of the pulse counters. The output is the output of the second element And 157. With the arrival of the three codes 11111111 to the information inputs, an SSI horizontal sync pulse appears at the output of block 138, their frequency is 31.25 kHz.

Block 243 selection frame synchronization (Fig) contains the first 161, second 162, third 163 pulse counters, the first 164, second 165, third 166 elements And, the first 167, second 168, third 169 elements NOT and a diode. The information inputs of the block are the counting inputs of the pulse counters and the second input of the And 166 element. With the arrival of the three codes 11111111 and the horizontal clock from the block 138 at the output of the block 138, a frame sync pulse of the CSI appears, it corresponds to the 432th count in the last line of each even frame , the frequency of the CSI is 25 Hz.

Blocks 104, 113, 122 of the code processing are identical, each includes (FIG. 13) trigger 170, first 171, second 172, third 173, fourth 174 registers, first 175, second 176, third 177 delay element blocks, fifth 178, sixth 179 registers, adder 180 and 16 diodes. Block 175 delays the codes by 10 ns, block 176 delays the codes by 84 ns (74 ns + 10 ns), block 177 by 13 ns (37 ns - 20 ns). The registers 178, 179 store 37 ns codes and issue them with the arrival of the output signal in parallel. The first and second information inputs of the code processing unit are the inputs of the blocks 175, 176 delay elements, the output is the combined outputs of the block 177 delay elements, the fifth 178 and the sixth 179 registers. The control input is the input of the trigger 170 and the combined control input of the adder 180.

The emitter 144 includes a pulse shaper connected in series (in duration and amplitude) and a pulsed infrared LED, the output window of which is the output of the emitter 144, the input is the input of the pulse shaper. Block 145 for separate observation of frames (Fig. 14) includes a infrared photodetector 181 connected in series, a pulse shaper 182, a pulse generator 183 that generates control pulses with a frequency of 50 Hz for a duration of 1 ms, and a piezoelectric motor 184. The piezoelectric motor 184 performs control pulses with generator 18Z shaft rotations with a resolution of 90 °. Two cylindrical frames 185 are fixed on the shaft, in which two neutral filters 186 made of nets are fixed. Each filter 186 occupies one fourth of the cylindrical surface of the frame 185. The filters 186 are arranged in a cylindrical frame against each other through 180 ° C. A piezoelectric motor 184 with a shaft with cylindrical frames 185 is mounted on the outside of the case of glasses 187 having right and left eye windows with transparent glasses in them (for eye safety). Right and left cylindrical frames 185 with neutral light filters 186 are located against the eye windows of the glasses. When viewing the program, glasses 187 are put on the eyes. With a single turn of the rim 185, the neutral filters 186 overlap the eye window twice, i.e. through 180 °. The position of the filters in the right frame relative to them in the left frame is offset by 90 °. The multiplicity of one filter is 2 ^x ; when the window is overlapped, their multiplicity is added up to 4 ^x .

The photodetector 181, the pulse shaper 182 and the pulse generator 183 are placed in a separate housing, which when viewing the gears is located by the input window of the photodetector 181 opposite the radiating side of the emitter 144 and from the viewer at a distance of the length of the connecting wires. Like the lenses of the first 1 and second 2 photoelectric converters on the transmitting side, the viewer's eyes observe on the kinescope screen 149 images of the same object from different positions, receiving a stereoscopic effect [4, p. 389]. Each eye observes its image 25 times per second; the duration of one observation interval is 0.02 s. The piezoelectric motor [5, p.40] rotates the shaft in 90 ° increments, the excitation voltage is 5 V, the current consumption is 0.1 A, the start time is 0.001 s (1 ms), the mass is 10 g, and the noise level is no more than 20 dB. For each control pulse from the generator 183, the piezoelectric motor 184 rotates the frames 185 with neutral filters by 90 °, alternately opening one eye window and closing the other with light filters. The overlap frequency is 25 Hz. The shaft rotation frequency is 12.5 r / s. To reduce the influence of inertia on the operation of moving parts, the shaft, cylindrical frames are made of light and durable materials, neutral filters are made of grids.

The clock frequency in the system is:

×8 разр=54 МГц,625 × 50 Hz ×

× 8 bits = 54 MHz,

where: 625 - the number of lines in the frame,

50 Hz - frame rate, 625 × 50 = 31.25 kHz line frequency,

– число пар отсчетов в строке при двухполярной передаче кодов, фиг.2,

- the number of pairs of samples in a row with bipolar transmission of codes, figure 2,

8 _bits - the number of bits in the code.

Photoelectric converter 1 generates three analog video signals of the right image E _RP , E _GP , E _VP , photoelectric converter 2 generates three analog video signals of the left image of the same object E _RL , E _GL , E _VL . The video signals from the outputs of the first photoelectric converter 1 are fed to the inputs of the ADC 3, 4, 5, the video signals from the outputs of the second photoelectric converter 2 are sent to the inputs of the ADC 6, 7, 8. Both photoelectric converters 1, 2 and six ADCs 3-8 are structurally placed in the transmitting the camera, the output of which is six binary codes of video signals: three from the right image (E _RP , E _GP , E _VP ), three from the left image (E _RL , E _GL , E _VL ). ADCs convert analog video signals to 8-bit codes. Alternate output of video signals from photoelectric converter 1 with ADC 3, 4, 5 and from photoelectric converter 2 with ADC 6, 7, 8 is performed by trigger 19 and keys 20, 21. Pulses of 50 Hz from the 7th output of frequency divider 12 are fed to the trigger input 19, the signal from the first output of which opens the first key 20, which transmits 13.5 MHz pulses to the clock inputs of the ADC 3, 4, 5, the codes of which during the first (odd) frame arrive at the drivers 13, 14, 15 of the codes. The ADCs 5, 7, 8 do not issue codes during this frame; 13.5 MHz control pulses do not arrive at their clock inputs. With the arrival of the second 50 Hz pulse to trigger 19, the key 20 closes, the key 21 opens, which passes 13.5 MHz pulses to the ADC 6, 7, 8 clock inputs, the codes from which enter the shapers 13 during the duration of the second (even) frame, 14, 15 codes. The ADC 3, 4, 5 in this frame do not issue codes, 13.5 MHz pulses do not arrive at their clock inputs. Shapers 13, 14, 15 codes convert parallel codes of video signals and sound into sequential ones and replace the representation of units in codes from pulses with positive and negative half-sinusoids of a monofrequency of 54 MHz from a frequency divider 12. The master oscillator 11 generates sine waves with a stability of 10 ^-7 . The frequency divider 12 generates signals from the frequency of the master oscillator 11 and issues: 13.5 MHz pulses from the first output to the ADC 3-8 clock inputs via keys 20, 21 and to the first control inputs of the code drivers 13, 14, 15, and pulses from the second output 6.75 MHz to the second control inputs of the shapers 13, 14, 15 codes and to the first control inputs of the ADC 9, 10, from the third - sinusoidal oscillations of 54 MHz to the third control inputs of the shapers 13, 14, 15 codes, from the fourth - pulses 31, 25 kHz to the fourth control inputs of the shapers 13, 14, 15 codes and to the third branching inputs of the ADC 9, 10, from the fifth - pulses of 25 Hz to the control input of the counter 18 pulses, from the sixth - pulses of 62.5 kHz to the second control inputs of the ADC 9, 10, from the seventh - pulses of 50 Hz to the input of the trigger 19 and from the eighth output - sinusoidal oscillations of 54 MHz to the inputs of the generators 23 and 28 of the carrier frequencies.

ACC 9, 10 convert the sound signals supplied to their inputs into 16-bit codes, which are fed to the second information inputs of the code formers 13, 14. A self-propelled distributor of 16 pulses with the arrival of a start signal U _P from the second output, the code generators 14 (at the moment 215 of the line sampling pulse) generates a code of eight units 11111111, which is the horizontal sync pulse code (431 counts of each line), to the third information inputs of the formers 13, 14 and to the second information input of the shaper 15 codes. A self-propelled distributor of 17 pulses with the arrival of U _P a start signal from the second output of the 18 pulse counter produces a code 11111111, which is a frame sync pulse code (432 counts of the last line of each even frame) to the fourth information inputs of the code generators 13, 14 and to the third information input of the code generator 15 . The pulse counter 18 is a two-bit one, it generates a start signal U _P from the second discharge (output 2) for the self-propelled distributor of 17 pulses with the arrival of the second pulse (215 sampling pulse of the line of the last line of the even frame) at the second output of the code generator 14. Generators 23, 28 of the carrier frequencies are frequency multipliers. 54 MHz sinusoidal oscillations from the eighth output of the frequency divider 12 are supplied to their inputs. In generator 23, the frequency of 54 MHz is multiplied by 10, the first carrier frequency of 540 MHz. In generator 28, the frequency of 54 MHz is multiplied by 12, the second carrier frequency of 648 MHz. The spectrum of the amplitude-modulated signal (Fig. 15) consists of a carrier and two side frequencies. One of the side frequencies and the carrier in the information sense are redundant. In each amplitude modulator 24, 26, 29, the carrier frequency is suppressed [2, p.234] and one of the side frequencies is filtered out. The amplitude modulator 24 outputs to the output amplifier 25 an upper side frequency of 594 MHz from the first carrier frequency of 540 MHz. Amplitude modulator 26 provides a lower side frequency of 486 MHz from the first carrier. Amplitude modulator 29 provides an upper side frequency of 702 MHz from a second carrier frequency of 648 MHz.

The receiving side receives three radio signals, amplifies them, detects half-sine waves on the basis of polarity, separates the detected codes by channels, selects horizontal and frame sync pulses, generates two carrier frequencies, separates the codes of audio signals, doubles the number of samples in each line, converts the codes video signals and sound into analog signals, reproduces alternately right and left images and stereo audio accompaniment. ADCs 3-8 have one conversion principle, which consists in scanning (Fig. 3) the beam from the LED 35 along the plane of the entrance pupils of the photodetectors of the line 38, the light pulse is converted into an electrical signal that excites one of the input buses of the encoder 39, which gives the code of the instantaneous value of the input video signal. The conversion is performed with a sampling rate of 13.5 MHz, the sampling pulses are fed to the input of the LED 35 from block 12. The slit aperture 36 and the lens 37 form a beam with an aperture equal to the size of the input window of the photodetector line 38. A pulsed LED AL402A with a pulse rise time of 25 ns is accepted as a radiation source , with a margin satisfying 13.5 MHz sampling (74 ns).

The photodetectors in line 38 are the avalanche photodiodes of the APD with a response time of 10 ns. Line 38 includes 255 photodetectors for encoding video signals with an 8-bit code. The output of each photodetector is connected to the corresponding input of the encoder 39. The encoder is represented by K155IV1 microcircuits with a response time of 20 ns [6, p.231]. The encoder generates codes from 00000001 to 11111111. The first photodetector of line 38 corresponds to code 00000001, the second to code 00000010, the third to code 00000011, etc., the 255th to code 11111111. The conversion time is 30 ns (10 ns + 20 ns) or 33 · 10 ⁶ prev / s, with a margin satisfying the frequency of 13.5 MHz (74 ns). Information creation speed by each ADC:

13.5 MHz × 8 _bits = 108 Mbps,

The ADC 9, 10 (Fig.6) convert two sound signals into 16-bit codes. 3a, the time of one line of the ADC generates two sound codes, a sampling rate of 62.5 kHz (31.25 kHz × 2). To obtain codes with 16 bits, the transfer coefficient of the voltage divider 57 is changed. Divider 57 is a seven-step resistive divider. Block 58 of the keys has seven keys for connecting the corresponding stage of the divider to the matching amplifier 59, which is an emitter follower. Line 67 of a multi-element photodetector contains 1024 photodetectors and converts the sound signal into a 10-bit code, 2 ¹⁰ . The resolution is adopted at 10 μV, the coding range of only the 67 line is 0–0.01024 V. Converting signals exceeding 2 ¹⁰ into the code is performed by the first decoder 68, encoder 69, second decoder 70, voltage divider 57 and key block 58. With their application, the coding range of sound signals is 0 - 0.65536 V, i.e. 2 ¹⁶ . The pulse from each photodetector enters the decoder 68, from it to the encoder 69. If there is no signal at the input of the divider 57, the code from the zeros comes to the input of the second decoder 70, the signal from the first output of the decoder 70 opens the first key in block 58, determining the transmission coefficient 1 , 0. When the signal reaches the value of code 2 ¹⁰ , a signal appears on the second output of the second decoder 70, which opens the second key in block 58 and closes the first key, the coefficient becomes 0.5, with code 2 ¹¹ - coefficient 0.25, with code 2 ¹² - 0.125, when code -0.0625 February ^13, when the code -0.03125 February ^14, when the code -0.015625 February ^15, which remains to code ^{16 February.} With a decrease in the amplitude of the input signal, the reverse process follows as the transmission coefficient increases. Units in codes are represented by the presence of an impulse, zeros by their absence. During one line, the encoder 69 issues two codes entering block 73, which contains two 16-bit registers. In the process of receipt, the codes are shifted from register to register by pulses U _SD shift. In block 73, two 16-bit codes are accumulated, which are sent one after the other at the end of each line (at the moments of line sampling pulses 214, 215) to the first 13, second 14 code generators.

The output signals come from the two outputs of the third decoder 72. The output signals form a counter 71 pulses and the third decoder 72. The counter 71 is 8-bit, keeps a score of 6.75 MHz, the cycle count 216 pulses. The counter is reset to the leading edge of the pulse U _{0 of} the line frequency of 31.25 kHz at the time of the 216 pulse of the line sampling.

The first _driver 13 codes per frame gives the codes of the video signals E _RP (E _RL ), two sound codes, a horizontal sync pulse code and, in the last line (625) of each even frame 432, a frame sync pulse code, FIG. 2. Units in codes of odd samples of a line are represented by positive half-sine waves, units in codes of even samples of a line are represented by negative half-sines of a monofrequency of 54 MHz with a stability of 10 ^-7 . The second shaper 14 codes gives the codes of the video signals E _GP (E _GL ), two sound codes, a horizontal sync pulse code, and the CSI code (432 counts) in 625 lines of an even frame. Units in the codes of odd samples are represented by positive half-sine waves, units in codes of even samples of a line are represented by negative half-sines, zeros - by the absence of both of them. The third code generator 15 provides for the frame the video signal codes E _VP (E _VL ), the SSI code and the CSI code, the representation of units in the codes is similar to that in the shapers 13, 14. The difference between the shaper 15 codes: from 361 to 430 samples in each row, it gives codes of synchronization signals E _SI , applied to the second inputs of the ADC 5 and 8.

The operation of the generator 14 (13) codes, Fig.7.

Codes with ADCs 4, 7 (3, 6) are sent in parallel with a frequency of 13.5 MHz to the inputs of a switching unit 75, branching a stream of codes 13.5 MHz into two at 6.75 MHz: the first stream of codes is odd samples of the line, the second code stream - even samples. Block 75 includes four K176KE1 microcircuits, which are 4-channel switches with a response time of 25 ns [7, p. 222]. The outputs of the first two microcircuits are connected to the first inputs of the AND elements of block 76, the outputs of the other two microcircuits are connected to the first inputs of the AND elements of block 81. A channel 74 is connected to the outputs of the block 75 by a trigger 74, at the input of which 13.5 MHz pulses are received. Eight pulses from the first 80 and second 85 self-propelled pulse distributors having eight bits each receive sequentially to the second inputs of the elements And blocks 76, 81, the starting pulses U _P for them are 6.75 MHz pulses. From the outputs of the AND elements of blocks 76, 81, the pulses of the codes through the OR elements 77, 78 and 82, 83 open the output keys 79, 84 for the duration of the clock period of 18.5 ns (10 ⁹ ns: 54 MHz). To the signal inputs of the output keys 54 MHz mono-frequency sinusoids arrive. The first output switch 79 in the open state passes the positive half-sine wave, the second output key 84 in the open state passes the negative half-sine wave. At the output of the code generator, the units in the codes of the odd samples of the lines are represented by positive half-sines, in the codes of the even samples of the lines are represented by negative half-sines. Zeros appear to be the absence of both. The output signal at the output of the code generator is either full sine waves of a monofrequency of 54 MHz, or partial sine waves of the same frequency. These signals modulate the carrier frequency. From the driver 13 codes modulate the first carrier frequency in block 24, from the driver 14 codes the second carrier frequency in block 29 of the transmitter 22. Timing diagrams of this process in Fig.16. The sound code consists of two parcels of 8 bits each. The first half of the code 1-8 bits goes to the first inputs of the AND elements of block 86 and through the OR elements 87, 78 goes to the input of the first key 79, the second half of the sound code 9-16 bits goes to the first inputs of the AND elements of block 89 and through the OR elements 90 , 83 goes to the input of the second output key 84. The keys 92, 93 are designed to separate the codes of video signals from sound codes. The key 92 is opened by the signal from the first input of the decoder 95 at the time 216 of the line sampling pulse (samples 431, 432 of FIG. 2) and remains open from 1 to 424 line samples.

At the moment 213 of the line sampling pulse, the signal from the second output of the decoder 95 closes the key 92, opens the key 93. Two sound codes are input to the outputs of the output keys 79, 84.

At the moment 215 of the sampling pulse, the line from the third output of the decoder 95 in the shaper 14 codes the pulse that is the start signal U _П for the self-propelled distributor 16 pulses, which gives the code 11111111 SSI, coming to the third inputs of the element OR 78 in the shapers 13, 14 and the second input element OR 78 in the shaper 15 codes. With the last line (625) in an even frame, the second self-propelled distributor 17 issues at the moment 432 of the line count the frame sync pulse code KSI 11111111 to the third inputs of the OR elements 83 in the drivers 13, 14 and the second input of the OR element 83 in the driver 15 codes. The signal U _P for starting the self-propelled distributor of 17 pulses gives a two-bit counter 18 pulses, the counting cycle, two pulses from the third output of the decoder 95 in the shaper 14 codes. The counter 18 is reset to zero by a 25 Hz pulse, then it receives two pulses from the second output of the code generator 14, the output signal from the output of the second discharge of the counter 18 is a start signal U _П for the self-propelled pulse distributor 17. The first counting pulse is the end of the odd frame, the second counting pulse is the end of the even frame. The process of the third shaper 15 codes is similar to the work of the shapers 13 and 14 codes and simpler, it does not have a process for generating sound codes (Fig. 8).

The first channel of the transmitter 22 of the radio signals emits an upper side frequency of 594 MHz from the first carrier of 540 MHz with information of the codes E _RP and E _RL , with the stability of the master oscillator 11 in 10 ^{-7 the} occupied band on the air is ± 59.4 Hz, i.e. 118.8 Hz. The second channel of the transmitter emits an upper side frequency of 702 MHz from the second carrier frequency of 648 MHz with information of the video signal codes E _GP and E _GL , which occupies the band of ± 70.2 Hz or 140.4 Hz. The third channel emits a lower side frequency of 486 MHz from the first carrier frequency with information, video signal codes E _VP and E _VL , which occupies the broadcast band ± 48.6 Hz, i.e. 97.2 Hz. In total, the occupied band on the air is 356.4 Hz. The transmitted frequency is received on a single antenna. Three radio signals arrive at the antenna of the receiving side, Fig.9. The radio signals are received by blocks 97, 106, 115, which are selectors of the decimeter-band channels / CDS / with electronic tuning, and receive radio signals in the range of 480-790 MHz. Each unit includes an input circuit, an radio frequency amplifier, and a mixer / VT2 / is used from the frequency converter [8, p.132, Fig. 4.2]. The band-pass filter of the radio frequency amplifier in each range is tuned by applying bias voltage to the varicaps from the electronic switch of the touch control unit 96, which is a program selection unit, for example, USU-1-15 [8, p. 86]. The amplified radio frequency signal through the communication loop [8, p.132] is fed to the mixer emitter / VT2 /, and the corresponding frequency equal to the carrier on the transmitting side, necessary for detecting a single-band signal [9, p.146], is supplied from the frequency synthesizer 139. The local oscillator circuit and the IF filter available in SKD-24 [8, Fig. 4.2] are not needed. The signal from the VT2 collector, which is the output signal of block 97 (106, 115), is fed to the input of the radio frequency amplifier 98 (207, 116), where it is amplified to the required value and fed to the input of the bipolar amplitude detector 99 (108, 117). The second inputs of the synthesizer 139 frequencies are connected to the second group of block 96 (after the diodes D11-D18 [8, p. 86]). When a transmission channel is turned on, the voltage of the corresponding diode determines the output of two frequencies to the third inputs of blocks 97 (first carrier frequency, output 5 of block 139), 115 (first carrier frequency) and block 106 (second carrier frequency, output 6 of block 139). Bipolar amplitude detectors 99, 108, 117 are made according to the scheme in figure 10. Diode D1 emits a positive envelope (Fig. 16) of the modulating signal. D2 diode from the modulating one selects envelopes of positive half-sine waves (unit symbols in codes of odd samples of a line), diode D3 from a modulating one selects envelopes of negative half-sinusoids (unit symbols of codes of even samples of a line). From the first output of the bipolar amplitude detector, the detected positive half-sine waves of a frequency of 54 MHz are fed to the input of the first pulse shaper 100 (109, 118), and from the second output, the detected negative half-sine waves are fed to the input of the second pulse shaper 101 (110, 119). The pulse shapers are made according to the scheme of an asymmetric trigger with emitter coupling [10, p.209], which form rectangular pulses from harmonically changing signals. The pulses from the formers have one polarity and a duration equal to the pulse duration in the codes on the transmitting side. Units in the codes are represented by the presence of an impulse, zeros by their absence. After turning on the power of the receiving side, the keys are in the closed state. The operating procedure of the receiving side is determined by control signals from the channel for generating control signals. The decisive role belongs to block 138 allocation of the horizontal clock. The condition for issuing the SSI from block 138 is the simultaneous arrival of three code pulses from eight units into it from three shapers 100, 109, 118 (11111111). In all codes of the line, except for the 431st reference, one or more zeros will be present, especially in the codes of three lines at the same time. For each zero in the code, the NOT elements (Fig. 11) will reset all counters in block 138. With the arrival of three codes 11111111, block 138 will give out an SSI pulse, their frequency is 31.25 kHz. SSI opens the key 140, enters the 4th input of block 143 and the first input of the frequency synthesizer 139.

The frequency synchronization in block 139 is performed based on the SSI pulse. Own frequency stability of the synthesizer 139 frequencies 10 ^-6 , the frequency of the synthesizer 139 is adjusted to the frequency and phase of the master oscillator of the transmitting side by the leading edge of the SSI pulse from block 138. The synthesizer 139 generates pulses 6 from the first output , 75 MHz discretization of the line, 54 MHz clock pulses from the second output, 62.5 kHz pulses from the third output - sound codes from blocks 126, 127, 133, 134 registers, from the fourth - 13.5 MHz pulses to the control inputs of the blocks 104, 113, 122 processing of codes from the fifth and sixth outputs — sinusoidal oscillations of the required first and second carrier frequencies to the third inputs of blocks 97, 106, 115. The odd code of the video signal E _R from the output of the pulse shaper 100 is received in serial form in the first register 102 of the video signal E _R , filling in the bits of which, the code becomes parallel. The code of the even reference of the video signal E _R from the output of the driver 101 is supplied to the second register 103, filling its bits, it becomes parallel. A similar process is tested codes E _G, filling register 111, video 112 E _G, E _B and the codes by filling registers 120, 121 a video signal _EV. The issuance of codes from the registers to blocks 104, 113, 122 of the code processing is performed by 6.75 MHz pulses; they also reset the bits of the registers when they are issued. The processing units 104, 123, 122 of the codes work identically, doubling the number of samples in each row by obtaining the average (intermediate) values of the samples between each passing code and the next one. Each block performs the addition of two codes of the previous and subsequent and dividing the sum code in half.

The operation of the code processing unit 104 (113, 122), FIG. 13. Odd codes from the first register 102 through the block 175 delay elements (10 ns) are sent in parallel to the register 171, 172. Chetnik codes from the second register 103 through the block 176 delay elements (84 ns) are sent in parallel to the register 173, 174. Each code is used twice : first time as previous, second time as next, so four registers 171-174 are used. With the arrival of the first 13.5 MHz pulse to the input of the trigger 170, the pulse U _vy1 from the first output of the trigger gives the code 0 _k from register 172 to the adder 180 and the code 0 _k (codes from one zeros) from register 173, which is fed through the diodes to the adder 180 and directly into the sixth register 179, which stores the code 74 ns. 10 ns after the issuance of the code from register 172, the registers 171 and 172 are filled with the following I _k code coming from block 175, which delayed the code by 10 ns to prevent the incoming code from being superimposed on the issued code. The adder 180 performs the addition of codes 0 _to +0 _to . As an adder, K555IM6 microcircuits with an addition time of 24 ns were used [6 p. 258]. Upon completion of addition, the pulse U ₀ 13.5 MHz gives the sum code to the block 177 delay elements (13 ns) and resets the adder circuit 180. Division by two is performed by shifting the sum code by one bit so that the least significant bit of the sum code is discarded, as when dividing decimal to ten. A shift by one bit is performed when issuing the code from the adder 180 to block 177 by a corresponding connection of the outputs of the adder and the inputs of block 177:

adder outputs 0 1 2 3 4 5 6 7 8 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ inputs of block 177 1 2 3 4 5 6 7 8

, следует с блока 177 в ЦАП 105. С приходом второго импульса 13,5 МГц в триггер 170 импульс U_выд2 со второго выхода триггера выдает код №2 “0_к” из регистра 179. Код №2 следует через 37 нс за кодом №1. Половина времени задержки кода регистром 179, т.е. 37 нс из 74 нс, приходится на процесс сложения в сумматоре 180 и задержку в блоке 177. На входы блоков 175, 176 коды поступают одновременно. Блок 176 выполняет задержку кода на 84 нс: 74 нс воспроизводит следование четного кода за нечетным и 10 нс - для исключения наложения поступающего кода на выдаваемый. Вслед за выдачей кода 0_к из регистра 174 регистры 173, 174 заполняются следующим кодом 2_к с блока 176. В это же время сумматор 180 производит сложение 0_к+1_к, при выдаче кода суммы в блок 177 следует деление на два, и код №3

идет на выход в ЦАП 105. С приходом третьего импульса в триггер 170 сигнал U_выд3 с первого выхода триггера 170 выдает из регистра 178 код №4 1_к, следующий за кодом №3 через 37 нс, с регистра 173 код 2_к в регистр 179 и через диоды в сумматор 180 и код 1_к из регистра 172 в сумматор.bit 0 means transfer to it when adding codes. The process of obtaining an intermediate (average) value of the code is illustrated in Fig.13. When doubling the number of row samples from 432 to 864 (27 MHz), the period of the samples is 37 ns. Addition takes 24 ns; therefore, block 177 must delay the code by 13 ns (37 ns - 24 ns). After addition and division, the intermediate code, which is code No. 1

follows from block 177 in the DAC 105. With the arrival of the second 13.5 MHz pulse into the trigger 170, the pulse U _vy2 from the second output of the trigger issues code No. 2 “0 _k ” from register 179. Code No. 2 follows after 37 ns for code No. 1 . Half the code delay time by register 179, i.e. 37 ns out of 74 ns, accounted for the addition process in the adder 180 and the delay in block 177. At the inputs of blocks 175, 176, the codes arrive simultaneously. Block 176 performs a code delay of 84 ns: 74 ns reproduces the following even code after the odd one and 10 ns to eliminate the overlap of the incoming code on the issued code. Following the issuance of the code 0 _k from register 174, the registers 173, 174 are filled with the following code 2 _k from block 176. At the same time, adder 180 adds 0 _k + 1 _k , when the sum code is sent to block 177, a division by two follows, and the code No. 3

goes to the DAC 105. With the arrival of the third pulse in the trigger 170, the signal U _exp3 from the first output of the trigger 170 gives the code No. 4 1 _k from the register 178, followed by the code No. 3 after 37 ns, from the register 173 the code 2 _k to the register 179 and through diodes to the adder 180 and code 1 _k from register 172 to the adder.

следует на выход в ЦАП 105. С приходом четвертого импульса в триггер 170 сигнал U_выд4 с триггера выдает код №6 2_к из регистра 179, код 2_к из регистра 174 в сумматор 180, регистры 173, 174 заполняются кодом 4_к, из регистра 171 код 3_к в регистр 178 и через диоды в сумматор 180. Следует сложение 2_к + 3_к, деление на два и код №47

следует в ЦАП 105. С приходом пятого импульса в триггер 170 сигнал U_выд5 выдает из регистра 178 код №8 3_к, код 3_к из регистра 172 в сумматор, из регистра 173 код 4_к в регистр 179 и через диоды в сумматор 180. Следует сложение 3_к+4_к, деление на два и выход кода №9

в цап 105. С приходом 6-го и последующих импульсов в триггер 170 процессы повторяются. С выходов блоков 104, 113, 122 коды с частотой 27 МГц поступают в ЦАП соответственно 105, 114, 123, каждый из которых преобразует коды удвоенных отсчетов строки в аналоговые видеосигналы соответственно Е_RП и Е_RЛ, Е_GП и Е_GЛ, Е_ВП и Е_ВЛ. Аналоговые видеосигналы Е_RП и Е_RЛ поступают в выходной видеоусилитель 150, Е_GП и Е_GЛ - в выходной видеоусилитель 151, Е_ВП и Е_ВЛ - в выходной видеоусилитель 152. Три видеосигнала основных цветов поочередно правого и левого изображений после усиления поступают на модуляторы цветного кинескопа 149. Одновременно видеосигналы Е_ВП, Е_ВЛ и Е_СИ поступают в видеоусилитель 146, с него в селектор 147 синхроимпульсов, выделяющий импульсы строк и кадров, поступающие в блок 148 строчной и кадровой разверток. Сигналы разветок поступают на соответствующие входы кинескопа 149, обеспечивая развертку кадра цветного изображения.Registers 171, 172 are filled with a 3 _k code, the adder performs an addition of 1 _k + 2 _k , then there is a division by two, and code No. 5

it should be output to the DAC 105. With the arrival of the fourth pulse in trigger 170, signal U _vy4 from the trigger gives code No. 6 2 _k from register 179, code 2 _k from register 174 to adder 180, registers 173, 174 are filled with 4 _k , from register 171 code 3 _k to register 178 and through diodes to the adder 180. Addition is 2 _k + 3 _k , division by two and code No. 47

it follows in the DAC 105. With the arrival of the fifth pulse in trigger 170, the signal U _vyd5 generates code No. 8 3 _k from register 178, code 3 _k from register 172 to the adder, code _{17 k} from register 173 _to register 179 and through diodes to adder 180. It follows the addition of 3 _to +4 _k , division by two and the output of code No. 9

in DAC 105. With the arrival of the 6th and subsequent pulses in the trigger 170 processes are repeated. From the outputs of blocks 104, 113, 122, codes with a frequency of 27 MHz are sent to the DACs, respectively 105, 114, 123, each of which converts the codes of doubled samples of a string into analog video signals, respectively, _ЕRП and Е _RЛ , Е _ГП and Е _GL , Е _VP and E _VL . The analogue video signals E _RP and E _RL are sent to the output video amplifier 150, E _GP and E _GL to the output video amplifier 151, E _VP and E _VL to the output video amplifier 152. Three video signals of the primary colors, alternately of the right and left images, are fed to color modulators after amplification kinescope 149. At the same time, the video signals E _VP , E _VL and E _SI are fed to a video amplifier 146, and from it to a sync pulse selector 147, which selects line and frame pulses arriving at a horizontal and vertical scanning unit 148. The signals of the outlets are fed to the corresponding inputs of the tube 149, providing a scan frame color image.

The key 140 is opened by the SSI pulses, the pulse counter 141 is 8-bit, it counts sampling pulses of 5.75 MHz and the counting cycle is 216 pulses. With the arrival of 213 pulses, the decoder 142 decrypts the binary code of the 213rd pulse and generates a signal U _{from the} first output, opening the keys 124, 125, 131, 132 in the first and second channels of the audio signal. At moments 214, 215 of the sampling pulses, the keys pass two sound codes into blocks 126, 127 and 133, 134 of the registers containing two 8-bit registers. With these codes audio signals U _vyd 62.5 kHz with the third output 139 of the frequency synthesizer are given respectively in DAC 138 and DAC 135, which convert the 16-bit codes into analog audio signals into their blocks 129, 136 sounds, where amplified , and then are reproduced by loudspeakers 130, 137. With the arrival of pulses 216 of the 216 pulse to the counter 141, the decoder 142 generates a signal from the second output, which closes the keys 124, 125, 131, 132, resets the counter 141 and closes the key 140. With the arrival of the next lowercase clock on control in key stroke 140 the process is repeated.

The condition for the issuance by the block 143 of the frame sync pulse of the CSI (Fig. 12) is the simultaneous arrival at the counting inputs of the block 143 of three codes 11111111 from the shapers 101, 110, 119 pulses and the arrival of the pulse of the CSI from block 138. The CSI from block 143 follow with a frequency of 25 Hz and come to the emitter 144. The pulse generator in the emitter 144 generates a pulse in duration and amplitude, which is fed to a pulsed infrared LED emitting an infrared pulse of appropriate duration. The photodetector 181 in the block 145 for separate observation of frames (Fig. 14) receives a signal from the emitter 144, the pulse shaper 182 generates a signal of duration and amplitude, which starts the pulse generator 183, which generates 50 Hz control pulses for the piezoelectric motor 184. The piezoelectric motor is used for control pulses rotates the shaft with 90 ° sampling. At the time of reproduction of the right image on the kinescope screen 149 synchronously with it, the right eye window with glasses 187 is open, the left eye window is blocked by neutral filters. The duration of the open state of the window and image is 20 ms. With the arrival of the next impulse from the generator 183, the shaft rotates 90 °, the left eye window opens, the right one is blocked by filters 186. The viewer observes the left image on the picture tube screen with the left eye. The right and left eyes of the viewer see each of its image, which is what perceives the three-dimensional image.

System operation.

Three analog video signals of the right image from the photoelectric converter 1 are supplied to the ADC 3, 4, 5, three analog video signals of the left image from the photoelectric converter 2 are supplied to the ADC 6, 7, 8, which convert them to 8-bit codes with 13.5 MHz sampling . Two sound signals are fed to the ADC 9, 10, which convert them to 16-bit codes with a sampling rate of 62.5 kHz.

Shapers 13, 14, 15 codes form consecutive codes from parallel codes and replace the representation of units from pulses in them with positive half-sine waves (odd samples of the line) and negative half-sine waves (even samples of the line) of the 54 MHz monofrequency. The clock frequency in the system is 54 MHz, the frequency stability of the master oscillator is 11 10 ^-7 . On the transmitting side, 625 lines of the frame are encoded, 432 counts each, line scan in the frame is line-by-line, line frequency is 31.25 kHz, frames are 50 Hz. The video signal of the right and left images follow alternately through the frame, 25 frames of one and the other per second. The distance between the optical axes of the lenses on the transmitting side of the first and second photoelectric converters corresponds to the optimal stereoscopic effect. The information is transmitted by three channels of the transmitter 22: the first transmits information of codes E _RP , E _RL , the second - codes E _GP , E _GL , the third codes E _VP , E _VL . The data transfer rate is 324 Mbps. The receiving side receives three radio signals, amplifies them, detects, extracts horizontal and frame sync pulses. Synthesizer 139 generates two carrier frequencies and provides the necessary control signals. In the channels of code processing, the frequency of samples in a line is doubled by obtaining intermediate values of samples between each previous and subsequent codes. Codes with a frequency of 27 MHz go to the DAC 105, 114, 123, where they are converted into analog video signals, which are amplified by the output video amplifiers 150, 151, 152 and fed to the corresponding modulators of the picture tube 149. The analog signals of the E _SI clock pulses entering the video signal stream E _B are received to the video amplifier 146, then to the clock selector 147 and to the horizontal and vertical scanning unit 148, from which they are supplied to the corresponding inputs of the kinescope 149, scanning the image on the screen. Before each odd frame, the emitter 144 produces infrared radiation received by the photodetector 181, the signal from which the pulse generator 183 is launched, which generates 50 Hz control pulses for the piezoelectric motor 184. For each pulse, the piezoelectric motor rotates the shaft with the filters 90 °. In this case, one of the eye windows of the glasses is open, the second is blocked by neutral filters 186. When playing the right image on the kinescope screen, the right eye window is opened simultaneously with it, the left one is blocked by filters, and vice versa. As a result, the viewer observes the right image with the right eye, the left image with the left eye, obtaining a three-dimensional image. Stereo sound reproduce two channels of the audio signal. The reproduced frame contains 625 lines with 864 samples in each, information playback speed of 648 Mbit / s.

The system can be applied over existing terrestrial TV networks in the UHF range reserved for television and via satellite communication lines. The number of blocks 145 to the receiving side should correspond to the number of viewers.

Used sources.

1. Patent No. 2173030, cl. H 04 7/00, bull. 24 from 08/27/01, prototype.

2. Radio transmitting devices, M. S. Shumilin and others, 1981, S. 234, 235.

3. Fridland M.V., Soshnikov V.G. “Automatic control systems in video recording devices”, M., 1988, p.118 fig.5.5, p.122, fig.5.10.

4. V.F. Samoilov, B.P. Khromoi “Television”, M., 1975, p. 389.

5. “Instruments and control systems”, No. 1 for 1990, p.40.

6. Digital integrated circuits, Minsk, 1991, S. 231, 258.

7. Shilo V.A. “Popular Digital ICs,” Chelyabinsk, 1989, p. 222.

8. Brodsky M.A. “Color television sets”, 1988, Minsk, p. 86, fig. 2.55, p. 132, fig. 4.2.

9. Radio communications, broadcasting and television, ed. A.D. Fortushenko, M., 1981, p. 146.

10. Barkan V.F., Zhdanov V.K. “Amplification and impulse technology”, M., 1981, p.209.

Claims (1)

A stereo television system containing a transmitting side, which includes a first photoelectric converter, the first, second, third outputs of which are connected, respectively, the first, second and third analog-to-digital converters (ADCs), includes the first ADC of the sound signal, the sinusoidal oscillation generator connected in series to the input whose synchronization signal is supplied, and a frequency divider, a first self-propelled pulse distributor and a radio signal transmitter, the channel of which includes a series connection data of the generator of the first carrier frequency, the input of which is connected to the corresponding output of the frequency divider, an amplitude modulator, including a ring modulator and a bandpass filter connected in series, and an output amplifier, an audio signal, the first, second, and third ADCs are applied to the information input of the first ADC of the sound signal contains a video amplifier, a piezoelectric deflector with a light reflector at the end, a pulsed emitter including a pulsed LED, a slit diaphragm and a lens, and a encoder, an ADC input is the input of the video amplifier is given, the encoder outputs are the output, the sampling frequency pulses are applied to the pulse LED input, the first ADC of the sound signal includes a controlled voltage divider, a key block, a matching amplifier, an audio frequency amplifier and a piezoelectric deflector with a light reflector at the end, the first source of a positive reference voltage, the output of which is connected to the second inputs of the audio frequency amplifier and piezoelectric deflector, the second source of negative reference voltage, you One of which is connected to the third inputs of the audio frequency amplifier and piezoelectric deflector, a pulsed emitter from a pulsed LED, a slit diaphragm, and a lens, a first decoder, an encoder, and a second decoder connected in series, the outputs of which are connected to the corresponding control inputs of the key block and the corresponding inputs of the first decoder, and includes serially connected pulse counter, the third decoder and the register block, the inputs of which are connected to the encoder outputs, and the outputs of the register block is are the ADC outputs of the sound signal, the first control input of which is the counter input of the pulse counter, the second is the control input of the pulse counter, the third is the combined LED input and the control input of the register block, and it contains the receiving side, including the antenna, the sensor control block, the first reception path and the processing of video signal codes, which contains a series-connected radio signal receiving unit, the first input of which is connected to the antenna, the second group of inputs is connected to the outputs of the touch control unit the amplifier, the radio frequency amplifier and the bipolar amplitude detector, and the first and second pulse shapers, the inputs of which are connected respectively to the first and second outputs of the bipolar amplitude detector, the receiving side includes three digital-to-analog converters (DACs), a video amplifier connected in series, the input of which is connected to the output of the corresponding DAC , a clock selector and a line and frame scan unit, the outputs of which are connected to the corresponding inputs of the color picture tube, three output an ideal amplifier of three primary colors, the outputs of which are connected to the corresponding control inputs of the color picture tube, includes a control signal generation channel containing a horizontal sync pulse extraction unit, the first and second inputs of which are connected to the outputs of the first and second pulse shapers, a key, a pulse counter, and a decoder connected in series, the horizontal sync pulse allocation block contains the first and second pulse counters, the counting inputs of which are the inputs of the block, the first and second elements NOTs whose inputs are connected respectively to the inputs of the first and second pulse counters, and the first AND element, whose inputs are connected to the outputs of the first and second pulse counters, and the output is the output of the horizontal sync pulse allocation unit, the outputs of the NOT elements and the output of the AND element through the diode are combined and connected to the control inputs of the pulse counters, includes the first channel of the audio signal containing the first and second keys, the inputs of which are connected to the outputs of the first and second pulse shapers, the first control the key inputs are connected to the first output of the decoder in the channel for generating control signals, the second control inputs of the keys are connected to the second output of the decoder, which is connected in parallel to the second control input of the key in the channels for generating the control signals and to the control input of the pulse counter, the outputs of the first and second keys are connected respectively, to the inputs of the first and second blocks of registers, the outputs of which are connected to the corresponding inputs of the DAC of the first channel of the audio signal, the output of which is connected to the input of the sound accompaniment unit, the output of which is connected to the loudspeaker input, characterized in that a second photoelectric converter identical to the first, fourth, fifth and sixth ADCs, the inputs of which are connected to the first, second, third outputs of the second, respectively, is inserted into it on the transmitting side a photoelectric converter, a second ADC of a sound signal, to the information input of which a second sound signal is supplied, the first, second, third code generators are connected in series A separate pulse counter and a second self-propelled pulse distributor, a trigger, first and second keys, the outputs of the first and fourth ADCs are connected to the first information input of the first code generator, the outputs of the second and fifth ADCs are connected to the first information input of the second code generator, the outputs of the third and sixth ADCs are connected to the first information input of the third code generator, the output of the first ADC sound signal is connected to the second information input of the first code generator, the output of the second ADC signal the sound is connected to the second information input of the second code generator, the output of the first self-propelled pulse distributor is connected to the third information inputs of the first and second code drivers, the output of the second self-driving pulse distributor is connected to the fourth information inputs of the first, second code drivers and to the third information input of the third code generator, the outputs of the frequency divider are connected first - to the first control the first inputs of the first, second, third code generators and the signal inputs of the first and second keys, the second to the second control inputs of the first, second, third code generators and to the first control inputs of the first and second ADC sound signals, the third to the third control inputs of the first, the second, third code shapers, the fourth - to the fourth control inputs of the first, second code shapers and to the third control inputs of the first and second ADC sound signals, the fifth - to the control input of the pulse counter the output of the second discharge of which is connected to the input of the second self-propelled pulse distributor, the sixth - to the second control inputs of the first and second ADCs of the sound signal, the seventh - to the trigger input, the first output of which is connected to the first control input of the first key and to the second control input of the second key, the second output is connected to the second control input of the first key and to the first control input of the second key, the output of the first key is connected to the clock inputs of the first, second, third ADCs, the output of the second key is connected it is connected to the clock inputs of the fourth, fifth, and sixth ADCs, the input of the first self-propelled pulse distributor and the counting input of the pulse counter are connected to the second output of the second code generator, the second channel is introduced into the radio signal transmitter, containing a second carrier frequency generator, an amplitude modulator and an output amplifier connected in series, the third channel, containing a series-connected amplitude modulator, the input of which is connected to the output of the generator of the first carrier frequency in the first channel, and the output amplifier the amplifier, the inputs of the first and second carrier frequencies generators are combined and connected to the eighth output of the frequency divider, the amplitude modulators in the second and third channels are identical to the amplitude modulator of the first channel, the second input of the amplitude modulator of the first channel is connected to the output of the first code generator, the second input of the amplitude modulator of the second channel the radio signal transmitter is connected to the first output of the second code generator, the second input of the amplitude modulator of the third channel of the radio signal transmitter is connected It is connected to the output of the third code driver, the first source of positive reference voltage, the second source of negative reference voltage and the array of multi-element photodetector are introduced into the first, second ADCs, the output of the first source of positive reference voltage is connected to the second inputs of the video amplifier and piezoelectric deflector, the output of the second source of negative reference voltage is connected to the third inputs of the video amplifier and piezoelectric deflector, the outputs of the multi-element photodetector line are connected to the encoder inputs, its drive windows are optically connected to the piezoelectric reflector, the fourth and fifth ADCs are identical to the first and second ADCs, a summing amplifier, a first source of positive reference voltage, a second source of negative reference voltage, a multi-element photodetector line are introduced into the third ADC, the first input of the summing amplifier is connected to the output of the video amplifier , the synchronization signal E is applied to the second input of the summing amplifier _SI , the output is connected to the first input of the piezoelectric deflector, the output of the first source of positive reference voltage is connected to the second inputs of the summing amplifier and the piezoelectric deflector, the output of the second source of negative reference voltage is connected to the third inputs of the summing amplifier and piezoelectric deflector, the input windows of the multi-element photodetector line are optically connected to the piezoelectric reflector, and its outputs are connected to the inputs of the encoder, the sixth ADC is identical to the third ADC, a lot of lines are introduced into the first ADC of the sound signal a photocell detector, the input windows of which are optically connected to the piezoelectric reflector, and its outputs are connected to the corresponding inputs of the first decoder, the second ADC of the sound signal is identical to the first ADC of the sound signal, the first and second code generators are identical, each includes a trigger and a switching unit and four channels connected in series , the inputs of the first and second channels are connected to the corresponding outputs of the switching unit, and the outputs of the four channels are combined, the first channel includes series-connected the first block of AND elements, the first and second OR elements and the first output switch, and the first self-propelled pulse distributor, the second channel includes the second block of AND elements, the third and fourth OR elements and the second output switch, and the second self-propelled pulse distributor, the first inputs of the first and the second blocks of elements And are connected to the corresponding outputs of the switching unit, the second inputs of the first block of elements And are connected to the outputs of the first self-propelled pulse distributor, the second inputs of the second block e AND elements are connected to the outputs of the second self-propelled pulse distributor, the third channel includes the third AND element block and the fifth OR element, and the third self-propelled pulse distributor, the output of the fifth OR element is connected to the second input of the second OR element, the fourth channel includes the fourth block of elements connected in series And the sixth OR element, and the fourth self-propelled pulse distributor, the output of the sixth OR element is connected to the second input of the fourth OR element, the second inputs are the third and fourth blocks of elements And are connected respectively to the outputs of the third and fourth self-propelled pulse distributors, includes the first and second keys and series-connected pulse counter and decoder, the first output of which is connected to the first and second control input of the first and second keys, respectively, the second output of the decoder is connected to the second and first control inputs of the first and second keys, respectively, the output of the first key is connected to the inputs of the first and second self-propelled distributor th pulse, the output of the second key is connected to the inputs of the third and fourth self-propelled pulse distributors, the input of the code generator is the combined output of the output keys, the first and second information inputs are the inputs of the switching unit and the inputs of the third and fourth blocks of AND elements, the third and fourth information inputs are third inputs of the second and fourth elements OR, the first control input is the trigger input, the second is the combined key input and the counting input of the pulse counter, the third is the combined input of the signal inputs of the first and second output keys, the fourth control input is the control input of the pulse counter, in the second code generator the decoder has a third output, which is the second output of the second code generator, the third code generator includes a trigger and a switching unit connected in series, and two channels, the channel inputs are connected to the corresponding inputs of the switching unit, and the channel outputs are combined, the first channel includes the first block of elements connected in series , the first and second OR elements and the first output switch, and the first self-propelled pulse distributor, the second channel includes the second block of AND elements connected in series, the third and fourth OR elements and the second output switch, and the second self-propelled pulse distributor, the first inputs of the first and second block of elements And connected to the corresponding outputs of the switching unit, the second inputs of the first block of elements AND are connected to the outputs of the first self-propelled pulse distributor, the second inputs of the second block of elements AND are connected the outputs of the second self-propelled pulse distributor, the output of the third code generator is the combined output of the output keys, the first information input is the inputs of the switching unit, the second and third information inputs are the second inputs of the second and fourth OR elements, the first control input is the trigger input, the second is the combined inputs of the first and the second self-propelled pulse distributors, the third - the combined inputs of the signal inputs of the output keys, on the receiving side in the first path when ma and code processing video signals entered video signal processing channel codes E _R including the first and second registers of the video signal E _R and a code processing unit, information inputs of the first and second video signal registers E _R respectively connected to the outputs of the first and second pulse shapers, the outputs of the video signal registers E _R connected to the corresponding inputs of the code processing unit, the outputs of which are connected to the inputs of the first DAC, a second path for the reception and processing of video signal codes is introduced, containing serially connected radio signal receiving unit, the first input of which is connected to the antenna, the second group of inputs is connected to the first group of outputs of the touch control unit , a radio frequency amplifier and a bipolar amplitude detector, first and second pulse shapers, the inputs of which are connected respectively to the first and second outputs of the bipolar polar amplitude detector, and codes the video signal processing channel E _G including the first and second registers of the video signal E _G and a code processing unit, information inputs of the first and second video signal registers E _G respectively connected to the outputs of the first and second pulse shapers, the outputs of the video signal registers E _G connected to the corresponding inputs of the code processing unit, the outputs of which are connected to the inputs of the second DAC, a third channel for receiving and processing codes of video signals is introduced, containing a series-connected radio signal receiving unit, the first input of which is connected to the antenna, the second group of inputs is connected to the first group of outputs of the touch control unit , a radio frequency amplifier and a bipolar amplitude detector, first and second pulse shapers, the inputs of which are connected to the first and second outputs of bipolar amplitudes th detector, and codes the video signal processing channel E _IN including the first and second registers of the video signal E _IN and code processing unit, information inputs of video signal registers E _IN connected to the outputs of the first and second pulse shapers, respectively, the outputs of the first and second video signal registers E _IN connected to the corresponding inputs of the code processing unit, the outputs of which are connected to the inputs of the third DAC, the code processing units are identical, each includes a trigger, first, second, third, fourth registers, first, second, third blocks of delay elements, fifth and sixth registers, and an adder , the first and second registers are connected in parallel to the outputs of the first block of delay elements, the inputs of which are the first information input of the block, the third and fourth registers are connected in parallel to the outputs of the second block of delay elements, the inputs of which are the second information input of the code processing unit, the trigger input is a control input, the first trigger output is connected in parallel to the control inputs of the second, third and fifth registers, the second trigger output is connected in parallel to the control inputs of the first, fourth and sixth registers, the outputs of the first register are connected to the inputs of the fifth register and through diodes to the first inputs of the adder, to which the outputs of the second register are connected, the outputs of the third register are connected to the inputs of the sixth register and through diodes connected to the second inputs of the adder, to which the outputs of the fourth register are connected, the outputs of the adder are connected to the inputs of the third block of delay elements, the outputs of which are combined with the corresponding outputs of the fifth and sixth registers and are outputs of the code processing unit, the control input of the adder is connected to the trigger input , a frequency synthesizer and a frame sync pulse extraction unit are introduced into the control signal generation channel, the first second, third inputs of which are connected to the outputs of the second waveforms pulse generators, respectively, in the first, second and third paths of receiving and processing codes of video signals, the fourth input is connected to the output of the horizontal sync pulse allocation unit, the output of which is connected to the first control input of the frequency synthesizer, the second group of inputs of which is connected to the second group of outputs of the touch control unit, the first the output of the frequency synthesizer is connected to the signal input of the key and to the first control inputs of the first and second video signal registers E _R , E _G , E _B , to the clock inputs of which the second output of the frequency synthesizer is connected, the fourth output of which is connected to the control inputs of the code processing units, the fifth output is connected to the third inputs of the radio signal reception blocks in the first and third paths of the reception and processing of video signal codes, the sixth output is connected to the third input of the reception block of the radio signal in the second path of receiving and processing codes of video signals, a third pulse counter, a second AND element, and a third NOT element, the output of which is inen with the outputs of the first and second elements NOT, and the input is connected to the counting input of the third pulse counter, which is the third input of the horizontal sync pulse allocation unit, the first and second inputs of the second AND element are connected respectively to the output of the first AND element and to the output of the third pulse counter, the output the second element And is the output of the block and is connected through the diode to the combined outputs of the three elements NOT, to which the control input of the third pulse counter is connected, the first, second and third inputs of the block The horizontal sync pulse is connected to the outputs of the first pulse shapers in the first, second, third paths of receiving and processing video signal codes, the frame sync pulse extraction unit contains the first, second, third pulse counters, the first, second, third elements AND, the first, second, third elements HE , and a diode, the inputs of the HE elements are connected to the counting inputs of the first, second, third pulse counters, respectively, which are the inputs of the block, the control inputs of the pulse counters are combined and connected to the combination the output outputs of the elements are NOT, the outputs of the first and second pulse counters are connected to the inputs of the first element And, the output of which and the output of the third pulse counter are connected to the inputs of the second element And, the output of which and the fourth input of the block are connected to the inputs of the third element And, the output of which is the output of the block and through a diode it is connected to the control inputs of the pulse counters, a second channel of the sound signal is introduced identical to the first channel of the sound signal, the inputs of the first and second keys of the second channel of the sound signal are connected respectively, to the outputs of the first and second pulse shapers in the second path for receiving and processing video signal codes, the clock inputs of the register blocks of both channels are connected in parallel to the second output of the frequency synthesizer and the first control inputs of the register blocks of both channels are connected in parallel to the third output of the frequency synthesizer, on the receiving side an emitter is introduced comprising a pulse shaper connected in series, the input of which is connected to the output of the frame sync pulse extraction unit, and pulse infrared LED, block for separate observation of frames, including a series-connected infrared photodetector, pulse shaper, pulse generator and piezoelectric motor, on the shaft of which there are fixed right and left cylindrical frames, each of which has two neutral filters, each neutral filter occupies one the fourth part of the cylindrical surface of the frame, neutral filters are arranged in a cylindrical frame against each other through 180 °, and the position of the neutral filters in the right-hand frame relative to them in the left-hand frame is 90 ° shifted, the infrared photodetector, pulse former and pulse generator are placed in a separate housing, which is located by the input window of the infrared photodetector opposite the radiating side of the emitter, a piezoelectric motor with a shaft , with cylindrical frames and neutral filters in them are fixed on the outside of the case of glasses having right and left eye windows with transparent glasses Against ocular windows on the outer side of points located respectively right and left cylindrical rim with neutral filters.

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