RU1835529C - Appliance for information collecting and coding from hodoscope detectors and multi-wired proportional cameras - Google Patents

Abstract

Field of use: data collection systems in Research on Nuclear Particle Physics. The inventive device for collecting and encoding information from multi-wire proportional cameras and hodoscopic detectors, containing formative amplifiers, an output register, a coding unit and an input register connected to the inputs of the corresponding outputs of the N independent amplifiers-shapers and outputs to the corresponding inputs coding unit, two adders are introduced, connected by inputs to the corresponding outputs of the coding unit and outputs to the corresponding inputs of the output register, and the block encoding is multi-link with the number of coding elements decreasing from input to output exponentially by a factor of n. 3 il ..

Description

The invention relates to the field of information measurement and computer technology, namely, data acquisition systems for research in nuclear physics and elementary particle physics, can be used to quickly collect and encode information from multiwire proportional cameras and hodoscopic detectors.

In FIG. 1 is a functional diagram of a device with a two-link circuit of an encoding unit; figure 2 is a functional diagram of the coding element of the first type;

Fig. 3 is a functional diagram of a coding element of the second type.

The device (Fig. 1) consists of N parallel amplifiers - drivers 1. The inputs 2 of which are the inputs of the device, and the outputs of the amplifiers - drivers 1 are connected to the inputs 3 of the input register 4, to which the Start bus is connected to the recording synchronization input 5. The outputs of input register 4 are divided into N / n parallel sections, each with (n + 1) bits, as follows:

1 section - bits from zero to the fifth.

00

GJ SP SL hO O

2 sections - bits from the n-th to the 2-nd second.

3 sections - bits from the 2nd to the 3rd, 1st section - bits from the (1-1) n to

In-oro.

Each lnth bit of the input register 4 is included as a junior in the (1 + 1) th section and as a senior in the lth. The outputs of the input register A are connected in sections to the inputs of the coding elements of the first type (CEPT) 6 of the encoding unit. moreover, the (n + k) -th output of input register A is connected to the k-th bit of the input of the first CEPT 6. The first outputs of 7 CEPT b are connected to the first inputs of 8 coding elements of the second type (CEPT) 9, and the second outputs 1Q of CEPT 6 connected to the second inputs of 11 KEVT 9. The third outputs of 12 KZET 6 are connected to the third inputs of 13 KEVT 9, and the fourth outputs of 14 KEPT 6 are connected to the fourth inputs of 15 KEVT 9. By the way, the input of 16 CEPT b ln + k-th section the k-th bit is connected to the output of the 17th CEPT 9. and the k-th bit of the output 1.7 of the 1st CEPT 6 is connected to the R-input In + k-oro of the bit input register 4.

The first output of 7 KEVT 9, located in the j-th link (, 3 ... lognN) at n + k-th place is connected to the k-th rank of the first input of 8 KEVT 9, located in j + 1-th link in 1st place, and the first exit 7 of KEVZ 9, the lognN-oro link is the bus end of the processing.

The second output of 10 KEVT 9, which is located in the Jth link at ln + kth place, is connected to the kth bit of the second input of 11 KEVT 9, which is located at 0 + 1) link in the ith place.

The third - (0 1od2p) -bit outputs 12 КЭВТ 9, located in the Jth link at ln + k-рм place are connected to the k-oro bits of the channel of the third input1 consisting of j channels of 0 1od2p) bits in each channel KEVT 9, standing in the j + 1-st link at the i-th place. The fourth 0 1od2p) -bit outputs of 14 KEVT 9, located in the jth link at ln + kth place, are connected to the ko bits of the channel of the fourth input 15, consisting of p channels of 0 1od2p) - bits in each channel KEVT 9, located in the j + 1st link in 1st place, is connected to the fifth input of 16 KEVZ 9, standing in the J-rd link in In + kth place, and to p to the input 16 of KEVZ 9 of the iognN-oro link the Prin 18 bus is connected, which is also connected to the R-input 18 of trigger 19 Ready. log2N bit third outputs 12 KEWT 9 lognN-oro links are connected to the inputs of the first term 20 of the first log2N-bit adder 21 and to the inverse inputs 22 of the subtracted second adder 23. 1od2M-bit fourth outputs 14 KEVT 9 IognN-oro links are connected to the inputs of the second term 24 of the first adder 21 and to the inputs 25 of the reduced second adder-subtractor 23. The outputs of the adders 21 and 23 are connected to the inputs of the output register 26, the output of which is a 2 od2M-bit output of the device, and to the write synchronization input 27 of the output 26 register The clock bus 28 is also connected, which is also connected to the S-input 29 of the trigger 19.

Each CEPT 6 (FIG. 2) consists of a p-bit priority coding scheme (CSC) 30 and an n + 1-bit cluster end coding scheme (CCM) 31, the inputs of which are combined bitwise from the first to n- the second (the n + 1st bit is supplied only to the CCMC 31) and are the inputs of the 8 CEPT 6. The high-order bits of the outputs of the CSC 30 and the CCMC31 are the first 7 and second 10 single-bit outputs of CEPT 6, the remaining bits of the outputs of the CECP 30 are third 12, and outputs 32 of CKRK 31 are fourth outputs of CEPT 6 and are connected inside CEPT 6 to the inputs of Iog2n, the input priority decoding circuit (LED O) 33, the outputs of which are the fifth outputs 17 of the KEPZ 6, and the fifth input 16 of the KEPZ 6 is connected to the building input 34 of the SDP 33.

Each CECT 9 (Fig. 3) consists of a first 35 and a second 36. priority coding scheme (UPC). identical SKP 30. The inputs of SKP 35 and 36 are the first 8 and second 11 inputs of KEVT 9, respectively, and the outputs 37 of SKP 35 and 38 SKP 36 are the senior Iog2n bits of the third 12 and fourth 14 outputs of KEVT 9, respectively, and connected also inside KEVT 9 to the address inputs of the first 39 and second 40 p-channel (| 1od2p) -bit multiplexers, the channel outputs of which are the third 13 and fourth 15 inputs of KEVT 9, respectively, and the outputs of the multiplexers 39 and 40 are junior Q- 1) log2n bits, respectively, of the third 12 and fourth 14 outputs of KEVT 9. Outputs 38 W The second SKP 36 is also connected to the inputs of the priority decoding circuit (SDP) 41, which is identical to the SDP 33. The outputs of the PSD 41 are the fifth outputs 17 of the CEC 9. And the gate-seeking input 42 of the SDP 41 is the fifth input of the 16 KEVZ 9 ..

SKP 30, 35 and 36, SKK 31, and SDP 33 and 41 are logical elements that implement the truth tables below (as an example for) and can be made in the form of combinational circuits or read-only memory devices. The states of the inputs and outputs not shown in the tables are not important for the operation of the device.

Table 1

Truth table UPC 30.35 and 36 dl

Continuation of the table. 3

Table 2 truth table CCM 31 dl

Table 3 truth table PSD 33 and 41 dl

Inputs

V 0 1 2 1 000 1001

Outputs

01 234567 11111111 10000000

It can be seen from Table 1 that the UPCs 30, 35, and 36 encode the number of the bit in which for the first time, counting from the lowest input bit, a unit appears after a series of zeros (combination 01).

If the term cluster defines a group of adjacent units, or one unit with zeros on each side, then SKP 30 and 35 at the output of 12 CEPT 6 and 37 KEVT 7 indicates that the beginning of the cluster in received

UPC input 30 and 35 bits are. In this case, G in the zero position is also considered the beginning of the cluster.

From table 2 it is seen that CCMC 31 encodes the number of the bit in which for the first time, counting

from the low order, the combination 10 appeared, i.e. CCM 31 at outputs 32 provides the address of the end of the lowest cluster. A single state of output 10 indicates that the end of the cluster at the input of CCM 31 is present.

In this case, the state All Zeros at the input of CCMC 31 is not considered to be the end of the cluster, and other states that do not have a combination of 10 are considered to be the state that does not have the end of the cluster.

From table 3 it is seen that SDP 33 and 41 code A

filed at her entrances, with a strobe

at the input V 34 and 42 decodes into a sequence of A units, starting from zero

to A-1 position, while maintaining zeros

at positions x to p-th.

A device for collecting and encoding information from hodoscopic detectors and legwire proportional cameras operates as follows. The Start signal, which comes from the bus 5 from the outside and records the voltage of the proportional chamber wires coming from the N inputs 2, amplified and

formed into logic signal levels by amplifiers mi-shapers 1.

Suppose that the original word X contains Q clusters of length Iq each with starting addresses Aq and ending addresses Bq. In other words, in the original M-bit word X, at positions Bq xAq + i, there are zeros, and at positions with numbers, there are ones. It's obvious that

.

...... ... A (, (1)

in the p-number system,

Ah 2aqin, M Bq Zbqi n. (2)

where aqi, bqi-n are significant (from O to np-1) values of the 1st digits of the numbers Aq and Bq, respectively. Obviously since

JJ Oh

Ai n 5, aqi n nci,

L

B1 P 2 bqin

1-2.

: ndi,

then, at the output 12 of the same CEPT 6, a binary number is formed representing the number of the position at which the cluster begins, i.e. number ai.

Similarly, according to Table 2, in all CEPT 6 with numbers Kci and i (di + 1), the signal at output 10 is O, and in CEPT 6 with numbers ci Kdi, the signal at output 10 is equal. At the outputs 14 of these CEPT 6 are formed: for CEPT 6 with numbers Kci-zeros, for CEPT 9 with code number bc. The signals from the outputs 7 are collected at the output 8 KEVT 9 of the next link and since,

Ai n 2 aqi

moreover, the outputs 7 of all CEPT 6 with numbers are zeroed, then the code is generated at the outputs 12 of CECT 9 of the second link with number C2

812.

Similarly, the signals from the respirator 10 of the CEPT 6 are collected at the inputs 11 of the CECT 9 of the second link and, since

 I bqin 3 n2d2

then at the output 14 of the CECT 9 of the second even number d2, the code bt2 is generated. Similarly, codes ai and bii are generated in all subsequent links, since the multiplexers 39 and 40 in all KEHTs 9- are controlled by the address input of the UPC 35 and 36

accordingly, codes pass through multiplexers 39 and 40 in the i-th link

m, i 2 bijn1 1

twenty

25

thirty

35

40

45

fifty

55

respectively (after all, the address at the input of multiplexers 39 and 40 is the numbers ai and bc of that of the previous, 1-1th link, in which the beginning and end of the cluster are detected, respectively).

Thus, the binary code of the number Ai is formed at the output 12 of the KEVT 9 of the last pth link, and the output code 14 of the 14 KEVT 9 is the code BL At the output of the adder 21, the p + 1-bit code 2Ci is generated:

2Ci Ai + Bi, (7)

and at the output of the adder-subtractor 23 is a bit-code LI:

.i-ait. ;

Since the low-order bit of the adder 21 is not connected to the D-inputs of the register 26, p-bit codes C (center of the lowest cluster) and Li (width of the lower cluster) are received at its inputs.

When a signal appears on synchronization bus 28, these codes are written to output register 26. Trigger 19 is switched with the same clock signal, the single state of which indicates readiness of information in register 26 for reading.

. After reading from the output register 26, an external receiver (not shown in Fig. 1) provides a signal received on the 1.8 bus. This signal is fed to the fifth input 16 of the CEPT 9 of the last, pth link, and since (see Fig. 2) the Lp code is supplied to the address input of the SDP 41, according to table 3, units appear at those outputs of 15 CECT, 9 last, p-th link that have numbers 0, ir ... bp-lV

. They, in turn, go to the input of 16 KE VT 9 (r-1) -st link with the same numbers and, similar to the above, cause single signals at all outputs 17 KEVT9 (r-1) -th link with numbers OJ ,. .. (bP-1-1): for the younger (Lp-1) groups, each of them with p KEVT 9.

Thus, nbip + bi (p-i) of the lowest units comes from the outputs of 17 KEVT of the 9th p-1st link.

Similarly, at the output of the (p-2) th link, n2bi (p-i) + bi (p-2) lower units are formed, etc.

As a result, at the outputs of 17 CAPES 6, Bi units appear in the lower bits, which arrive at the Bi lower R-inputs of register 4 and reset these bits to O.

From this moment, the younger cluster {Ai, Bi} is destroyed, turned into O and the device accepts as the younger cluster, the next one, with the addresses of the beginning and end of Az and B2, and the operation of the device resumes, as described above, starting from the moment the initial information was written to register 4..

The operation of the device is continued in such a way that all clusters are processed sequentially until they are exhausted. After processing and resetting the serial cluster, the entire register 4 is reset. Therefore, at the outputs 7 KEVT 9 of all links of zero, including the output 7 of KEVD 9 of the last, p-th link, where zero is formed if and only if (see table 1), when the entire register A. .

Zero at the output of 7 KECTs of the 9th link and is a signal at the end of processing.

The processing of each cluster takes time, linearly dependent on the number of links:

Then P (2 GCEVT + GSDP + TSM + tRG + T4T + G), (8)

where tkevt is the response time of one KEVT 9 (SKP 35 and 36 in parallel and multiplexers 39 and 40 in parallel);

 - time parallel operation of the adders 21 and 23

TRG - write time to output register 26 ;.

ttc is the reading time by an external receiving device (communication channel, memory device, etc.) of information from register 26;

TR - reset time of input register 4,

The coefficient 2 in front of the r-kkevt term is effective because the r-tkevt time is required both for the occurrence of the KEHT information at the outputs of the adders 21 and 23, and for. passing a reset signal to the input of input register 4; GSDP-time decryption reset one SDP 33.

Thus, the processing of the entire source array from the input register 4 requires time t

 lognN (2 GKEBT + tsdp) +0 (tzm + g with +

+ T4T + TRG). (9)

In the prototype, tnP time is required to process the entire array from input register 4: tnP: Q

tnp SfrsM + tcht + 2 TRG) + (gskp + TR) tq,

where GSCP is the time-value of the tripping of the UPC 30, i.e.

9

Get: tnp

02)

 (gsm + tcht + 2 TUG) + (gscp + TR) g ig

In addition, the prototype system has

32 bits, with the length of the input word, sequential polling is performed. If we take 32 for n - the base bit of the proposed device, then tnp for

N bits will have to be increased n times:

tnp Q (rsw + tcht + 2 TRG) + - (gskp + TUG) 2

(YU)

Prien in TSM TMT TRG tskgg tsdp (11)

 + - 2 lq.

t-4Qr + - I In

It is obvious that, moreover, the payoff function f tnp / t will increase with increasing

the number of Ig units in each cluster and

with an increase in the number of N wires, the camera.

For example, during Monte Carlo simulations of the /.i decay, for the METR setup developed by the Institute for Nuclear Research of the Russian Academy of Sciences, average values (of clusters) were obtained. Lg (wires), i.e. from (12) at, 1924 e

While 13 tons. Thus, the average gain for the installation. The meter will be „

f JnEi - T 924 t 13

148 times.

Thus, this device allows you to process information about one candidate for the desired event on average 148 times faster (for installing METP), reducing dead time from 4 1924 g to

4 13g.

The use of the invention provides improved performance by simultaneously determining not only the start address, but also the end address of the youngest (having minimum start and end addresses) clusters, and then resetting the younger cluster so that the next cluster becomes the youngest, as well as parallel -calculating the coordinates of the center and

cluster widths.

Formula s and a Device for collecting and coding information from hodoscopic detectors and

multi-wire proportional chambers, containing N stand-alone amplifiers-shapers, the inputs of which are the inputs of the device, the output register, the output of which is the output of the device, the coding unit and the input register connected by the inputs to the outputs of the N stand-alone amplifiers-shapers and the outputs to the corresponding inputs of the block encodings, and so on.

0

that, in order to increase the reliability and speed, two adders are introduced into it, connected by inputs to the corresponding outputs of the encoding unit and outputs by the corresponding inputs of the output register, and the encoding unit is multi-link with the number of encoding elements decreasing exponentially by half.

fts. 1

Figure 1

. 7: