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KR970077366A - Method of manufacturing high-voltage transistor - Google Patents

Method of manufacturing high-voltage transistor Download PDF

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Publication number
KR970077366A
KR970077366A KR1019960014660A KR19960014660A KR970077366A KR 970077366 A KR970077366 A KR 970077366A KR 1019960014660 A KR1019960014660 A KR 1019960014660A KR 19960014660 A KR19960014660 A KR 19960014660A KR 970077366 A KR970077366 A KR 970077366A
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KR
South Korea
Prior art keywords
region
forming
source
predetermined
drain
Prior art date
Application number
KR1019960014660A
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Korean (ko)
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KR100192183B1 (en
Inventor
송택근
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019960014660A priority Critical patent/KR100192183B1/en
Publication of KR970077366A publication Critical patent/KR970077366A/en
Application granted granted Critical
Publication of KR100192183B1 publication Critical patent/KR100192183B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 반도체 소자의 제조방법에 있어서, 트랜지스터의 채널영역에 소오스/드레인 드립트(drift) 영역과 같은 타입의 채널 드립트 영역을 형성함으로써 펀치 쓰루 현상을 방지함과 더불어, 트랜지스터 구동에 따른 동작 저항을 감소시킬 수 있는 고전압 트랜지스터의 제조방법에 관한 것으로, 반도체 기판상에 소정의 웰을 형성한 후, 상기 웰 영역에 소정의 소오스/드레인 드립트영역을 형성한 다음, 웰 영역 상부에 필드 산화막 및 게이트 절연막을 형성하고 상기 게이트 절연막 상부에 소정의 게이트 전극을 형성한 후, 상기 소오스/드레인 드립트 영역의 소정 부분에 소오스/드레인의 고농도 주입 영역을 형성하여 접합영역을 구축하는 고전압 트랜지스터의 제조방법에 있어서, 상기 소오스/드레인 드립트 영역의 형성시 상기 게이트 전극 하부에 있는 상기 반도체 기판 표면에 소정의 채널 드립트 영역을 형성하는 것을 특징으로 한다.The present invention relates to a method of manufacturing a semiconductor device, in which a punch-through phenomenon is prevented by forming a channel drip region of the same type as a source / drain drift region in a channel region of a transistor, A method for fabricating a high voltage transistor, the method comprising: forming a predetermined well on a semiconductor substrate; forming a predetermined source / drain region in the well region; And forming a junction region by forming a gate insulating film, forming a predetermined gate electrode on the gate insulating film, and forming a high concentration injection region of a source / drain in a predetermined portion of the source / drain region, The method of claim 1, further comprising forming a source / drain region Is characterized in that a predetermined channel drip region is formed on the surface of the semiconductor substrate.

Description

고전압 트랜지스터의 제조방법Method of manufacturing high-voltage transistor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제2a도 내지 제2f도는 본 발명의 일 실시예에 따른 고전압 트랜지스터의 제조방법을 나타낸 공정 단면도.FIGS. 2a through 2f are process cross-sectional views illustrating a method of manufacturing a high-voltage transistor according to an embodiment of the present invention.

Claims (2)

반도체 기판상에 소정의 웰을 형성한 후, 상기 웰 영역에 소정의 소오스/드레인 드립트 영역을 형성한 다음, 웰 영역 상부에 필드 산화막 및 게이트 절연막을 형성하고 상기 게이트 절연막 상부에 소정의 게이트 전극을 형성한 후, 상기 소오스/드레인 드립트 영역의 소정 부분에 소오스/드레인 고농도 주입 영역을 형성하여 접합영역을 구축하는 고전압 트랜지스터의 제조방법에 있어서, 상기 소오스/드레인 드립트 영역의 형성시 상기 게이트 전극 하부에 있는 상기 반도체 기판 표면에 소정의 채널 드립트 영역을 형성하는 것을 특징으로 하는 고전압 트랜지스터의 제조방법.A predetermined source / drain region is formed in the well region, a field oxide film and a gate insulating film are formed on the well region, a predetermined gate electrode / drain region is formed on the gate insulating film, Drain region, and forming a junction region by forming a source / drain high concentration implant region in a predetermined portion of the source / drain region, the method comprising the steps of: forming a source / Wherein a predetermined channel drip region is formed on the surface of the semiconductor substrate at the bottom of the electrode. 제1항에 있어서, 상기 채널 드립트 영역은 상기 소오스/드레인 드립트 영역과 동일한 불순물 농도를 갖는 것을 특징으로 하는 고전압 트랜지스터 제조방법.The method of claim 1, wherein the channel drip region has the same impurity concentration as the source / drain region. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960014660A 1996-05-06 1996-05-06 Method of manufacturing high-voltage transistor KR100192183B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960014660A KR100192183B1 (en) 1996-05-06 1996-05-06 Method of manufacturing high-voltage transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960014660A KR100192183B1 (en) 1996-05-06 1996-05-06 Method of manufacturing high-voltage transistor

Publications (2)

Publication Number Publication Date
KR970077366A true KR970077366A (en) 1997-12-12
KR100192183B1 KR100192183B1 (en) 1999-06-15

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960014660A KR100192183B1 (en) 1996-05-06 1996-05-06 Method of manufacturing high-voltage transistor

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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101175231B1 (en) 2005-04-11 2012-08-21 매그나칩 반도체 유한회사 A semiconductor device and method for manufacturing the same
KR100770539B1 (en) 2006-08-11 2007-10-25 동부일렉트로닉스 주식회사 Semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
KR100192183B1 (en) 1999-06-15

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