KR970054008A - Capacitor Manufacturing Method of Semiconductor Device - Google Patents

Abstract

A method of manufacturing a capacitor having a cylindrical lower electrode capable of increasing cell capacitance while maintaining a proper step between a cell address region and a peripheral circuit region has been disclosed. According to the present invention, a conductive film is formed on the entire surface of the substrate on which the planarization layer pattern and the first etch stop layer pattern are formed, and the second etch stop layer pattern is formed on a predetermined area on the conductive film formed on the contact hole. Forming a conductive layer pattern using the second etch stop layer as an etch mask, forming an insulating layer pattern exposing the conductive layer pattern, and having a height lower than a surface of the insulating layer pattern And forming a pattern, forming a spacer on sidewalls of the insulating film pattern, and forming a lower electrode. According to the present invention, by forming a cylindrical lower electrode having a large effective capacitor area, the step difference between the cell array area and the peripheral circuit area can be properly maintained, thereby improving the pattern capacitance and the step coverage in the subsequent process, and at the same time increasing the cell capacitance. Can be.

Description

Capacitor Manufacturing Method of Semiconductor Device

Since this is an open matter, no full text was included.

4 to 11 are cross-sectional views illustrating a method of manufacturing a capacitor according to Embodiment 1 of the present invention.

Claims (14)

Patterning the planarization layer and the first etch stop layer sequentially formed on the semiconductor substrate to form a planarization layer pattern and a first etch stop layer pattern having contact holes exposing a predetermined region of the semiconductor substrate; Forming a conductive film on an entire surface of the substrate on which the planarization layer pattern and the first etch stop layer pattern are formed; Forming a second etch stop layer pattern on a predetermined region on the conductive layer formed on the contact hole; Forming a conductive layer pattern exposing the first etch stop layer pattern by etching the conductive layer using the second etch stop layer as an etch mask; Forming an insulating film on an entire surface of the substrate on which the conductive film pattern is formed, and forming an insulating film pattern that exposes the conductive film pattern by sequentially etching the insulating film and the second etch stop layer pattern; Forming a modified conductive film pattern by etching the conductive film pattern to have a height lower than a surface of the insulating film pattern using the insulating film pattern as an etching mask; Forming a spacer on sidewalls of the insulating film pattern; And forming a cylindrical lower electrode by etching the deformed conductive layer pattern so as not to expose the first etch stop layer pattern using the spacer and the insulating layer pattern as an etch mask. Manufacturing method. The method of claim 1, wherein the forming of the second etch stop layer pattern comprises: forming an oxide blocking layer on an entire surface of the substrate on which the conductive layer is formed; Patterning the oxide blocking layer to form an oxide blocking layer pattern exposing a conductive layer formed on the contact hole; Forming a second etch stop layer pattern on the exposed conductive layer; And removing the oxide blocking layer pattern. The method of claim 1, wherein the insulating layer pattern is formed to have a height equal to or lower than a surface of the conductive layer pattern. The method of claim 1, further comprising exposing the first etch stop layer pattern by etching the spacer and the insulating layer pattern after forming the lower electrode. 2. The method of claim 1, further comprising etching the spacers and the insulating layer pattern after forming the lower electrode, but not exposing the first etch stop layer pattern by leaving a portion of the insulating layer pattern. Method for manufacturing a capacitor of a semiconductor device. The method of claim 1, wherein the second etch stop layer pattern is formed of a silicon oxide layer. The method of claim 2, wherein the oxide blocking layer is formed of silicon nitride (Si ₃ N ₄ ). A planarization layer pattern having a contact hole exposing a predetermined region of the semiconductor substrate by patterning the planarization layer, the first etch stop layer, and the undercut insulating film sequentially formed on the semiconductor substrate, the first etch stop layer pattern, and the undercut insulating film pattern Forming a; Forming a conductive film on an entire surface of the substrate on which the planarization layer pattern, the first etch stop layer pattern, and the undercut insulating layer pattern are formed; Forming a second etch stop layer pattern on a predetermined region on the conductive layer formed on the contact hole; Forming a conductive layer pattern exposing the undercut insulating layer pattern by etching the conductive layer using the second etch stop layer pattern as an etch mask; Forming an insulating layer pattern on the substrate on which the conductive layer pattern is formed, and sequentially etching the insulating layer and the second etch stop layer pattern to expose the conductive layer pattern; Forming a modified conductive film pattern by etching the conductive film pattern to have a height lower than a surface of the insulating film pattern using the insulating film pattern as an etching mask; Forming a spacer on sidewalls of the insulating film pattern; And forming a cylindrical lower electrode by etching the deformed conductive layer pattern such that the undercut insulating layer pattern is not exposed by using the spacer and the insulating layer pattern as an etch mask. Way. The method of claim 8, wherein the forming of the second etch stop layer pattern comprises: forming an oxide blocking layer on an entire surface of the substrate on which the conductive layer is formed; Patterning the oxide blocking layer to form an oxide blocking layer pattern exposing a conductive layer formed on the contact hole; Forming a second etch stop layer pattern on the exposed conductive layer; And removing the oxide blocking layer pattern. The method of claim 8, wherein the insulating layer pattern is formed to have the same height as the surface of the conductive layer pattern or to have a lower height. The method of claim 8, further comprising exposing the undercut insulating layer pattern by etching the spacer and the insulating layer pattern after forming the lower electrode. The semiconductor device of claim 8, further comprising etching the spacer and the insulating layer pattern after forming the lower electrode, but not exposing the undercut insulating layer pattern by leaving a portion of the insulating layer pattern. Capacitor manufacturing method. The method of claim 8, wherein the second etch stop layer pattern is formed of a silicon oxide layer. The method of claim 9, wherein the oxide blocking layer is formed of silicon nitride (Si ₃ N ₄ ). ※ Note: The disclosure is based on the initial application.