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KR970013348A - Capacitor Manufacturing Method of Semiconductor Device - Google Patents

Capacitor Manufacturing Method of Semiconductor Device Download PDF

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Publication number
KR970013348A
KR970013348A KR1019950025725A KR19950025725A KR970013348A KR 970013348 A KR970013348 A KR 970013348A KR 1019950025725 A KR1019950025725 A KR 1019950025725A KR 19950025725 A KR19950025725 A KR 19950025725A KR 970013348 A KR970013348 A KR 970013348A
Authority
KR
South Korea
Prior art keywords
polysilicon
forming
sidewalls
transistor
spacer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1019950025725A
Other languages
Korean (ko)
Inventor
박형무
최원택
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950025725A priority Critical patent/KR970013348A/en
Publication of KR970013348A publication Critical patent/KR970013348A/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/01—Manufacture or treatment
    • H10D1/041—Manufacture or treatment of capacitors having no potential barriers
    • H10D1/042—Manufacture or treatment of capacitors having no potential barriers using deposition processes to form electrode extensions

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

단순한 공정으로 넓은 표면적을 갖는 신규한 커패시터 제조방법을 개시한다. 본 발명은 트랜지스터가 형성된 반도체 기판상에 층간 절연막을 형성하고, 매몰 콘택트 형성전에 확장된 스토리지 노드 면적을 갖기 위하여 상기 층간절연막 상부에 질화막, 전도성을 갖는 제1 폴리실리콘층 및 고온산화막을 순차적으로 형성하는 단계, 사진공정을 이용하여 상기 트랜지스터의 활성영역이 노출될 수 있도록 상기 충돌을 차례로 식각하여 접촉 홀을 형성하는 단계, 상기 접촉 홀에 제2 폴리실리콘을 채우는 단계, 상기 고온산화막을 제거한 후, 노출된 상기 제2 폴리실리콘의 양측벽에 스페이서를 형성하는 단계, 상기 스페이서의 양 측벽에 제3 폴리실리콘 패턴을 형성하는 단계, 상기 스페이서를 제거하고 노출된 제1 폴리실리콘을 원하는 크기로 패터닝하여 상기 제1 폴리실리콘, 제2 폴리실리콘 및 제3 폴리실리콘 패턴으로 이루어진 스토리지 전극을 형성하는 단계로 구성된다.A novel process for producing capacitors having a large surface area in a simple process is disclosed. According to the present invention, an interlayer insulating film is formed on a semiconductor substrate on which a transistor is formed, and a nitride film, a conductive first polysilicon layer, and a high temperature oxide film are sequentially formed on the interlayer insulating film in order to have an extended storage node area before forming a buried contact. Forming a contact hole by sequentially etching the collision so that the active region of the transistor is exposed by using a photo process, filling a second polysilicon into the contact hole, and removing the high temperature oxide film, Forming a spacer on both sidewalls of the exposed second polysilicon, forming a third polysilicon pattern on both sidewalls of the spacer, removing the spacer and patterning the exposed first polysilicon to a desired size A switch consisting of the first polysilicon, the second polysilicon, and the third polysilicon pattern It consists of forming a ridge electrode.

Description

반도체장치의 커패시터 제조방법Capacitor Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도 내지 제6도는 본 발명의 일 실시예에 따른 커패시터 형성방법을 단계별로 순차적으로 도시한 공정단면도이다.1 to 6 are process cross-sectional views sequentially showing a capacitor forming method according to an embodiment of the present invention step by step.

Claims (3)

반도체장치의 커패시터를 제조하는 방법에 있어서, 트랜지스터가 형성된 반도체 기판상에 층간 절연막을 형성하고, 매몰 콘택트 형성전에 확장된 스토리지 노드면적을 갖기 위하여 상기 층간절연막 상부에 질화막, 전도성을 갖는 제1 폴리실리콘층, 및 산화막을 순차적으로 형성하는 단계 : 사진공정을 이용하여 상기 트랜지스터의 활성영역이 노출될 수 있도록 상기 충돌을 식각하여 접촉 홀을 형성하는 단계 : 상기 접촉 홀에 제2 폴리실리콘을 채우는 단계 : 상기 산화막을 제거한 후, 노출된 상기 제2 폴리실리콘의 양측벽에 스페이서를 형성하는 단계 : 상기 스페이서의 양측벽에 제3 폴리실리콘 패턴을 형성하는 단계 : 및 상기 스페이서를 제거하고 노출된 제1 폴리실리콘을 원하는 크기로 패터닝하여 상기 제1 폴리실리콘, 제2 폴리실리콘 및 제3 폴리실리콘 패턴으로 이루어진 스토리지 전극을 형성하는 단계로 이루어진 커패시터 제조방법.A method of manufacturing a capacitor of a semiconductor device, comprising: forming an interlayer insulating film on a semiconductor substrate on which a transistor is formed, and having a nitride film and a conductive first polysilicon on the interlayer insulating film to have an extended storage node area before forming a buried contact. Forming a layer and an oxide film sequentially: forming a contact hole by etching the collision to expose the active region of the transistor using a photo process: filling a second polysilicon into the contact hole: After removing the oxide layer, forming spacers on both sidewalls of the exposed second polysilicon; forming third polysilicon patterns on both sidewalls of the spacers; and removing the spacers and exposing the first polysilicon. Patterning silicon to a desired size allows the first polysilicon, second polysilicon and third pole Capacitor manufacturing method consisting of forming a storage electrode of a silicon pattern. 제1항에 있어서, 상기 스토리지 전극을 형성하는 단계 후, 상기 제1 폴리실리콘 하부의 상기 질화막을 제거하는 단계를 부가하는 것을 특징으로 하는 커패시터 제조방법.The method of claim 1, further comprising removing the nitride film under the first polysilicon after the forming of the storage electrode. 제1항에 있어서, 상기 제3 폴리실리콘 스페이서 형성시, 포토마스크 패터닝을 하지 않고 이방성의 과도식각으로 제1 폴리실리콘까지 식각하여 자기정렬로 스토리지 전극을 형성하는 것을 특징으로 하는 커패시터 제조방법.The method of claim 1, wherein when forming the third polysilicon spacer, the storage electrode is formed by self-alignment by etching up to the first polysilicon by anisotropic transient etching without photomask patterning.
KR1019950025725A 1995-08-21 1995-08-21 Capacitor Manufacturing Method of Semiconductor Device Withdrawn KR970013348A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950025725A KR970013348A (en) 1995-08-21 1995-08-21 Capacitor Manufacturing Method of Semiconductor Device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950025725A KR970013348A (en) 1995-08-21 1995-08-21 Capacitor Manufacturing Method of Semiconductor Device

Publications (1)

Publication Number Publication Date
KR970013348A true KR970013348A (en) 1997-03-29

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950025725A Withdrawn KR970013348A (en) 1995-08-21 1995-08-21 Capacitor Manufacturing Method of Semiconductor Device

Country Status (1)

Country Link
KR (1) KR970013348A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100279876B1 (en) * 1997-05-27 2001-02-01 마쉬 윌리엄 에프 Adhesion Reinforcement Composition and Preparation Method for Water-Based Adhesives

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100279876B1 (en) * 1997-05-27 2001-02-01 마쉬 윌리엄 에프 Adhesion Reinforcement Composition and Preparation Method for Water-Based Adhesives

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Legal Events

Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19950821

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid