KR970031571A

KR970031571A - A TU aligning apparatus using DRAM in a sychronous transmission system

Info

Publication number: KR970031571A
Application number: KR1019950045896A
Authority: KR
Inventors: 곽경갑
Original assignee: 유기범; 대우통신 주식회사
Priority date: 1995-11-30
Filing date: 1995-11-30
Publication date: 1997-06-26
Also published as: KR0153688B1

Abstract

본 발명은 동기식 전송장치에 있어서 DRAM을 이용한 TU신호 정렬장치는 수신된 TU1데이타의 포인터를 처리하여 수신 TUl클럭(Rx TU1 clk) 과 수신 V5클럭 (Rx V5 clk)을 발생하고, TU타입을 판별하기 위한 TU 판별신호를 출력하는 TU1포인터처리부(50); 상기 포인터 처리부(50)로부터 수신 TU1클럭(Rx TU1 clk)과 수신 V5위치 클럭(Rx V5 clk)을 입력받아 TU판별신호(TU_type)에 따라 라이트클럭(write_clk)을 발생하는 라이트 클럭 생성부(52); TU1 데이타를 송신하기 위한 임의의 TU1클럭(Tx TU1 clk)과 수신 V5클럭(Rx V5 clk)을 입력받아 소정 TUG2클럭 이내로, TU판별신호 (TU_type)에 따라 리드클럭(read_clk)과 송신 V5위치클럭(Rx V5 clk)을 발생하는 리드클럭 생성부(54); 및 상기 수신된 TU1데이타중 포인터를 제거한 VC1데이타를 상기 라이트클럭에 따라 저장하고, 상기 리드클럭에 따라 출력하여 TU1 데이타를 재 정렬하는 DRAM(56)으로 구성되어 약 3 TUG2클럭이내로 재정렬할 수 있다.According to the present invention, a TU signal alignment device using DRAM in a synchronous transmission device processes a pointer of received TU1 data to generate a received TUl clock (Rx TU1 clk) and a received V5 clock (Rx V5 clk), and determines the TU type. A TU1 pointer processor (50) for outputting a TU discrimination signal to be used; The write clock generator 52 which receives the received TU1 clock (Rx TU1 clk) and the received V5 position clock (Rx V5 clk) from the pointer processor 50 and generates a write clock (write_clk) according to the TU discrimination signal (TU_type). ); Arbitrary TU1 clock (Tx TU1 clk) and receive V5 clock (Rx V5 clk) for transmitting TU1 data are received within the predetermined TUG2 clock, and according to TU discrimination signal (TU_type), the read clock (read_clk) and the transmit V5 position clock A lead clock generator 54 generating (Rx V5 clk); And a DRAM 56 storing the VC1 data from which the pointer of the received TU1 data is removed according to the write clock, and outputting the VC1 data according to the read clock and realigning the TU1 data within about 3 TUG2 clocks. .

Description

A TU aligning apparatususing DRAM in a synchronous transmission system

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제5도는 본 발명에 따른 정렬장치를 도시한 블럭도이고,5 is a block diagram showing an alignment device according to the present invention,

제6도의 (a) 내지 (j)는 VC12 데이타를 재정렬하는 것을 도시한 타이밍도이다.(A) to (j) of FIG. 6 are timing diagrams showing rearrangement of VC12 data.

Claims

After mapping service data such as DS1 or DS1E signal to VC1, pointer processing is performed to form TU1 signal, TU1 signals are multiplexed to form STM-n synchronous digital level signal or demultiplexed received STM-n signal to TU1 signal In the synchronous transmission device capable of time slot exchange in units of VC1 after being separated into a group, a pointer of received TU1 data is processed to generate a receive TU1 clock (Rx TU1 clk) and a receive V5 clock (Rx V5 clk). A TU1 pointer processing unit 50 for outputting a TU discrimination signal for determining a TU type; A light clock generator 52 which receives a received TU1 click (Rx TU1 clk) and a received V5 position clock (Rx V5 clk) from the pointer processor and generates a light clock (wrtte_clk) according to a TU discrimination signal; Receive arbitrary TU1 clock (Tx TU1 clk) and receive V5 clock (Rx V5 clk) to transmit TU1 data, and within TUG2 clock, lead clock (read_clk) and transmit V5 position clock (Tx V5 clk) according to TU discrimination signal. A lead clock generator 54 generating a); And a DRAM (56) storing VC1 data from which the pointer is removed from the received TU1 data according to the write clock, and outputting the VC1 data according to the read clock and realigning the TU1 data. Signal aligner.

※ Note: The disclosure is based on the initial application.