JPH02119337A - Data transmission/reception equipment - Google Patents

Abstract

PURPOSE:To prevent severe constraint from being applied to the kind of the data transmission speed of a terminal possible to be housed by generating an irregular clock in which the number of change points in a constant time is equal to that of a terminal clock and whose fundamental cycle is integer times the system clock based on the system clock. CONSTITUTION:An irregular clock generation circuit 303 generates the irregular clock by a frame synchronizing signal and the system clock. The irregular clock performs three times of rising change in the eight cycles of the system clock similarly as the terminal clock, and also, the fundamental cycle of the change is set at integer times the system clock. Also, the rising change of the irregular clock is phase-locked with that of the frame synchronizing signal. Therefore, it follows that the data transmission speed from a multiplex separation circuit 201 inputted to a reception buffer memory 202 synchronizing with the irregular clock coincides with that outputted from the reception buffer memory 202 to a reception terminal interface 203 synchronizing with the terminal clock.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transmitting and receiving device that transmits and receives data between terminals via a time division multiplexed bus.

[Conventional technology]

Conventionally, the multiplexing circuit of this type of data transmitting/receiving device has a transmission switch for multiplexing data onto a time division multiplexed bus and speed conversion for converting the speed of data from a terminal to the data speed of the time division multiplexed bus. It has two memories (memory A and memory B), and a demultiplexing circuit demultiplexes data from the time division multiplex bus and converts the data speed of the time division multiplex bus to the data speed to the terminal. Two memories (memory C and memory D) are provided as reception switch memories for conversion and conversion.

The operation of such a conventional data transmitting/receiving device will be explained with reference to FIGS. 3, 4, and 5. FIG. 3 shows an example of memory operation in a multiplexing circuit, FIG. 4 shows an example of memory operation in a demultiplexing circuit, and FIG. 5 shows an example of the timing of each conventional control clock.

In FIG. 3, data is written into the memo IJA and the memo 17B alternately every cycle of the frame synchronization signal.

While memory A is writing data, data is read from memory B, while memory B is writing data, data is read from memory A, and each read data is multiplexed and inserted into a time division multiplex path. In order to phase-synchronize the multiplexing of data onto the time-division multiplex path with the frame synchronization signal, reading data from memory A and memory B is performed in synchronization with a system clock that is phase-synchronized with the frame synchronization signal. On the other hand, data is written to memory A and memory B in synchronization with a terminal clock whose speed is synchronized with the data speed of the terminal. Therefore, as shown in Figure 5, it is necessary to synchronize the phases of the system clock and terminal clock, and to minimize the phase difference between the system clock and terminal clock so that reading and writing to the same memory do not overlap. be.

In FIG. 4, data is written into memory IJC and memory D alternately every cycle of the frame synchronization signal. While memory C is writing data, data is read from memory D, and while memory D is writing data, data is read from memory IJC. As shown in Figure 4, data is separated from the time-division multiplexed path using a system in which the writing of data to the memo IJC and memo IJ is phase-synchronized with the frame synchronization signal, as shown in Figure 4. This is done in synchronization with the clock. On the other hand, data is read from memory C and memory D in synchronization with a terminal clock whose speed is synchronized with the data speed of the terminal.

Therefore, as shown in Figure 5, it is necessary to minimize the phase synchronization between the system clock and the terminal clock, and to minimize the phase difference between the system clock and the terminal clock so that reading and writing do not overlap with each other using the same memory. There is.

As explained above, when a conventional data transmitting/receiving device multiplexes and demultiplexes data onto a time division multiplex path in synchronization with a frame synchronization signal, it uses a terminal clock synchronized with the data transmission rate of the terminal and a time division multiplex path. It is necessary to realize phase synchronization in the device within the data transmitting/receiving circuit with a system clock synchronized in speed with the transmission rate of data passing through the frame synchronization signal and phase synchronized with the frame synchronization signal. Here, when the terminal clock and system clock are high-speed, attempting to supply a terminal clock that is phase-synchronized with the system clock from one terminal clock generation circuit to multiple data transmitting and receiving devices means that the transmission to each data transmitting and receiving circuit is This is difficult due to variations in delay. In order to achieve this relatively easily, as in the case of the terminal clock of 4.096 MHz shown in Figure 5, the frequency of the terminal clock is limited to - an integer of the system clock that is phase-synchronized with the frame synchronization signal. By dividing the clock by an integer, a terminal clock whose phase is synchronized with the frame synchronization signal is generated inside each data transmitting/receiving device. Furthermore, regarding the phase synchronization between the system clock and an integer terminal clock that is an integer fraction of a relatively high-speed system clock, such as the case where the terminal clock is 3.072 MHz as shown in FIG.
There is a configuration in which a highly accurate phase-locked loop oscillator is provided in each data transmitting/receiving device, and this oscillator generates a terminal clock that is phase-synchronized with the system clock.

[Problem to be solved by the invention]

The conventional data transmitting/receiving device described above is used to achieve phase synchronization between the terminal clock and the system clock.

Set the frequency of the terminal clock to an integer fraction of the system clock.
There is a problem in that the types of data transmission speeds of terminals that can be accommodated are severely restricted by limiting the data transmission speed to .

Furthermore, it is not economical because an expensive high-precision phase-locked loop oscillator must be provided in each data transmitting/receiving device to generate a terminal clock having a frequency that is an integer fraction of the system clock in phase synchronization with the system clock.

[Means to solve the problem]

The data transmitting/receiving device of the present invention includes a system clock generation circuit that generates a frame synchronization signal that is phase-synchronized with a system clock, and a terminal clock generation circuit that generates a terminal clock that is synchronized with the data transmission speed of a terminal and frequency-synchronized with the system clock. and an irregular clock generation circuit that generates an irregular clock based on the system clock, the number of changing points in a certain period of time being the same as the terminal clock, and the fundamental period of change being an integral multiple of the system clock;
a transmission buffer memory that accumulates data from a terminal in synchronization with a clock from this terminal and outputs it in synchronization with the irregular clock; and a transmission buffer memory that receives output data of the transmission buffer memory in synchronization with the irregular clock and received data. a multiplexing circuit that inserts data into the time division multiplexed bus in synchronization with the system clock; and a demultiplexer that receives data from the time division multiplexed bus in synchronization with the system clock and outputs it in synchronization with the irregular clock. and a reception buffer memory that stores data from the demultiplexer circuit in synchronization with the irregular clock and outputs it in synchronization with the terminal clock.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

In addition, FIGS. 2, 3, and 4 show the operation l of the same embodiment.
t is a diagram for explaining.

In FIG. 1, 101 is a terminal, 102 is a sending terminal interface, 103 is a sending buffer memo] 104
4 is a multiplexing circuit; 401 and 402 are switch memories (A, B) in the multiplexing circuit 104; 201 is a demultiplexing circuit;
03 and 404 are switch memories (C, D) in the demultiplexing circuit 201, 202 is a reception buffer memory, 203 is a reception terminal interface, 300 is a frame synchronization signal generation circuit, 301 is a terminal clock generation circuit, and 302 is a system clock generation circuit. 303 is an irregular clock generation circuit, and 304 is a time division multiplex bus.

First, generation of various clocks will be explained with reference to FIG. The system clock generation circuit 302 operates at the data rate (8,192 Mbps) of the time division multiplexed bus 304.
System clock (8,192MHz) speed synchronized to
occurs. The frame synchronization signal generation circuit 300 generates a frame synchronization signal (8KHz) phase-synchronized with the system clock.
) occurs. The terminal clock generation circuit 301 is the terminal 10
It generates a terminal clock (3,072 MHz) that is synchronized in speed with the data rate (3,072 Mbps) from 1 and 3/8 of the frequency of the system clock.

However, the terminal clock is not phase synchronized with the system clock because it is difficult to achieve phase synchronization with the system clock. Irregular clock generation circuit 303
generates frame synchronization signals, system clocks, and irregular clocks. As shown in FIG. 2, this irregular clock undergoes three startup changes during eight periods of the system clock, just like the terminal clock, and the basic period of the changes is an integral multiple of the system clock. Further, the irregular clock has a frame synchronization signal and a rising edge change in phase synchronization. Here, the irregular clock is generated by synchronizing the phase with the frame synchronization signal and the system clock because the basic period of the irregular clock is an integral multiple of the system clock, and the system clock that is the source of the irregular clock is the frame synchronization signal. It is easy to realize this because it is phase synchronized with.

Next, data reception by the terminal 101 from the time division multiplexed bus 304 will be explained with reference to FIG.

The demultiplexer circuit 201 synchronizes the data on the time division multiplex bus 304 with the system clock (8,192MHz).
Furthermore, the data is separated in phase synchronization with the frame synchronization signal, and the separated data is outputted to the reception buffer memory 202 in synchronization with the irregular clock. Further, the demultiplexing circuit 201 has a data rate (8,192M) separated from the time division multiplex bus 304.
bps) to the data transmission speed (3,072 Mbps) to the receiving backup memory 202, and two memories, memory C403 and memory D404, are used as switch memories for this separation and speed conversion. has.

As shown in FIG. 4, memory C403 and memory D404
writes data alternately every cycle of the frame synchronization signal. While memory C403 is writing data, memory D4
Also, while the memo 1 JD 404 is writing data, it reads data from the memory C 403, and the read data is output to the reception buffer memory 202 in FIG. 1 as reception data to the terminal 101. To phase-synchronize the separation of data from the time division multiplexed bus 304 to a frame synchronization signal, as shown in FIG.

Data is written to the memo JC 403 and the memory D 404 in synchronization with a system clock whose phase is synchronized with the frame synchronization signal. On the other hand, data reading from the memory C403 and the memo 1JD404 is performed in synchronization with an irregular clock whose phase is synchronized with the frame synchronization signal.
This can be done without overlapping with writing to the same memory. Here, if data is read from the memory C403 and the memory D404 using a terminal clock that is not phase synchronized with the frame synchronization signal, there is a risk that reading and writing in the same memory will overlap. The reception buffer memory 202 stores the data from the demultiplexer circuit 201 in synchronization with an irregular clock, and outputs the stored data as reception data to the terminal 101 to the reception terminal interface 203 in synchronization with the terminal clock. Out of memory. As shown in FIG. 2, the number of changing points during one period of the frame synchronization signal of the terminal clock (3, Q 72 MHz) and the irregular clock is the same.

Therefore, the speed of data from the demultiplexer circuit 201 that is input to the reception buffer memory 202 in synchronization with the irregular clock and the reception buffer memory 202 in synchronization with the terminal clock.
The speed of data output to the receiving terminal interface 203 is the same as that of 02. However, since it is difficult to achieve phase synchronization between the terminal clock and the frame synchronization signal, phase synchronization with the fretome synchronization signal is not achieved. Receiving terminal interface 203 (c) Multiplexes the received data sent from the receiving buffer memo 1J202 to the terminal 101 and the terminal clock, and sends the multiplexed data to the terminal 101.

Next, transmission of data from terminal 101 to time division multiplexed bus 304 will be explained with reference to FIG. Terminal 101
extracts the transmitting terminal clock (3,072 MHz) from the data received from the receiving terminal interface 203. Therefore, although the transmitting terminal clock is not phase synchronized with the system clock, it is 3/8 frequency synchronized. Terminal 101 multiplexes the transmitting terminal clock and transmission data and sends the multiplexed data to transmitting terminal interface 102. Sending terminal interface 102 DI terminal 1
The transmitting terminal clock sent from 01 and the transmitting data are separated. The transmission buffer memory 103 receives and stores data from the transmission terminal interface 102 in synchronization with the transmission terminal clock. The transmission buffer memory 103 is a first-in-first-out memory that stores data from the transmission terminal interface 102 in synchronization with the transmission terminal clock and outputs the stored data in synchronization with an irregular clock. As shown in FIG. 2, the number of changing points during one period of the frame synchronization signal of the transmitting terminal clock (3,072 MHz) and the irregular clock is the same. However, since it is difficult to achieve phase synchronization between the transmitting terminal clock and the data from the terminal 101 with respect to the frame synchronization signal, phase synchronization with the frame synchronization signal is not achieved. However, data from the terminal 101 that is not phase-synchronized with the frame synchronization signal is
3. Phase synchronization with the frame synchronization signal is achieved at the time of output in synchronization with the irregular clock, and the transmission rate of the output data becomes the same as that of the transmitting terminal clock.

This is because the transmitting terminal clock is sent from the terminal clock generation circuit 301 to the terminal 101 via the receiving terminal interface 203, is extracted by the terminal 101, and is extracted by the terminal 101.
This is because the clock is multiplexed into the transmission data from 01 and arrives at the transmitting terminal interface 102 again, where the clock is extracted. Therefore, the transmitting terminal clock and the irregular clock are completely synchronized in frequency with a 1=1 relationship, and data underrun (data shortage) or overrun (data overflow) in the transmission buffer memory 103 occurs.
does not occur. The multiplexing circuit 104 receives data from the transmission buffer memory 103 in synchronization with an irregular clock,
The received data is multiplexed onto the time division multiplex bus 304 in synchronization with the system clock and phase synchronization with the frame synchronization signal. The multiplexing circuit 104 also includes the transmission buffer memory 1
03 (3,072 Mbps) to the data speed of the time division multiplexed bus 304 (8,192 Mbps)
), and includes two memories, memory A401 and memory B4O2, as switch memories for multiplexing and speed conversion. As shown in FIG. 3, data is written alternately into the memory A401 and memory B4O2 every cycle of the frame synchronization signal.

While memory A401 is writing data, data is read from memory B402, and while memory B402 is writing data, data is read from memory A401, and each read data is multiplexed and inserted into hour/minute side line 1 bus 304. . Data is multiplexed onto the time division multiplex bus 304 as shown in FIG.

In order to synchronize the phase with the frame synchronization signal, memory A40
Reading of data from memory B4O2 and memory B4O2 is performed in synchronization with a system clock whose phase is synchronized with the frame synchronization signal. Meanwhile, Memory Person 401 and Memo! JB40
Since writing to memory 2 is performed in synchronization with an irregular clock that is phase-synchronized with the frame synchronization signal, it can be performed without overlapping with reading from the same memory. On the other hand, memo! 7A401 and memo! If writing to JB4O2 is performed using a terminal clock that is not phase synchronized with the frame synchronization signal, there is a risk that reading and writing in the same memory will overlap.

As described above, the data transmitting/receiving apparatus of this embodiment accommodates a terminal having a data transmission rate of 3/8 of the system clock, and multiplexes and demultiplexes data onto the time division multiplexed bus 304 using the system clock and frame synchronization signals. This can be done in sync with the

Note that in the above embodiment, the system clock is 8.1
Although the case where the frequency is 92 MHz and the terminal clock is 3.072 MHz has been described, data transmission and reception can be performed in the same manner as in 1 using clocks of other frequencies.

〔Effect of the invention〕

As explained above, according to the present invention, the number of change points in a certain period of time is the same as the terminal clock synchronized with the data transmission rate of the terminal, and the basic period of change is an integral multiple of the system clock synchronized in phase with the frame synchronization signal. In addition, by using an irregular clock that is phase-synchronized with the frame synchronization signal, it is possible to accommodate terminals with transmission speeds not only of an integer fraction of the system clock, but also of an integer fraction of the system clock, and to multiplex data onto a time division multiplex bus. It is economically possible to perform the separation in synchronization with the system clock and frame synchronization signal.

FIG. 4 is a diagram showing an example of the operation of a memory in a demultiplexing circuit, and FIG. 5 is a diagram showing an example of the timing of each clock in a conventional example.

101...Terminal, 102...Sending terminal interface, 103...Sending buffer memo! J, 104...
・Multiplex circuit, 201... Demultiplex circuit, 2o2...
・Reception buffer memory lJ, 203...Reception terminal interface, 300...Frame synchronization signal generation circuit,
301...Terminal clock generation circuit, 302...System clock generation circuit, 303...Irregular clock generation circuit.

304...Time division multiplexed bus, 401...Memory A,
402...Memory B, 403...Memory C, 404
...Memory D0

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the timing of each clock in the same embodiment, and FIG. 3 is a diagram showing the operation of memory in a multiplexing circuit. times

Claims (1)

[Claims] A system clock generation circuit that generates a frame synchronization signal that is phase-synchronized with the system clock; a terminal clock generation circuit that generates a terminal clock that is synchronized with the data transmission speed of the terminal and frequency-synchronized with the system clock; and a fixed time change point. an irregular clock generation circuit that generates an irregular clock based on the system clock, the number of which is the same as that of the terminal clock, and whose basic cycle of change is an integral multiple of the system clock; a transmission buffer memory that stores data in synchronization with the system clock and outputs data in synchronization with the irregular clock; a multiplexing circuit inserted into the division multiplexed bus; a multiplexing and demultiplexing circuit that receives data from the time division multiplexed bus in synchronization with the system clock and outputs it in synchronization with the irregular clock; and data from the multiplexing and demultiplexing circuit. A data transmitting/receiving device comprising: a receiving buffer memory that accumulates in synchronization with the irregular clock and outputs in synchronization with the terminal clock.