KR970024188A - Word line manufacturing method of semiconductor device - Google Patents
Word line manufacturing method of semiconductor device Download PDFInfo
- Publication number
- KR970024188A KR970024188A KR1019950037052A KR19950037052A KR970024188A KR 970024188 A KR970024188 A KR 970024188A KR 1019950037052 A KR1019950037052 A KR 1019950037052A KR 19950037052 A KR19950037052 A KR 19950037052A KR 970024188 A KR970024188 A KR 970024188A
- Authority
- KR
- South Korea
- Prior art keywords
- word line
- forming
- moved
- conductive layer
- semiconductor device
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/14—Word line organisation; Word line lay-out
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체소자의 워드선 제조방법에 관한 것으로, Z자형 활성영역을 갖는 비대칭 메모리 단위 셀 구조에서 소자분리 산화막의 경계 부분에서의 난반사에 의한 워드선의 왜곡 정도를 보상해주는 방법으로서, 난반사로 변형되는 정도 만큼 양쪽 워드선을 상·하로 이동시켜 워드선의 중심점을 콘택의 중심점과 일치되도록하였으므로, 워드선 형성이 용이하고, 주변의 기타 층들과의 공정마진 여유도가 증가되어 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a word line of a semiconductor device. A method for compensating the degree of distortion of a word line due to diffuse reflection at the boundary of an isolation oxide layer in an asymmetric memory unit cell structure having a Z-shaped active region. By moving both word lines up and down as much as possible to make the center point of the word line coincide with the center point of the contact, it is easy to form the word line, and the margin of process margin with other layers around it is increased, resulting in process yield and device operation. Reliability can be improved.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제4도는 본 발명에 따른 반도체소자의 설계 레이아웃도.4 is a design layout diagram of a semiconductor device according to the present invention.
Claims (3)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950037052A KR0169598B1 (en) | 1995-10-25 | 1995-10-25 | Process of manufacturing semiconductor device word line |
JP8246675A JP2850879B2 (en) | 1995-09-18 | 1996-09-18 | Semiconductor device word line manufacturing method |
US08/715,631 US5834161A (en) | 1995-09-18 | 1996-09-18 | Method for fabricating word lines of a semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950037052A KR0169598B1 (en) | 1995-10-25 | 1995-10-25 | Process of manufacturing semiconductor device word line |
Publications (2)
Publication Number | Publication Date |
---|---|
KR970024188A true KR970024188A (en) | 1997-05-30 |
KR0169598B1 KR0169598B1 (en) | 1999-01-15 |
Family
ID=19431246
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950037052A KR0169598B1 (en) | 1995-09-18 | 1995-10-25 | Process of manufacturing semiconductor device word line |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR0169598B1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111653563A (en) * | 2020-05-28 | 2020-09-11 | 福建省晋华集成电路有限公司 | Layout structure of dynamic random access memory and manufacturing method of photomask |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100431323B1 (en) * | 1997-11-01 | 2004-06-16 | 주식회사 하이닉스반도체 | Exposure mask |
KR102037063B1 (en) | 2013-03-15 | 2019-11-26 | 삼성전자주식회사 | Semiconductor Devices and methods of manufacturing the same |
-
1995
- 1995-10-25 KR KR1019950037052A patent/KR0169598B1/en not_active IP Right Cessation
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111653563A (en) * | 2020-05-28 | 2020-09-11 | 福建省晋华集成电路有限公司 | Layout structure of dynamic random access memory and manufacturing method of photomask |
CN111653563B (en) * | 2020-05-28 | 2022-03-04 | 福建省晋华集成电路有限公司 | Layout structure of dynamic random access memory and manufacturing method of photomask |
Also Published As
Publication number | Publication date |
---|---|
KR0169598B1 (en) | 1999-01-15 |
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Payment date: 20081006 Year of fee payment: 11 |
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