KR970010155B1 - Apparatus for controlling command signal in the wide range communication card - Google Patents

Abstract

If command input C1 puts on "1" among command input(C0,C1,C2,C3) and control signal "STRB" puts on low-high-low, starting signal(TT) of cell is inserted automatically, and if command input(C0,C1,C2,C3) all put on "0" and control signal "STRB" does low, synchronous signal(JK) is inserted automatically. Also, in case of transfer of data, command input(C0,C1,C2,C3) all put on "0" and control signal "STRB" does low-high-low. If data is recorded on transfer FIFO, CELCNTEN signal converts from low to high, so that 54 event counter(7) is operated.

Description

Command signal control device of wide area communication card

1 is a schematic diagram illustrating one embodiment of a data format used in airspace communication.

2 is a circuit diagram showing an embodiment of a command signal control apparatus for a wide area communication card according to the present invention.

3 is a timing diagram showing each signal according to FIG.

* Explanation of symbols for main parts of the drawings

1, 2, 9: D flip-flop 3: Signal detector

4, 5: first and second counters 6: negative logic circuit

7: 54 event counter 8, 10: negative logic circuit

11: shift register 12, 16, 17: negative logic circuit

13, 18: logical sum circuit 14, 15: logical multiplication circuit

19: signal generator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a taxi chip widely used for wide range communication. In particular, a command of a wide range communication card suitable for transmitting data at high speed is provided. The present invention relates to a signal control device.

Workstation adopts a top-down design method that can be used easily and conveniently from the user's point of view, and the computer assists the user so that it does not take much effort to acquire the function when the user uses the workstation. It is also called a desktop computer because it realizes the user's working environment as it is.

In addition, it realizes a highly human-machine interface, performs work through dialogue processing by display, and input device equipped with high speed computing device, high resolution display, keyboard and mouse. It has a network function, and is composed of software and hardware that operate as a set of processes.

In this regard, an asynchronous transfer mode cell in which a wide area communication is based on a wide area communication card inserted into an SBus expansion slot of a conventional workstation, that is, a 140 Mbps wide area communication card using a taxi chip ( Wide area communication card that transmits data according to cell) transmits data according to the transmitted cell in 8-bit byte unit on taxi chip by first-in first-out (FIFO) method. Send it to the other party's system.

In this case, the data format according to the asynchronous transmission mode cell used in the wide area communication is 53 bytes as shown in FIG. 1, and a start of cell signal (TT) of the cell is transmitted first, followed by 53 bytes of asynchronous. Transmission mode has a form in which data according to a cell is transmitted.

Here, asynchronous transmission refers to a method of transmitting one data at a time in data transmission. Therefore, a circuit for controlling the transmission of the start signal TT of the cell prior to data transmission according to the asynchronous transmission mode cell is needed.

In addition, when there is no data to be transmitted, the synchronization signal JK must be transmitted to maintain synchronization between the transmission and reception, and thus a circuit for controlling the synchronization signal JK is also required.

However, in this conventional technique, since a command signal such as a start signal TT and a synchronization signal JK of a cell is controlled by a central processing unit (CPU), data cannot be transmitted at a relatively high speed.

The present invention has been made to solve such a conventional problem, to provide a command signal control apparatus for a wide area communication card to configure a separate circuit for controlling the command signal of the taxi chip to transmit data at high speed. The purpose is.

In order to achieve the above object, the present invention records the data according to the asynchronous transmission mode cell to be transmitted by the system to the transmission first-in-first-out (memory that inputs and outputs the data in the first-in-first-out manner). The signal detection unit detects the CELCNTEN signal generated by the TXCLK signal and outputs the detected CELCNTEN signal, and the signal detection unit 53-5-1-2 outputs the signal value according to the TXCLK signal. -3-.. -50-51-52-53-0-... As the count value goes from 53 to 0, the / TXC1 signal for transmitting the cell's start signal (TT) is outputted, and each time the / TXC1 signal is output, it resets itself by the / TXC1 signal. It outputs the CELCLR signal synchronized with the / TXCLK signal according to the internal clock / TXCLK signal and / RS-PWR signal by receiving the 54 Event counter and the / TXC1 signal of the 54 event counter. Delay Flip Flop, the CELCLR signal of the D flip-flop, the / TXC1 signal of the 54 event counter, the output of the signal detector and the / RDFIFO1 signal for reading the transmission FIFO1 by receiving the / TXCLK signal, The / RDFIFO2 signal for reading the transmission FIFO2, the / RFFIFO3 signal for reading the transmission FIFO3, the / RDFIFO4 signal for reading the transmission FIFO4, the STRB signal for timing the data, and the timing of the synchronization signal (JK). STRB-SYNC signal to grab and The parts made of the signal generating and outputting a STRB-DATA signal to capture the timing of the data songhal characterized.

The signal detection unit may include a D flip-flop for passing a CELCNTEN signal according to a TXCLK signal, and a D flip-flop for passing an output of the D flip-flop according to a TXCLK signal.

In addition, the 54 event counter has a first counter that counts to a decimal value according to the signal detection unit after the count value is initialized to 2, and each time the count value of the first counter reaches 10 when the count value is initialized to 5; A second counter that counts according to the signal of the first counter, and a signal applied by the first and second counters are subjected to a negative AND operation to apply a / TXC1 signal to the first counter whenever the counter value becomes 53 to 0. Characterized in that it consists of a negative logical product circuit that causes the counter to be reset (Reset).

Next, the signal generator shifts the data to sequentially output the last shifted data every four clocks by the / TXCLK signal, and outputs the signals / RDFIFO1, / RDFIFO2, / RDFIFO3, and / RDFIFO4. ), A negative OR circuit that performs an NOR operation on the output of the shift register and uses the input of the shift register to shift the data, and the / RDFIFO1, / RDFIFO2, / RDFIFO3, / RDFIFO4 signals of the shift register. Logic multiplication circuit for multiplying, NOR circuit for outputting logical multiplication circuit and / TXCLK signal, and outputting STRB-DATA signal, and STRB with negative logical sum operation of / TXCLK signal and CELCLR signal of D flip-flop A negative sum circuit for outputting a SYNC signal, a logical sum circuit for performing an OR operation on the outputs of the two negative logic sum circuits, and an STRB signal for outputting a STRB signal; , Logic for ORing the / TXC1 signal of the event counter and the output of the negative OR circuit, and performing an AND operation on the output of the OR circuit and the output of the signal detector and applying a signal according to the AND operation to the shift register. It is characterized by consisting of a multiplication circuit.

Hereinafter, described in detail by the accompanying drawings an embodiment of the present invention as follows.

2 is a circuit diagram showing an embodiment of a command signal control apparatus for a wide area communication card according to the present invention, in which a system (not shown) transmits data according to an asynchronous transfer mode cell to which an SBus interface (not shown) is transmitted. Signal detection unit 3 which detects the CELCNTEN signal according to the TXCLK signal and outputs the detected CELCNTEN signal according to the TXCLK signal through the recording FIFO (not shown in the drawing), and the coefficient value is initialized to 52. Then, the signal of the signal detection unit 3 is set to 53-0-1-2-3-... According to the TXCLK signal. -50-51-52-53-0-... As the count value goes from 53 to 0, the / TXC1 signal for transmitting the cell's start signal (TT) is outputted, and each time the / TXC1 signal is output, it resets itself by the / TXC1 signal. A 54 event counter 7 for reset and a / TXC1 signal from the 54 event counter 7 are output to output a CELCLR signal synchronized with the / TXCLK signal according to the internal clock / TXCLK signal and / RS-PWR signal. The transfer FIFO1 is read by receiving the D flip-flop 9, the CELCLR signal of the D flip-flop 9, the / TXC1 signal of the 54 event counter 7, the output of the signal detector 3, and the / TXCLK signal. / RDFIFO1 signal to read, / RDFIFO2 signal to read the transmission FIFO2, / RDFIFO3 signal to read the transmission FIFO3, / RDFIFO4 signal to read the transmission FIFO4, STRB signal to time the data, synchronization signal (JK) STRB-SYNC signal for timing of data and other data DATA-made for STRB signal for catching the humming in the signal generating section 19 to output.

Here, the signal detector 3 includes a D flip-flop 1 for passing a CELCNTEN signal according to the TXCLK signal, and a D flip-flop 2 for passing the output of the D flip-flop 1 according to the TXCLK signal.

In addition, the 54 event counter 7 has a first counter 4 which is initialized to 2 after the count value is initialized to 2, and the counter value is initialized to 5, and the count value is initialized to 5. When the count value of the counter 4 becomes 10, the second counter 5 counting according to the signal of the first counter 4 and the signals of the first and second counters 4 and 5 are applied to the negative logic. Each time the product is multiplied by 53 to 0, a negative logic circuit 6 is applied to the first counter 4 so that the first counter 4 is reset.

Next, the signal generator 19 shifts the data to sequentially output the last shifted data every four clocks by the / TXCLK signal, and outputs the signals / RDFIFO1, / RDFIFO2, / RDFIFO3, and / RDFIFO4. 11) a negative-OR circuit 12 for performing an NOR operation on the output of the shift register 11 and using the input of the shift register 11 to cause the shift register 11 to shift data; and the shift register 11 Outputs the STRB-DATA signal by performing an AND logic operation on the logical AND circuit (15), which performs an AND operation on the / RDFIFO1, / RDFIFO2, / RDFIFO3, / RDFIFO4 signals, A negative logic sum circuit 17, a negative logic sum circuit 16 that outputs a STRB-SYNC signal by performing a negative logic sum operation on the / TXCLK signal and the CELCLR signal of the D flip-flop 9, and the negative logic sum circuits 16 and 17. Boolean OR operation of output of STRB signal A logic sum circuit 18 for outputting, a logic sum circuit 13 for performing an OR operation on the / TXC1 signal of the 54 event counter 7, and the output of the negative logic sum circuit 16, and an output and signal detection unit of the logic sum circuit 13 ( It consists of an AND circuit 14 which performs an AND operation on the output of 3) and applies a signal according to the AND operation to the shift register 11.

According to the present invention thus made, first, the taxi chip Am7968 (not shown in the drawing) has a command input C1 of 1 among the command inputs C0, C1, C2, and C3 and the control signal STRB low-high-low. In this case, the start signal TT of the cell is automatically inserted, and the synchronization signal JK is automatically inserted when the command inputs C0, C1, C2, and C3 are all set to 0 and the control signal STRB is set low.

In the case of data transmission, the control signal STRB can be made low-high while the command inputs C0, C1, C2, and C3 are all zero.

Then, when data is written to the transmit FIFO, the CELCNTEN signal goes from low to high and accordingly the 54 event counter 7 starts counting.

Here, the 54 event counter 7 is initialized to 52, but when the first clock comes in immediately after the CELCNTEN signal becomes high, it becomes 53. At this time, a control signal for inserting the start signal TT of the cell is made, and the cell Since the start signal TT is the start of cell transmission, the 54 event counter 7 is reset.

Referring to FIG. 3, first, the signal detector 3 records a CELCNTEN signal as shown in FIG. 3A by writing data corresponding to an asynchronous transmission mode cell transmitted by the system to a transmission FIFO through the SBus interface. Is detected according to the TXCLK signal as shown in FIG. 3C, and the CELENTEN signal as shown in FIG.

The next 54 event counter 7 initializes the count value to 52 and then resets the signal of the signal detector 3 to 53-0-1-2-3-... According to the TXCLK signal as shown in FIG. -50-51-52-53-0-... As the count value goes from 53 to 0, outputs the / TXC1 signal as shown in FIG. 3 (H) for transmitting the start signal (TT) of the cell, and / as shown in FIG. Each time the TXC1 signal is output, it resets itself by the / TXC1 signal as shown in FIG.

At this time, the negative logic circuit 8 performs a negative logic operation on the / TXC1 signal as shown in FIG. 3 (H) of the 54 event counter 7 and outputs a TXC1 signal like as shown in FIG. 3 (G). 10) performs a negative logic operation on the TXCLK signal as shown in FIG. 3C to output the internal clock / TXCLK signal.

Subsequently, the D flip-flop 9 receives the / TXC1 signal as shown in FIG. 3 (H) of the 54 event counter 7 to the internal clock / TXCLK signal and the / RS-PWR signal as shown in FIG. 3 (B). Therefore, the CELCLR signal as shown in FIG. 3 (I) synchronized with the internal clock / TXCLK signal is output.

The signal generator 19 is a CELCLR signal of the D flip-flop 9 as shown in FIG. 3 (I), a / TXC1 signal of the 54 event counter 7 as shown in FIG. 3 (H), and a signal detector 3 And the / RDFIFO1 signal as shown in FIG. 3 (J) for reading the transmission FIFO1 by receiving the / TXCLK signal, which is the output of the negative logic circuit 10, and the third diagram (K) for reading the transmission FIFO2 and / RDFIFO2 signal, such as FIG. 3 (L) for reading the transmission FIFO3, / RDFIFO3 signal, such as FIG. 3 (M) for reading the transmission FIFO4, FIG. 3, for timing data. STRB signal as shown in (D), STRB-SYNC signal as shown in FIG. 3E for timing the synchronization signal JK, and STRB-DATA signal as shown in FIG. 3 as F for timing the data to be transmitted. Outputs

Here, the D flip-flop 1 of the signal detector 3 passes the CELCNTEN signal as shown in FIG. 3A as the TXCLK signal as shown in FIG. (2) passes the output of the D flip-flop 1 as the TXCLK signal as shown in FIG. 3 (C) goes from low to high as in the case of the D flip-flop (1).

Further, the first counter 4 of the 54 event counter 7 counts as the power supply Vcc and ground GND are connected to the terminals B, ENT, END and terminals A, C, and D, respectively. When the value is initialized to 2 and then the decimal value is counted according to the signal of the signal detection unit 3, when the count value becomes 10, the signal is output to the terminal RCO. The second counter 5 supplies the power supply Vcc and ground. As GND is connected to terminals A, C, and END and terminals B and D, respectively, the count value is initialized to 5, and the first counter counts each time the count value of the first counter 4 becomes 10. The signal is applied to the terminal ENT from the terminal RCO of (4) and counted, and the negative AND circuit 6 receives the output signals of the first and second counters 4 and 5 to perform an AND logic operation. Whenever the count value goes from 53 to 0, that is, when all four inputs are high, the / TXC1 signal as shown in FIG. 3 (H) is applied to the terminal (/ CLRN) of the first (4). 4) is reset.

Next, the shift register 11 of the signal generator 19 shifts the data according to the terminals 1D, 2D, 3D, and 4D and finally shifts the data every four clocks by the / TXCLK signal applied to the terminal CLK. Are sequentially outputted to each terminal (1QN, 2QN, 3QN, 4QN), / RDFIFO1 as shown in FIG. 3 (J), / RDFIFO2 as shown in FIG. 3 (K), / RDFIFO3 as shown in FIG. 3 (L) The / RDFIFO4 signal as shown in FIG. 3 (M) is output, respectively, and the NOR circuit 12 performs an NOR operation on the outputs 1Q, 2Q, and 3Q of the shift register 11, and Used as an input 1D, the shift register 11 shifts the data 1D, 2D, 3D, and 4D.

Subsequently, the logical AND circuit 15 includes / RDFIFO1 as shown in FIG. 3 (J) of the shift register 11, / RDFIFO2 as shown in FIG. 3 (K), / RDFIFO3 as shown in FIG. The logical AND operation of the / RDFIFO4 signal as shown in FIG. M is performed, and the negative logical sum circuit 17 performs an AND logic operation on the output of the logical AND circuit 15 and the / TXCLK signal to generate the STRB-DATA as shown in FIG. The negative logic circuit 16 outputs a negative signal by performing a negative-OR operation on the / TXCLK signal and the CELCLR signal as shown in FIG. 3 (I) of the D flip-flop 9, and the STRB-SYNC signal as shown in FIG. 3 (E). Outputs

In addition, the OR circuit 18 performs an OR operation on the outputs of the NOR circuits 16 and 17 and outputs an STRB signal as shown in FIG. 3D. The OR circuit 13 performs the operation of the 54 event counter 7. The / TXC1 signal such as 3 degrees (H) and the output of the negative logic sum circuit 16 are ORed, and the AND product 14 is the output of the logic sum circuit 13 and the D flip-flop 2 of the signal detector 3. The AND output is applied to the shift register 11 to apply a signal corresponding to the AND operation.

As described above, the present invention implements a separate logic circuit for controlling the command signal of the taxi chip, thereby controlling the command signal of the taxi chip such as the synchronous signal JK of the asynchronous transmission mode cell and the start signal TT of the cell. There is an effect that can be transmitted at high speed without a processing device.

Claims (5)

A signal detector (3) for detecting the CELCNTEN signal according to the TXCLK signal by writing data in the asynchronous transmission mode cell to be transmitted to the transmission FIFO and outputting the detected CELCNTEN signal; The count value is initialized to 52, and the signal of the signal detector 3 is counted according to the TXCLK signal, and the count value is changed from 53 to 0 so that the / TXC1 signal for transmitting the start signal TT of the cell is output. A 54 event counter 7 which resets itself by the / TXC1 signal whenever the / TXC1 signal is output; A negative logic circuit (10) receiving the TXCLK signal and performing a negative logic operation to output an internal clock / TXCLK signal; The D flip-flop which receives the / TXC1 signal of the 54 event counter 7 and outputs a CELCLR signal synchronized with the / TXCLK signal according to the internal clock / TXCLK signal and / RS-PWR signal of the negative logic circuit 10. (9); The transmission FIFO1 is read by receiving the CELCLR signal of the D flip-flop 9, the / TXC1 signal of the 54 event counter 7, the output of the signal detector 3, and the / TXCLK signal of the negative logic circuit 10. / RDFIFO1 signal to read, / RDFIFO2 signal to read the transmission FIFO2, / RDFIFO3 signal to read the transmission FIFO3, / RDFIFO4 signal to read the transmission FIFO4, STRB signal to time the data, synchronization signal (JK) And a signal generator (19) for outputting a STRB-SYNC signal for timing the data and a STRB-DATA signal for timing the data to be transmitted. 2. The apparatus of claim 1, wherein the signal detector (3) comprises: a D flip-flop (1) for passing a CELCNTEN signal according to a TXCLK signal; And a D flip-flop (2) for passing the output of the D flip-flop (1) according to the TXCLK signal. 5. The apparatus according to claim 1, wherein said 54 event counter (7) comprises: a first counter (4) for initializing the count value to 2 and performing a decimal count according to the signal of the signal detector (3); A second counter 5 which is initialized to 5 and counts according to the signal of the first counter 4 whenever the counter value of the first counter 4 becomes 10; Receives the signals of the first and second counters 4 and 5 and performs an AND logic operation to apply a / TXC1 signal to the first counter 4 whenever the coefficient value is changed from 53 to 0. A command signal control apparatus for a wide area communication card comprising a negative logical product circuit (6) for resetting the signal. The signal generator 19 sequentially shifts data and sequentially outputs data which is finally shifted every four clocks by the / TXCLK signal of the negative logic circuit 10, and the signals / RDFIFO1, / RDFIFO2, and /. A shift register 11 for outputting the RDFIFO3 and / RDFIFO4 signals; A negative logic sum circuit (12) for negating the OR of the output of the shift register (11) to use the input of the shift register (11) to cause the shift register (11) to shift data; An AND circuit 15 for performing an AND operation on the / RDFIFO1, / RDFIFO2, / RDFIFO3, and / RDFIFO4 signals of the shift register 11; A negative logic sum circuit (17) for outputting a STRB-DATA signal by performing a negative logic OR operation on the output of the logical AND circuit (15) and the / TXCLK signal of the negative logic circuit (10); A negative logic sum circuit (16) for negative logic sum operation of the / TXCLK signal of the negative logic circuit (10) and the CELCLR signal of the D flip-flop (9) to output a STRB-SYNC signal; A logic sum circuit (18) for performing an OR operation on the outputs of the negative logic sum circuits (16, 17) to output a STRB signal; A logic sum circuit (13) for ORing the / TXC1 signal of the 54 event counter (7) and the output of the negative logic sum circuit (16); And a logical multiplication circuit (14) which logically multiplies the output of the logical sum circuit (13) and the output of the signal detection unit (3) and applies a signal corresponding to the logical multiplication operation to the shift register (11). Command signal control device. 2. The apparatus of claim 1, further comprising a negative logic circuit (8) for negative logic operation on the / TXC1 signal of said 54 event counter (7) to output a TXC1 signal.