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KR970007111B1 - Isoating method of integrated circuit - Google Patents

Isoating method of integrated circuit Download PDF

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Publication number
KR970007111B1
KR970007111B1 KR1019880015690A KR880015690A KR970007111B1 KR 970007111 B1 KR970007111 B1 KR 970007111B1 KR 1019880015690 A KR1019880015690 A KR 1019880015690A KR 880015690 A KR880015690 A KR 880015690A KR 970007111 B1 KR970007111 B1 KR 970007111B1
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South Korea
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device isolation
forming
oxide film
integrated circuit
buried oxide
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KR1019880015690A
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Korean (ko)
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KR900008639A (en
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류시봉
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엘지반도체 주식회사
문정환
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

An isolating method of semiconductor IC's(Integrated Circuits) is provided to simplify the processes. The isolating method comprises the steps of: forming a buried oxide layer(2) by ion-implanting an oxygen ions into a silicon substrate(1); forming a thermal oxide pattern(3) on the buried oxide layer(2); ion-implanting oxygen ions to the exposed buried oxide layer(2) using the thermal oxide pattern(3) as a mask; and annealing the implanted substrate of oxygen ions, thereby forming an isolating oxide(4) for isolating the devices.

Description

반도체 집적회로의 소자 격리 방법Device Isolation Method of Semiconductor Integrated Circuits

제1도는 종래의 소자 격리 방법을 나타낸 공정 단면도.1 is a process cross-sectional view showing a conventional device isolation method.

제2도는 본 발명에 따른 소자 격리 방법을 나타낸 공정 단면도.2 is a process cross-sectional view showing a device isolation method according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 기판 2, 3, 4 : 산화막1: substrate 2, 3, 4: oxide film

본 발명은 반도체 접적회로 제조공정에 관한 것으로, 특히 공정을 단순화하고 소자 격리 특성을 향상시키는데 적당하도록 한 반도체 집적회로의 소자 격리 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit fabrication process, and more particularly, to a device isolation method of a semiconductor integrated circuit adapted to simplify the process and improve device isolation characteristics.

종래의 반도체 제조 방법 중 소자 격리 방법은 여러 가지가 알려져 있으나 대표적인 방법으로는 제1도와 같이 소자 격리 영역에 산화막을 형성하여 각각의 소자들을 격리하는 방법이 있다.Although a number of device isolation methods are known in the related art, there is a method of isolating individual devices by forming an oxide film in the device isolation region as shown in FIG. 1.

이하, 첨부된 도면을 참고하여 종래 기술의 소자 격리 공정에 관하여 설명하면 다음과 같다.Hereinafter, a device isolation process according to the related art will be described with reference to the accompanying drawings.

제1도는 종래 기술의 소자 격리 방법을 나타낸 공정 단면도이다.1 is a process sectional view showing a device isolation method of the prior art.

먼저, 제1도(a)와 같이, 실리콘 기판(1)에 높은 에너지의 산소 주입 공정을 하여 제1도(b)와 같이 실리콘 기판(1) 내의 일정 깊이에 매몰산화막(2)을 형성한다.First, as shown in FIG. 1A, a high energy oxygen injection process is performed on the silicon substrate 1 to form a buried oxide film 2 at a predetermined depth in the silicon substrate 1 as shown in FIG. 1B. .

그리고 제1도(c)와 같이, 열산화 공정을 하여 실리콘 기판(1)의 표면에 산화막(3)을 형성시키고 소자 격리 영역의 산화막(3)이 제거되도록 패터닝한다.Then, as shown in FIG. 1C, an oxide film 3 is formed on the surface of the silicon substrate 1 by a thermal oxidation process and patterned so that the oxide film 3 in the device isolation region is removed.

이어, 패터닝 되어진 상기의 산화막(3)을 마스크로 하여 제1도(d)와 같이, 건식 식각법을 이용하여 매몰산화막(2)이 노출되도록 소자 격리 영역의 실리콘 기판(1)을 식각한다.Subsequently, using the patterned oxide film 3 as a mask, the silicon substrate 1 in the device isolation region is etched to expose the buried oxide film 2 by dry etching as shown in FIG.

그리고 제1도(e)와 같이, 실리콘 기판(1)이 식각되어진 소자 격리 영역에 CVD공정으로 산화규소(4)를 다시 채워서 소자 격리층을 형성하고 후속되는 반도체 제조공정을 진행하였다.As shown in FIG. 1E, the silicon oxide 4 is refilled by the CVD process in the device isolation region where the silicon substrate 1 is etched to form the device isolation layer, and the subsequent semiconductor manufacturing process is performed.

그러나 상기와 같은 종래의 소자 격리 방법에 의하면 건식 식각법에 의한 실리콘 기판의 식각공정과, 상기의 식각공정에 의한 식각부분에 산화규소 물질을 충전하는 과정에 많은 시간이 소요되었으며, 건식식각장비 및 CVD장비 등 여러 가지 기구를 필요로 하는 단점이 있었다.However, according to the conventional device isolation method as described above, the etching process of the silicon substrate by the dry etching method and the process of filling the silicon oxide material into the etching portion by the etching process have been time consuming. There are disadvantages that require various instruments such as CVD equipment.

또한 CVD에 의하여 충전된 산화규소가 기판 표면 밖으로 밀려나와 소자 격리 후에 이것을 제거하는 평탄화 공정을 해야 하는 등 공정에 어려움이 많았다.In addition, the silicon oxide filled by the CVD is pushed out of the substrate surface, and the process has been difficult, such as a planarization process to remove it after device isolation.

본 발명은 상기한 문제점을 해결하기 위하여 안출한 것으로, 실리콘 기판을 식각함이 없이 산소주입법에 의하여 산화막을 형성함으로써 종래의 방법에 의하여 제조공정이 훨씬 간단한 반도체 집적회로의 소자 격리 방법을 제공하고자 한 것이다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides an element isolation method of a semiconductor integrated circuit, which is much simpler in manufacturing process by a conventional method by forming an oxide film by oxygen injection without etching a silicon substrate. will be.

제2도는 본 발명의 반도체 집적회로의 소자 격리 방법을 나타낸 공정 단면도이다.2 is a cross sectional view showing a device isolation method of a semiconductor integrated circuit according to the present invention.

본 발명의 소자 격리 공정은 먼저, 제2도(a)와 같이, 실리콘 기판(1)에 높은 에너지로 산소를 1차 주입하여 제2도(b)와 같이 상기 실리콘 기판(1) 내의 일정 깊이에 매몰산화막(2)을 형성한다.In the device isolation process of the present invention, first, as shown in FIG. 2 (a), oxygen is first injected into the silicon substrate 1 with high energy, and as shown in FIG. 2 (b), a predetermined depth in the silicon substrate 1 is obtained. A buried oxide film 2 is formed in the film.

그리고 열산화 공정으로 제2도(c)와 같이, 실리콘 기판(1) 표면에 산화막(3)을 형성시키고 상기의 산화막(3)을 소자 격리 영역을 제외한 부분에만 남도록 식각하여 실리콘 기판(1)의 소자 격리 영역이 노출되도록 한다.In the thermal oxidation process, as shown in FIG. 2C, an oxide film 3 is formed on the surface of the silicon substrate 1, and the oxide film 3 is etched to remain only in a portion except the device isolation region. Allow the device isolation region of to be exposed.

이어, 제2도(d)와 같이, 상기의 식각 공정에 의해 패터닝되어진 산화막(3)을 산소 이온 주입시에 소자 격리 영역 이외의 활성영역에 산소가 주입되는 것을 방지하기 위한 마스크로 사용하여 실리콘 기판(1)에 2차 산소이온 주입공정을 한다.Subsequently, as shown in FIG. 2D, the oxide film 3 patterned by the above etching process is used as a mask to prevent oxygen from being injected into active regions other than the device isolation region during oxygen ion implantation. A secondary oxygen ion implantation process is performed on the substrate 1.

이때, 최초의 주입에너지는 매몰산화막(2) 형성시의 에너지와 동일하게 하고 점차 그 에너지 강도를 점차 줄여가면서 반복하여 소자 격리 영역에 산소가 고루 분포하도록 한다.At this time, the initial injection energy is the same as the energy when the buried oxide film 2 is formed, and the energy intensity is gradually decreased, and the oxygen is repeatedly distributed evenly in the device isolation region.

상기와 같은 방법으로 이온 주입 에너지를 조절하여 산소 이온을 주입하여 열처리를 하게 되면 성장되는 산화막층의 프로파일을 조절할 수 있게 된다. 즉, 이 상태에서 열처리 공정을 하여 제2도(e)와 같이, 소자 격리 부분에 산화막(4)을 실리콘 기판(1)과 동일한 높이로 형성한다.By adjusting the ion implantation energy in the above manner, when the oxygen ion is implanted and heat treated, the profile of the grown oxide layer can be controlled. That is, the heat treatment process is performed in this state to form the oxide film 4 at the same height as the silicon substrate 1 in the element isolation portion as shown in FIG.

상기한 본 발명의 소자 격리 공정은 기판 식각 공정을 하지 않으므로 공정이 훨씬 간단하여지고 기판 식각을 위한 식각장치나 CVD장치 등이 불필요하게 되어 경제성이 뛰어나며, 2차 산소 이온 주입의 조건을 최적화하면 기판 표면이 평탄하여 이후의 공정이 용이하여지는 등 많은 효과가 있다.Since the device isolation process of the present invention does not perform a substrate etching process, the process is much simpler, and an etching apparatus or a CVD apparatus for substrate etching is unnecessary, so that the economic efficiency is excellent. There are many effects such that the surface is flat to facilitate subsequent processing.

Claims (2)

반도체 기판에 산소이온을 주입하고 열처리하여 매몰산화막을 형성하는 공정, 기판표면에 절연막을 형성하고 격리 영역의 절연막을 제거하는 공정, 격리 영역에 산소이온을 주입하고 열처리하여 격리 산화막을 형성하는 공정을 포함하는 반도체 집적회로의 소자 격리 방법.Forming a buried oxide film by injecting and heating oxygen ions into a semiconductor substrate, forming an insulating film on the surface of the substrate, removing an insulating film in the isolation region, and forming an isolation oxide film by injecting and heating oxygen ions into the isolation region. Device isolation method of a semiconductor integrated circuit comprising. 제1항에 있어서, 격리 영역에 산소이온주입시, 최초의 산소주입에너지는 매몰산화막 형성시의 에너지와 같게 하고, 점차로 에너지를 감소시키면서 수회에 걸쳐 산소이온을 주입하는 것을 특징으로 하는 반도체 집적회로의 소자 격리 방법.The semiconductor integrated circuit according to claim 1, wherein when the oxygen ion is injected into the isolation region, the initial oxygen injection energy is the same as the energy when forming the buried oxide film, and the oxygen ion is implanted several times while gradually decreasing the energy. Device isolation method.
KR1019880015690A 1988-11-28 1988-11-28 Isoating method of integrated circuit KR970007111B1 (en)

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