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KR960024982A - Effective use and method of memory - Google Patents

Effective use and method of memory Download PDF

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Publication number
KR960024982A
KR960024982A KR1019940040377A KR19940040377A KR960024982A KR 960024982 A KR960024982 A KR 960024982A KR 1019940040377 A KR1019940040377 A KR 1019940040377A KR 19940040377 A KR19940040377 A KR 19940040377A KR 960024982 A KR960024982 A KR 960024982A
Authority
KR
South Korea
Prior art keywords
memory
data
signal
value
lower data
Prior art date
Application number
KR1019940040377A
Other languages
Korean (ko)
Other versions
KR0152314B1 (en
Inventor
원창연
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940040377A priority Critical patent/KR0152314B1/en
Publication of KR960024982A publication Critical patent/KR960024982A/en
Application granted granted Critical
Publication of KR0152314B1 publication Critical patent/KR0152314B1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G06F12/0684—Configuration or reconfiguration with feedback, e.g. presence or absence of unit detected by addressing, overflow detection

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Error Detection And Correction (AREA)

Abstract

본 발명은 통신분야에서 자주 사용하는 인터리빙 기술을 적용하여 메모리의 용량을 줄이도록 함을 특징으로 하는 메모리의 효과적 이용장치 및 방법에 관한 것으로, 컨벌루션 인터리빙을 할 때는 많은 메모리가 필요로 하게 되는 문제점이 있어, 본 발명은 실제 사용하지 않은 메모리의 상위 혹은 하위 데이타 비트를 사용하여 컨벌루션 인터리빙과 같이 메모리를 효과적으로 사용할 수 있도록 하기 위하여 현재의 입력시키고자 하는 메모리 어드레스에 실려 있는 이전의 상위 혹은 하위 데이타 비트의 값을 피드백시켜, 지금 입력하고자 하는 상위 혹은 하위 데이타의 값과 함께 메모리에 입력시켜 이전의 상위 혹은 하위 데이타 비트의 값을 손상되지 않게 함으로써 메모리를 효율적으로 활용할 수 있게 한 것이다.The present invention relates to an apparatus and method for effectively using a memory characterized by reducing the capacity of a memory by applying an interleaving technique frequently used in the communication field, and a problem that requires a lot of memory when performing convolutional interleaving. Thus, the present invention uses the upper or lower data bits of an unused memory to effectively use the memory, such as convolutional interleaving. By feeding back a value, it is input to the memory together with the value of the upper or lower data to be input now, so that the value of the previous upper or lower data bit is not damaged so that the memory can be utilized efficiently.

Description

메모리의 효과적 이용장치 및 방법Effective use and method of memory

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 구성도이다.1 is a block diagram of the present invention.

Claims (2)

4비트를 하나의 심벌로 하는 상위 데이타의 출력신호(A) 내지 메모리부로부터 피드백된 데이타 신호(A’)를 임시저장하는 상위버퍼(10’)와, 4비트를 하나의 심벌로 하는 하위 데이타의 출력신호(B) 내지 메모리부로부터 피드백된 데이타 신호(B’)를 임시저정하는 하위버퍼(20)와, 8비트 데이타 버스를 연결하여 상기 상하위버퍼(10, 20)를 통한 데이트 출력신호를 입력하는 메모리부(30)와, 메모리부(30)에 저장된 데이타를 버퍼(10, 20)로 리드하거나 버퍼(20, 20)에 저장된 데이타를 메모리부(30)로 라이트하는 신호를 제어신호를 출력하는 리드/라이트 제어부(40)와, 상위 데이타(A) 입력시 피드백된 하위 데이타 신호(B’)를 선택하고 하위 데이타(B) 입력시 피드백된 상위 데이타 신호(A’)를 선택하는 데이타출력 제어부(50) 및 어드레스 제어부(60)로 구성함을 특징으로 하는 메모리의 효과적 이용장치.Upper buffer 10 'for temporarily storing the output signal A of the upper data having 4 bits as one symbol to the data signal A' fed back from the memory unit, and lower data having 4 symbols as one symbol. The output buffer B to the data buffer B 'fed back from the memory unit, and the lower buffer 20 to temporarily store the data output signal through the upper and lower buffers 10 and 20 by connecting an 8-bit data bus. A control signal is used to input a signal to the memory unit 30 and the data stored in the memory unit 30 to the buffers 10 and 20 or to write data stored in the buffers 20 and 20 to the memory unit 30. Data for selecting the outputted read / write control unit 40 and the lower data signal B 'fed back when the upper data A is input, and selecting the upper data signal A' fed back when the lower data B is input. It is composed of an output control unit 50 and an address control unit 60 Effective use of a memory device which. 현재 입력시키고자 하는 메모리 어드레스에 실려있는 이전의 상위 혹은 데이타 비트의 값을 피드백 시킨 다음, 현재 입력하고자 하는 상위 혹은 하위 데이타의 값과 메모리에 입력시킴으로써, 이전의 상위 혹은 하위 데이타 비트의 값을 손상시키지 않고 메모리를 효율적으로 활용할 수 있도록 함을 특징으로 하는 메모리의 효과적 이용방법.Damages the value of the previous upper or lower data bit by feeding back the value of the previous upper or lower data bit on the memory address to be inputted, and then inputting it into the memory and the upper or lower data value to be inputted. Effective use of the memory, characterized in that the memory can be utilized efficiently without having to. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940040377A 1994-12-31 1994-12-31 Memory device KR0152314B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940040377A KR0152314B1 (en) 1994-12-31 1994-12-31 Memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940040377A KR0152314B1 (en) 1994-12-31 1994-12-31 Memory device

Publications (2)

Publication Number Publication Date
KR960024982A true KR960024982A (en) 1996-07-20
KR0152314B1 KR0152314B1 (en) 1998-10-15

Family

ID=19406131

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940040377A KR0152314B1 (en) 1994-12-31 1994-12-31 Memory device

Country Status (1)

Country Link
KR (1) KR0152314B1 (en)

Also Published As

Publication number Publication date
KR0152314B1 (en) 1998-10-15

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