KR960013624B1 - Manufacture of shallow junction semiconductor device - Google Patents

Abstract

forming a field oxide film(2), a gate oxide film(4), a polysilicon gate(3), a side wall spacer(5), and a source/drain junction(6) on a silicon substrate(1); evaporating a polysilicon film(7) in a finite thickness on a surface of wafer; crystallizing the polysilicon film(7) by a heat treatment; removing all remains except for a photoresistor(8-1); removing all remains except for a silicon layer(7-1) by the etch-back; injecting an impurity into the source/drain region; forming source/drain junction(9); performing a heat treatment.

Description

Manufacturing method of shallow junction semiconductor device

1A and 1B are cross-sectional views showing a conventional shallow junction semiconductor device.

2A to 2G are cross-sectional views of a shallow junction semiconductor device of the present invention.

* Explanation of symbols for main parts of the drawings

1,11 silicon substrate 2,12 field oxide

4,13: gate oxide

3,14 polysilicon gate

5,15: side wall spacer

6,16 n-source / drain junction

7,7-1: additional silicon layer

8,8-1: photo-resister

9,17: n + source / drain junction

10: low-temperature oxide

11 aluminum-based wiring metal 12 barrier metal

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method for manufacturing an ultra-high density semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a very shallow source / drain of a shallow junction.

Recently, as semiconductor technology becomes very high speed and ultra high integration, source / drain formation technology requires more advanced technology, and extremely shallow source / drain junction formation technology is a core technology that must be developed in the manufacture of ultra-high density semiconductor devices. . In the conventional shallow junction formation method (refer to (a) and (b) of FIG. 1), a source of shallower junction is ion-implanted with a low energy by using ion implanter in the source / drain region 16 at low energy. / Drain has been formed.

However, in the fabrication of ultra-high density semiconductor devices, shallow junction formation having a junction depth of 100 nm or less is required. In the conventional source / drain junction formation method, shallow junction formation is extremely difficult, and how to form a shallow junction source / drain junction Even so, the sheet resistance of the source / drain regions and the contact resistance between the metal wiring and the source / drain regions become very large, resulting in poor semiconductor device characteristics.

In particular, when P + source / drain formation using boron (B) having a high diffusion rate such as PMOS and complementary moss (CMOS) is required, the conventional shallow junction formation method requires a level of the level required for ultra-high density devices. It is more impossible to form a shallow junction.

SUMMARY OF THE INVENTION The present invention has been made to solve these problems in the prior art, and improves the characteristics of the semiconductor device by reducing the sheet resistance and the contact resistance.

In order to achieve the above object, in the present invention, a gate insulating film is formed on a P-type silicon substrate, poly-silicon is deposited, and the crystalline characteristics of the polycrystalline silicon are heat treated to a level similar to that of the single crystal of the silicon substrate. Crystallization, leaving only silicon in the source / drain regions of the silicon layer further deposited by the etch-beck process, is used to form a shallow junction.

In this way, since the source / drain regions have a junction depth of the silicon substrate itself and the thickness of the additionally deposited silicon layer is added, the total junction depth is deep, but the junction depth, that is, the effective junction depth in the original silicon substrate is shallow. Is formed.

A preferred embodiment of the present invention will now be described in detail with reference to FIG. 2.

(A) to (g) of FIG. 2 is a side view showing the process sequence for manufacturing an NMOS according to the present invention.

First, as shown in FIG. 2A, a P-type silicon substrate 1 is used to form a pattern of an activation / deactivation region by photolithography, and an ion implantation process and a field oxide layer 2 for field threshold voltage control are performed. Growth, formation of gate insulating film 4 of about 3-50 nm, ion implantation process for controlling threshold voltage of transistor, formation and definition of polycrystalline silicon gate 3 of about 200-500 nm, formation of n-source / drain junction, about 20-300 nm The process of forming the sidewall spacers 5 is performed sequentially.

Subsequently, a process of forming and crystallizing a polycrystalline silicon film for forming a shallow junction is performed. In this process, a low-pressure chemical vapor deposition method deposits about 20-300 nm of the shallow junction-forming polycrystalline silicon film 7 on the entire surface of the wafer (FIG. B)), The polycrystalline silicon film for shallow junction formation is crystallized by solid epitaxial growth by heat treatment at a temperature of about 500-900 ° C.

After the crystallization of the polycrystalline silicon film is performed as described above, the step of forming a shallow junction silicon layer is performed.

In this step, the photoresist 8 having excellent planarization characteristics is applied to the entire surface of the wafer (FIG. 3 (c)) after the second step (b) of the previous step is performed, and the photoresist 8 is etched to obtain a source. Only the photoresist 8-1 of the / drain region remains, and all the rest are removed (Fig. 2 (d)).

Subsequently, as shown in FIG. 2 (e), only the silicon layer 7-1 of the active region of the additionally deposited silicon layer is left as an etch-back process, and all the others are removed.

As described above, after the silicon layer 7-1 for bonding is formed, impurities such as phosphorus (P) or arsenic (As) are ion-implanted at high concentration into the source / drain region by using an ion implanter, and then n + source / After the drain junction 9 is formed, it is activated at high temperature using rapid heat treatment or an electric furnace heat treatment (FIG. 2 (bar)).

According to this process, the total junction depth is deep, but a shallow n + source / drain junction having an effective junction depth of 100 nm or less is formed.

The above activation process may be performed after the BPSG insulation film deposition process to be performed later in this embodiment.

After this activation process, a BPSG insulating film deposition and reflow process at high temperature, a contact hole defining process, a barrier metal and wiring metal film deposition and pattern forming process, an alloying process, a passivation process, or an addition may be added. A multi-layered metal wiring forming process and the like are carried out in the usual process sequence.

In the present specification, as described above, the method has been described in detail only in the case of forming n + source / drain, and the shallow junction P + source / drain required for PMOS and complementary moss (CMOS) is to be formed. In this case, the same method of forming a shallow junction of n + source / drain is performed, but B or BF 2 is used instead of P or As as an ion implantation impurity.

The technical effects expected when using the present invention as described above are as follows.

Firstly, the effective junction depth of the source / drain regions can be made into a shallow junction of 100 nm or less, and secondly, the impurity concentration and the impurity concentration gradient of the source / drain regions can be easily adjusted. Since the final junction depth of the source / drain regions can be deepened, and impurities in the source / drain regions can be formed at high concentration, the sheet resistance and contact resistance can be made excellent, and the device characteristics can be improved. The surface height of the source / drain regions is increased by the thickness of the polysilicon film, and the height difference from the gate region is reduced, thereby improving the planarization characteristics of the semiconductor device. Fifth, the surface height of the source / drain regions increases. Step coverage in the wiring metal as the aspect ratio of the source / drain regions is reduced by the thickness of the polycrystalline silicon film. Improved and is characterized in that the superior reliability of the contact and metal wiring.

Finally, the smaller the size of the gate-to-field as in the VLSI semiconductor circuit in implementing the present invention, it is advantageous, which has the effect of increasing the density in the highest integrated device.

Claims (2)

A method of manufacturing a semiconductor device having a source / drain having a shallow junction, comprising: a field oxide film 2, a gate oxide film 4, a polycrystalline silicon gate 3, and a sidewall on a defined silicon substrate 1 in an active region After the process of forming the spacers 5 and the source / drain junctions 6 is completed, a polycrystalline silicon film 7 is deposited on the wafer surface to a predetermined thickness and heat-treated to crystallize the polycrystalline silicon film 7. Process and applying the photoresist 8, removing only the photoresist 8-1 of the source / drain region and removing the rest, and leaving only the silicon layer 7-1 of the active region by etch back to remove the rest. And implanting impurities into the source / drain regions at high concentration to form a source / drain junction (9) and heat treatment. The method of manufacturing a shallow junction semiconductor device according to claim 1, wherein the polycrystalline silicon film 7 has a thickness of 20 to 300 nm, and a heat treatment temperature for crystallizing the polycrystalline silicon film 7 is 500 to 900 ° C. Way.