JPH11186546A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent junction characteristics, etc., from deteriorating in a MOS transistor structure in which an elevated source/drain structure is combined with salicide. SOLUTION: A monocrystal silicon film 108a is selectively grown on an exposed n-type diffusion layer 106, and a non-monocrystal silicon 18b is grown on the facet of the silicon film 108a. A silicon oxide film 109 is deposited over entirely and then polished by chemicomechanical polishing(CMP) method, until the non-monocrystal silicon film 108b adjacent to the insulating film 107 of a sidewall is exposed. After a silicon oxide film 105 left on a polysilicon film 104 has been removed, the polysilicon 104 and a selectively grown silicon film 108 are made into n-type, and an n<+> -type diffusion layer 110 is formed on the top layer of a p-type silicon substrate 101. A silicide film 111 is formed in self-alignedly on the polysilicon film 104 and the silicon film 108.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having an elevated source / drain structure and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, integrated circuits in which a large number of transistors, resistors, and the like are integrated on a semiconductor substrate have been widely used in important parts of computers and communication devices. With the increase in the degree of integration of devices, design rules are shrinking year by year.

[0003] In a MOS type integrated circuit,
In order to suppress the short channel effect accompanying the reduction in gate length, it is required to make the depth of the diffusion layer shallow. At the same time, it is necessary to prevent an increase in resistance due to a shallow diffusion layer depth. As a method for keeping the depth of the diffusion layer shallow and keeping the resistance of the diffusion layer low, an elevated source / drain structure in which only the source / drain regions are raised with silicon and a silicide which is a compound of silicon and a metal are formed in a self-aligned manner. It is considered to be an effective method to combine with salicide.

[0004] The elevated source / drain structure itself has been tried in several ways.
For example, using dichlorosilane as a source gas,
There is known a method for selectively epitaxially growing silicon only on the source / drain. However, a facet surface is formed at an end of the single crystal silicon film because the single crystal silicon film is deposited by epitaxial growth.

FIG. 4 shows a structure in which an elevated source / drain structure formed of a single crystal silicon film and salicide are combined. In FIG. 4, 101 is a silicon substrate, 102 is an isolation insulating film, 103 is a gate insulating film, 121 is a gate electrode, 122 is a silicon nitride film,
107 is a side wall insulating film, 106 is an n-type diffusion layer, and 110 is n
^{The +} type diffusion layer 111 is a silicide film.

When the elevated source / drain structure is combined with a silicide film, the silicide film 111 is formed to a deep region in the diffusion layer 110 of the substrate 101, and there is a problem that a junction leak occurs.

Therefore, an n ⁺ -type diffusion layer is formed by implanting ions of arsenic or the like into a single crystal silicon film formed by selective growth, followed by annealing.
A technique has been proposed in which single crystal silicon formed by selective growth is converted into an n-type conductivity type to suppress junction leakage. FIG. 5 shows a structure formed using this process. The facet surface is formed and the thickness of the single crystal silicon film is thin.
In the vicinity, the depth of the n ⁺ type diffusion layer 110 increases.

By using this process, there is no region where the pn junction surface and the silicide film are very close to each other, and it is possible to avoid the problem that junction leakage increases. However, there is a problem that the depth of the diffusion layer 110 near the gate electrode is increased and the short channel effect cannot be suppressed.

[0009]

As described above, when the elevated source / drain structure is combined with salicide, there is a problem that silicide is also formed in the substrate and a junction leak occurs. Further, when ions are implanted into selectively grown single crystal silicon in order to prevent junction leakage, the depth of the diffusion layer is increased, and the short channel effect cannot be suppressed.

An object of the present invention is to provide a method of manufacturing a semiconductor device which can suppress a short channel effect while preventing junction leakage in a structure combining an elevated source / drain structure and salicide. is there.

[0011]

Means for Solving the Problems [Configuration] The present invention is configured as follows to achieve the above object. (1) The present invention (claim 1) provides a MOS transistor formed in an active region surrounded by an element isolation insulating film on a silicon substrate, and a silicide formed on a source / drain diffusion layer of the MOS transistor. And an insulating film is formed on the element isolating insulating film surrounding the active region, and the silicide film is not in contact with the element isolating insulating film. . (2) According to the present invention (claim 2), a MOS
A method for manufacturing a semiconductor device for forming a transistor, comprising: a step of forming an element isolation insulating film in a predetermined region of the silicon substrate; a step of forming a gate insulating film, a gate electrode made of polycrystalline silicon on the exposed silicon substrate; Forming a laminated film by sequentially laminating a gate upper insulating film, forming a sidewall insulating film on a side wall of the laminated film, and forming a film on an exposed surface of the silicon substrate in contact with the sidewall insulating film. Selectively forming a silicon film thicker than the thickness of the gate electrode, depositing an insulating film on the element isolation insulating film, side wall insulating film, gate upper insulating film and silicon film; Etching or polishing the film and the silicon film substantially uniformly to expose the silicon film in a region adjacent to the sidewall insulating film, and removing the gate upper insulating film And that step, characterized in that it comprises a step of forming a self-aligned manner silicide film on the silicon film and the gate electrode. (3) According to the present invention (claim 3), a MOS
A method of manufacturing a semiconductor device for forming a transistor, comprising: forming an element isolation insulating film in a predetermined region of the silicon substrate; and forming a gate insulating film, a gate electrode, and a gate upper insulating film on the exposed silicon substrate. Forming a laminated film by sequentially laminating, forming a sidewall insulating film of the laminated film, and forming a film on the exposed surface of the silicon substrate at a portion in contact with the sidewall insulating film, the film thickness of the gate electrode. A step of selectively forming a thicker silicon film; a step of depositing an insulating film on the element isolation insulating film, the side wall insulating film, the gate upper insulating film and the silicon film; Etching or polishing evenly,
A step of exposing the silicon film in a region adjacent to the sidewall insulating film; and a step of forming a silicide film on the silicon film in a self-aligned manner.

Preferred embodiments of the present invention are described below. (3-1) The gate upper insulating film and the side wall insulating film are silicon nitride films. (2,3-1) After substantially uniformly etching or polishing the insulating film and the silicon film, ion implantation is performed to form source / drain diffusion layers of the MOS transistor. (2,3-2) after the formation of the silicide film, a step of forming an interlayer insulating film on the silicide film, the side wall insulating film, the upper gate insulating film, and the insulating film; Forming an opening connected to the silicide film in the interlayer insulating film under conditions faster than the insulating film; and embedding an electrode in the opening. (2,3-3) The gate upper insulating film is a silicon nitride film, and the interlayer insulating film is a silicon oxide film.

[Function] The present invention has the following functions and effects by the above configuration. Source of MOS transistor
After selectively forming a silicon film having a thickness greater than that of the gate electrode at a portion in contact with the sidewall insulating film on the drain diffusion layer,
An insulating film is formed on the entire surface. Then, the surfaces of the silicon film and the insulating film are flattened by using a CMP method or the like. Then, by forming the silicide film in a self-aligned manner, the silicide film is not formed in the substrate since there is no part where the silicide film is partially thin.

Further, by forming the diffusion layer by performing ion implantation after flattening the silicon film, the diffusion layer does not become deep and the short channel effect can be suppressed.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] FIG. 1 is a process sectional view showing a manufacturing process of a MOS FET device according to a first embodiment of the present invention.

First, an isolation insulating film 102 made of a silicon oxide film is formed on a p-type silicon substrate 101 having a (100) crystal orientation. Then, after the exposed surface of the p-type silicon substrate 101 is oxidized to form a gate insulating film 103 made of a silicon oxide film, a polycrystalline silicon layer 104 to be a gate electrode and a silicon oxide film (gate upper insulating film) 105 Are sequentially deposited and then patterned to form a gate electrode-shaped laminated film. Then, arsenic is ion-implanted using the silicon oxide film 105 as a mask to form n.
A mold diffusion layer 106 is formed. Then, after depositing a silicon nitride film on the entire surface, anisotropic etching is performed on the silicon nitride film to form a sidewall insulating film 107. Then, the exposed gate insulating film 103 is removed.
At this time, the etching amount is adjusted so that the silicon oxide film 105 on the polycrystalline silicon film 104 remains even after the silicon oxide film 103 is removed (FIG. 1A).

Next, using a selective growth process of silicon, (11) is selectively formed on the exposed n-type diffusion layer 106.
1) Single-crystal silicon film 108 having facet face
a is grown (FIG. 1B). In the selective growth, by adjusting the deposition temperature (for example, 750 ° C.), imperfect crystalline silicon, that is, a polycrystalline or amorphous non-single-crystal silicon film 108b grows on the facet surface of the single-crystal silicon 108a.

The growth rate of the non-single-crystal silicon film 108b covering the facet surface depends on the isolation insulating film 102b.
For the region in contact with the silicon oxide film used for the material of
The growth is faster in the region in contact with the silicon nitride film used as the material of the gate electrode side wall. Non-single-crystal silicon film 10 formed by utilizing such selective growth characteristics of the silicon film
8b is deposited until the thickness of the portion in contact with the sidewall insulating film is greater than the thickness of the gate electrode and is greater than or equal to the thickness consumed by the subsequent silicide film formation process (FIG. c)).

Next, a silicon oxide film (insulating film) is formed on the entire surface.
After depositing 109, silicon films 108 (108a, b), selectively grown using chemical mechanical polishing (CMP),
Silicon oxide films 105 and 109 and sidewall insulating film 107
To the non-single-crystal silicon film 1 adjacent to the side wall insulating film 107.
08b is exposed until the surface of the device is flattened, and the non-single-crystal silicon film 108b in the region adjacent to the side wall insulating film is polished.
Is exposed (FIG. 1 (d)). By this CMP process,
Single crystal silicon film 108 grown on n-type diffusion layer 106
a and the non-single-crystal silicon film 108b have a uniform total film thickness. Also, since the upper surface of the non-single-crystal silicon film 108b at a position adjacent to the sidewall insulating film 107 is above the upper surface of the gate electrode, the silicon oxide film 10b on the gate electrode
5 is not removed.

Next, after the silicon oxide film 105 remaining on the polycrystalline silicon film 104 is removed, n-type impurities such as arsenic are ion-implanted, and a thermal process is performed.
Polycrystalline silicon 104 and selectively grown silicon film 10
8 is an n-type conductivity type and a p-type silicon substrate 1
The n ⁺ type diffusion layer 110 is formed on the surface layer of the semiconductor device (see FIG. 1).
(E)).

Next, a silicide film 111 is self-aligned on the polycrystalline silicon film 104 and the silicon film 108 by performing a salicide process such as deposition of a metal film such as titanium, heat treatment, and selective removal of unreacted metal. It is formed (FIG. 1F).

Finally, after an interlayer insulating film 112 such as a silicon oxide film is deposited on the entire surface, a contact hole connected to the silicide film 111 on the n ⁺ type diffusion layer 106 is formed in the interlayer insulating film 112. After a conductive film such as aluminum is deposited on the entire surface, patterning is performed to form a wiring layer 1.
By forming 13, the MOS FET device is completed. (FIG. 1G) According to the present embodiment, the parasitic resistance can be reduced without increasing the junction leak current even when the diffusion layer is made shallower by miniaturization of the element.

[Second Embodiment] FIG. 2 is a process sectional view showing a manufacturing process of a MOS FET device according to a second embodiment of the present invention.

An insulating film (silicon oxide film) 10 for element isolation is formed on a p-type silicon substrate 101 having a (100) crystal orientation.
Form 2 Then, after forming the gate recording film 103, an n-type polycrystalline silicon layer 114 for a gate electrode, a high melting point metal film 115 such as tungsten for reducing gate resistance, and a silicon nitride film 116 are sequentially deposited. ,
Patterning is performed to form a gate electrode-shaped laminated film. Next, arsenic is ion-implanted using the silicon nitride film 116 as a mask to expose the exposed p-type silicon substrate 1.
On the surface of No. 01, an n-type diffusion layer 106 is formed. And
After depositing a silicon nitride film on the entire surface, anisotropic etching is performed on the silicon nitride film to form a sidewall insulating film 107. Then, the exposed gate insulating film 10
3 is removed (FIG. 2A).

Next, as in the first embodiment, the exposed n-type diffusion layer 10 is formed by using a selective growth process of silicon.
A single-crystal silicon film 108a and a polycrystalline silicon film 108b are selectively formed on 6 (FIG. 2B).

Next, after a silicon oxide film 109 is deposited on the entire surface, the silicon film 108, the silicon oxide film 109, the interlayer insulating film 107, and the silicon nitride film 116 are removed by a CMP method. Polishing is performed until the silicon film 108b is exposed (FIG. 2)
(C)). At this time, by adjusting the film thickness so that the film thickness b of the silicon nitride film is larger than the step a between the silicon substrate 101 and the device isolation insulating film 102, the gate electrode extending on the device isolation insulating film 102 Also, the silicon nitride film 116 can be left on the electrode.

Next, an n-type impurity such as arsenic is ion-implanted, and a thermal process is performed to convert the silicon film 108 into an n-type conductivity type and to form a p-type silicon substrate 101.
The n ⁺ -type diffusion layer 110 is formed on the surface layer. By performing a salicide process such as deposition of a metal film such as titanium, heat treatment, and selective removal of unreacted metal,
A silicide film 111 is formed on the exposed silicon film 108.
Is formed (FIG. 2D). Here, before performing the salicide process, the silicon oxide film 109 is receded by a solution etching using hydrofluoric acid or the like, thereby forming the silicide film 1.
It is also possible to enlarge the area where 11 is formed.

Finally, after an interlayer insulating film 112 such as a silicon oxide film is deposited on the entire surface, a contact hole connected to the silicide film 111 is formed in the interlayer insulating film 112.
In forming this contact hole, the interlayer insulating film 112 is etched under the condition that the etching speed of the interlayer insulating film 112 is higher than the etching speed of the silicon oxide film. Then, after depositing a conductive film such as aluminum, patterning is performed to form the wiring layer 113.
The type FET device is completed (FIG. 2E).

According to the present embodiment, the parasitic resistance can be reduced without increasing the junction leakage current even when the diffusion layer is made shallow by the miniaturization of the element. When a contact hole for connecting the silicide film 110 is formed, by using an etching method in which the etching rate for a silicon oxide film (interlayer insulating film) is sufficiently higher than that for a silicon nitride film (gate upper insulating film), this contact can be obtained. A so-called self-aligned contact structure that can prevent a short circuit between the gate electrode and the source / drain electrode as shown in FIG. 3 even if the position of the hole is shifted due to misalignment in the photolithography process or the like. To reduce the area of the source / drain diffusion layer. It becomes possible.

The present invention is not limited to the above embodiment. For example, in the above-described embodiment, the non-single-crystal silicon film is grown on the facet surface during the growth of the single-crystal silicon film. Is also good. Note that, similarly to non-single-crystal silicon, single-crystal silicon has a higher growth rate at a portion in contact with the silicon nitride film than at a portion in contact with the silicon oxide film. In addition, the present invention
Various modifications can be made without departing from the scope of the invention.

[0031]

As described above, according to the present invention, after selectively forming a silicon film thicker than the gate electrode, forming an insulating film over the entire surface, and polishing the insulating film and the silicon film, By forming the silicide film in a self-aligned manner, a junction leak can be prevented without forming the silicide film in the substrate.

Further, by performing ion implantation after polishing the insulating film and the silicon film, the short channel effect can be suppressed without increasing the depth of the diffusion layer adjacent to the gate electrode. .

[Brief description of the drawings]

FIG. 1 is a process cross-sectional view showing a manufacturing process of a MOS FET device according to a first embodiment.

FIG. 2 is a process cross-sectional view showing a manufacturing process of a MOS-type FET device according to a second embodiment.

FIG. 3 is a sectional view showing a structure of a MOS-type FET device according to a second embodiment.

FIG. 4 is a sectional view showing the structure of a conventional MOS FET device.

FIG. 5 is a cross-sectional view showing the structure of a conventional MOS FET device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 101 ... p-type silicon substrate 102 ... element isolation insulating film 103 ... gate insulating film 104 ... polycrystalline silicon film 105 ... silicon oxide film 106 ... n-type diffusion layer 107 ... side wall insulating film 108a ... single crystal silicon 108b ... polycrystalline silicon 109: insulating film 110: n ⁺ type diffusion layer 111: silicide film 112: interlayer insulating film 113: wiring

Claims (5)

[Claims] A MOS transistor formed in an active region surrounded by an isolation insulating film on a silicon substrate; and a silicide film formed on source / drain diffusion layers of the MOS transistor. A semiconductor device, wherein an insulating film is formed on an element isolation insulating film surrounding the active region, and the silicide film is not in contact with the element isolation insulating film. 2. A method of manufacturing a semiconductor device in which a MOS transistor is formed on a silicon substrate, comprising: forming an element isolation insulating film in a predetermined region of the silicon substrate; and a gate insulating film on the exposed silicon substrate. Forming a laminated film by sequentially laminating a gate electrode and a gate upper insulating film made of polycrystalline silicon; forming a sidewall insulating film on a side wall of the laminated film; Selectively forming a silicon film having a thickness at a portion in contact with the sidewall insulating film larger than the thickness of the gate electrode; and forming a silicon film on the element isolation insulating film, the sidewall insulating film, the gate upper insulating film, and the silicon film. Depositing an insulating film; and etching or polishing the insulating film and the silicon film substantially uniformly to expose the silicon film in a region adjacent to the sidewall insulating film. Step and a step of removing the gate upper insulating film, a method of manufacturing a semiconductor device which comprises a step of forming a self-aligned manner silicide film on the silicon film and the gate electrode. 3. A method of manufacturing a semiconductor device in which a MOS transistor is formed on a silicon substrate, comprising: forming an element isolation insulating film in a predetermined region of the silicon substrate; and a gate insulating film on the exposed silicon substrate. Forming a laminated film by sequentially laminating a gate electrode and a gate upper insulating film; forming a sidewall insulating film on a side wall of the laminated film; contacting the exposed side surface of the silicon substrate with the sidewall insulating film; Selectively forming a silicon film in which the thickness of the portion is greater than the thickness of the gate electrode; and depositing an insulating film on the element isolation insulating film, the sidewall insulating film, the gate upper insulating film, and the silicon film. A step of substantially uniformly etching or polishing an insulating film and the silicon film to expose the silicon film in a region adjacent to the sidewall insulating film; Forming a self-aligned silicide film on the film. 4. After the formation of the silicide film, a step of forming an interlayer insulating film on the silicide film, the side wall insulating film, the gate upper insulating film, and the insulating film; 4. The method according to claim 3, further comprising: forming an opening in the interlayer insulating film connected to the silicide film using a faster condition; and embedding an electrode in the opening. Of manufacturing a semiconductor device. 5. The method according to claim 2, wherein said sidewall insulating film is a silicon nitride film.