KR950015388A

KR950015388A - Semiconductor memory circuit charging complementary bit lines

Info

Publication number: KR950015388A
Application number: KR1019940028599A
Authority: KR
Inventors: 겐지 고또
Original assignee: 가네꼬 히사시; 닛본덴기 가부시끼가이샤
Priority date: 1993-11-02
Filing date: 1994-11-02
Publication date: 1995-06-16
Also published as: JPH07130177A

Abstract

반도체 메모리 디바이스는 프리차지 트랜지스터들과 비트 라인 레벨 등화 트랜지스터들 및 비트 라인 레벨 보상 트랜지스터들을 갖고 있다. 각각의 프리차지 트랜지스터는 판독 동작에 앞서 비트 라인을 프리차지하기 위해 비트 라인들 중 하나와 전원 단자 사이에 삽입된다. 2개의 비트 라인들의 전압 레벨을 등화시키기 위해 각각의 비트 라인 레벨 트랜지스터는 메모리 셀들이 삽입되는 비트라인들 사이에 삽입된다. 각각의 비트 라인 레벨 보상 트랜지스터는 각각의 프리차지 트랜지스터에 병렬로 접속된다. 비트 라인 레벨 보상 트랜지스터의 게이트 전극은 비트 라인에 접속된다 판독 동작의 초기 단계 동안, 비트 라인 레벨 보상 트랜지스터의 게이트-소스 전압의 절대값이 트랜지스터의 게이트 임계 전압보다 더 작고 트랜지스터는 오프-상태로 있기 때문에, 비트 라인의 전압 레벨은 높은 감소율로 강하한다. 그러므로, 비트 라인의 전압 레벨의 변화는 빠르게 감지되고 메모리 디바이스의 동작 효율성은 향상된다.The semiconductor memory device has precharge transistors and bit line level equalization transistors and bit line level compensation transistors. Each precharge transistor is inserted between one of the bit lines and the power supply terminal to precharge the bit line prior to the read operation. Each bit line level transistor is inserted between the bit lines into which memory cells are inserted to equalize the voltage level of the two bit lines. Each bit line level compensation transistor is connected in parallel to a respective precharge transistor. The gate electrode of the bit line level compensation transistor is connected to the bit line. During the initial phase of the read operation, the absolute value of the gate-source voltage of the bit line level compensation transistor is less than the gate threshold voltage of the transistor and the transistor is in an off state. Therefore, the voltage level of the bit line drops at a high reduction rate. Therefore, the change in the voltage level of the bit line is quickly detected and the operating efficiency of the memory device is improved.

Description

Semiconductor memory circuit charging complementary bit lines

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명의 양호한 실시예에 따른 반도체 메모리 디바이스의 회로도.3 is a circuit diagram of a semiconductor memory device according to a preferred embodiment of the present invention.

Claims

In a semiconductor memory circuit, a precharge transistor, which is connected between a power supply terminal and a bit line, whose gate is connected to receive a precharge signal, and is connected in parallel to the precharge transistor, wherein the bit line And a bit line level compensation transistor which has a control electrode connected to and is turned on when the voltage of said bit line is lower than a predetermined voltage.

2. The semiconductor memory circuit of claim 1 wherein the bit line level compensation transistor is an enhancement P-channel MOSFET.

A semiconductor static RAM comprising: a pair of compensation bit lines, at least one static RAM memory cell connected to the pair of compensation bit lines and connected to a word line, the pair of compensation bit lines and a voltage A bit line load circuit connected between a supply terminal and a pair of precharge transistors connected between the voltage supply terminal and the pair of compensation bit lines, and gates of the precharge transistor Connected in order to receive a precharge signal, each in parallel to a corresponding said precharge transistor of said respective bit line level compensation transistor having an enhancement P-channel transistor, each of which has its own gate Including a pair of bit line level compensation transistors connected to corresponding ones of said bit lines Semiconductor static RAM, characterized in that.

※ Note: The disclosure is based on the initial application.