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KR940022808A - 반도체 디바이스 및 그 제조방법과 리이드 프레임 및 탑재기판 - Google Patents

반도체 디바이스 및 그 제조방법과 리이드 프레임 및 탑재기판 Download PDF

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Publication number
KR940022808A
KR940022808A KR1019940004332A KR19940004332A KR940022808A KR 940022808 A KR940022808 A KR 940022808A KR 1019940004332 A KR1019940004332 A KR 1019940004332A KR 19940004332 A KR19940004332 A KR 19940004332A KR 940022808 A KR940022808 A KR 940022808A
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KR
South Korea
Prior art keywords
semiconductor device
lead
package
hole
chip
Prior art date
Application number
KR1019940004332A
Other languages
English (en)
Other versions
KR0121735B1 (ko
Inventor
마꼬또 기따노
아사오 니시무라
아끼히로 야구찌
나에 요네다
류지 고노
나오따까 다나까
데쯔오 구마자와
Original Assignee
가나이 쯔또무
가부시끼가이샤 히다찌세이사꾸쇼
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가나이 쯔또무, 가부시끼가이샤 히다찌세이사꾸쇼 filed Critical 가나이 쯔또무
Publication of KR940022808A publication Critical patent/KR940022808A/ko
Application granted granted Critical
Publication of KR0121735B1 publication Critical patent/KR0121735B1/ko

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    • H—ELECTRICITY
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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Abstract

고밀도 패키지에 접합한 플라스틱 몰드 타입의 반도체 디바이스 및 그 제조방법과 이것을 탑재한 프린트회로 기판인 탑재기판, 서로 조합된 반도체 디바이스 패키지를 포함하는 반도체 디바이스 및 반도체 디바이스에 사용되는 리이드 프레임으로서, 리이드 수가 패키지 사이즈와 비례하므로, 리이드 수가 증가함에 따라 패키지의 사이즈가 커진다는 단점이 있어 다핀에 의해 형성되는 고밀도 탑재에는 제한된다는 문제점을 해소 하기 위해, 패키지의 한쪽 표면에서 패키지 내부에 리이드 표면에 이르도록 마련된 제1의 구멍과 패키지의 반대 표면의 구멍에 대응하는 위치에 있어서 반대 표면에서 리이드의 상기 한쪽 표면에 대응하는 이면에 이르도록 마련된 제2의 구멍을 포함하고, 제1의 구멍과 제2의 구멍이 한쌍으로 마련되어 있고 한쌍을 포함하는 여러개의 세트로 구성되어있다.
이러한 반도체장치 및 그 제조방법과 리이드 프레임 및 탑재기판을 이용하는 것에 의해 리이드 프레임의 표면의 수지에 의래 덮여지거나 오염되지 않으므로 리이드 프레임에 접속된 땝납범프는 용이하게 형성된다.

Description

반도체 디바이스 및 그 제조방법과 리이드 프레임 및 탑재기판
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1실시예에따른 반도체 디바이스의 사시도, 제2도는 본 발명의 제1실시예에 따른 반도체 디바이스의 단면도, 제3도는 본 발명의 제1실시예에 따른 반도체 디바이스의 변형의 단변도.

Claims (41)

  1. 반도체 칩, 여러 개의 리이드 및 상기 칩과 상기 리이드를 서로 전기적으로 접속하는 수단을 갖고, 플라스틱으로 이들을 봉입하여 패키지를 형성하는 반도체 디바이스에 있어서, 상기 패키지의 한쪽 표면에서 상기패키지 내부의 상기 리이드 표면에 이르도록 마련된 제1의 구멍과, 상기 상기 패키지의 반대 표면의 상기 구멍에 대응하는 위치에 있어서 상기 패키지의 반대 표면에서 상기 리이드의 상기 한쪽 표면에 대응하는 이면에 이르도록 마련된 제2의 구멍을 포함하고, 제2의 구멍과 제2의 구멍이 한쌍으로 마련되어 있고, 상기 한쌍을 포함하는 여러개의 세트로 마련되는 반도체 디바이스.
  2. 제1항에 있어서, 상기 리이드에 접속되어 잇는 도전성 재료로 이루어진 범프는 상기 구멍의 일부 또는 전부의 내부에 마련되어 있는 반도체 디바이스.
  3. 제2항에 있어서, 상기 도전성 재료는 땝납인 반도체 디바이스.
  4. 제2항에 있어서, 도전성 재료로 이루어진 상기 범프는 상기 패키지의 표면에서 돌출되어 있는 반도체 디바이스.
  5. 제1항에 있어서, 패키지의 상기 표면의 구멍의 각 영역은 상기 리이드의 표면에서 상기 제2의 구멍보다 넓은 반도체 디바이스.
  6. 제1항에 있어서, 상기 각 구멍은 상기 패키지의 내부로 향해 좁아지도록 테이퍼로 되는 반도체 디바이스.
  7. 제1항에 있어서, 상기 리이드의 표면에서 상기 구멍의 안둘레는 리이드의 상기 표면의 범위내인 반도체 디바이스.
  8. 제7항에 있어서, 상기 구멍의 의치의 상기 각 리이드는 상기 각 리이드의 다른 부분보다 폭이 넓은 반도체 디바이스.
  9. 제1항에 있어서, 상기 패키지 표면에서 상기 리이드 표면에 이르는 상기 구멍의 깊이는 상기 퍄키지 표면의 상기 구멍의 열림사이즈보다 작은 반도체 디바이스.
  10. 제1항에 있어서, 상기 반도체 칩을 상기 리이드에 전기적으로 접속하는 상기 수단은 금속와이어를 포함하는 반도체 디바이스.
  11. 제1항에 있어서, 상기 반도체 칩을 상기 리이드에 전기적으로 접속하는 도전성 재료로 이루어진 범프를 포함하는 반도체 디바이스.
  12. 제1항에있어서, 상기 리이드는 금속박막이 플라스틱 막에 부착되어 있는 테이프를 포함하고, 상기 반도체 칩을 상기 리이드에 전기적으로 접속하는 상기 수단이 테이프 오토매티드 본딩 기술을 포함하는 반도체 디바이스.
  13. 제1항에 있어서, 상기 반도체 칩이 칩패드 위에 탑재되는 반도체 디바이스.
  14. 제1항에 있어서, 상기 반도체 칩의 회로 형성표면은 절연막을 거쳐 상기 리이드에 본딩되는 반도체 디바이스.
  15. 제1항에 있어서, 상기 반도체 칩의 회로 형성표면의 반대 표면은 절연막을 거쳐 상기 리이드에 본딩되는 반도체 디바이스.
  16. 제13항에 있어서, 상기 패키지 표면에서 상기 칩패드에 이르는 구멍이 마련되는 반도체 디바이스.
  17. 제16항에 있어서, 상기 칩패드에 접속하는 도전성 재료로 이루어진 범프는 상기패키지에서 상기 칩패드에 이르는 구멍의 내부에 마련되어 있는 반도체 디바이스.
  18. 제1항에 있어서, 플라스틱 몰드 돌기가 상기 패키지 표면위에 마련되어 있는 반도체 디바이스.
  19. 제1항에 있어서, 상기 리이드는 상기 패키지에 마련된 상기 구멍에 의해 노출된 부분의 구멍을 거쳐 마련되는 반도체 디바이스.
  20. 제19항에 있어서, 상기 리이드에 접속하는 도전성 재료의 범프는 상기 구멍의 일부 또는 전부내에 마련되어 있고, 상기 관통구멍은 상기 도전성 재료로 채워지는 반도체 디바이스.
  21. 제1항과 같은 반도체 디바이스가 적층된 여러개의 반도체 디바이스 및 각 반도체 디바이스 내에 마련된 상기 구멍에 배치된 도전성 재료에 의해 서로 접속되어 있는 각 반도체 디바이스의 리이드를 포함하는 반도체 장치.
  22. 제21항에 있어서, 적층된 적어도 하나의 반도체 디바이스는 연산처리 기능을 갖는 반도체 칩을 갖고, 반도체 디바이스의 다른 하나는 메모리 칩을 가지는 반도체장치.
  23. 제1항과 같은 반도체 디바이스의 한쪽 표면에 하나 이상의 전자부훔이 마련되고, 상기 전자부품의 외부단자와 상기 반도체 디바이스의 상기 리이드가 도전성 재료에 의해 서로 전기적으로 접속되는 반도체 장치.
  24. 제23항에 있어서, 상기 반도체 디바이스는 연산처리 기능을 갖는 반도체 칩을 가지고, 상기 전자부품은 메모리 칩을 가지는 반도체장치.
  25. 반도체 칩,리이드 및 상기 칩을 상기 리이드에 전기적으로 접속하는 수단을 포함하고, 플라스틱으로 이들을 봉입하여 패키지를 형성하며 반도체 디바이스는 형성하며 반도체 디바이스는 상기 패키지의 적어도 한쪽 표면에 마련된 구멍을 포함하며, 상기 구멍은 상기 패키지 내부의 상기 리이드의 표면에 이르고 상기 패키지의 내부를 향해 점점 좁아지는 데이퍼로 형성되는 반도체 디바이스.
  26. 반도체 칩,리이드 및 상기 칩을 상기 리이드에 전기적으로 접속하는 수단을 포함하고, 플라스틱으로 이들을 봉입하여 패키지를 형성하며, 반도체 디바이스는 상기 패키지에서 돌출하지 않는 상기 리이드, 한쪽 끝이 내부 리이드의 여러 부분에 접속되고 다른 끝이 상기 패키지의 표면에서 돌출하도록 봉입 플라스틱 부분을 관통하는 도전성 재료, 상기 도전성 재료와 각 주기성 사이의 공간을 형성하는 봉입 플라스틱 포함하는 반도체 디바이스.
  27. 제26항에 있어서, 상기 도전성 재료는 땜납인 반도체 디바이스.
  28. 반도체 칩, 리이드 및 상기 칩을 상기 리이드에 전기적으로 접속하는 수단을 포함하고, 이들을 플라스틱으로 봉입하여 패키지를 형성하며, 반도체 디바이스는 상기 패키지의 한쪽 표면에서 반대 표면에 이르는 관통구멍을 포함하고, 상기 관통구멍은 상기 패키지 내부의 상기 리이드에 의해 차단되는 반도체 디바이스.
  29. 반도체 칩을 피하기 위해 하부 몰드와 마주하는 상부 몰드로 플라스틱을 봉입하는 다이의 상부 몰드와 하부 몰드 위에 여러개의 돌기를 형성하는 스텝, 사익 돌기 사이에 리이드 프레임을 놓는 스텝, 상기 다이에 봉입 플라스틱을 흐르게 하는 스텝을 포함하는 반도체 디바이스의 제조방법.
  30. 제3항 또는 제27항과 같은 반도체 디바이스의 패키지 표면 위에 마련된 구멍내에 크림땜납을 채우는 스텝, 그후 땜납범프를 형성학 위해 가열하는 스텝을 포함하는 반도체 디바이스의 제조방법.
  31. 여러개의 리이드와 상기 리이드를 지지하는 외부 프레임을 포함하고, 다른 부분보다 넓은 부분이 상기 리이드의 일부 또는 전부에대해 각 리이드를 위해 마련되는 리이드 프레임.
  32. 제31항에 있어서, 다른 부분보다 넓은 상기 리이드 부분에 관통구멍이 마련되어 있는 리이드 프레임.
  33. 제31항에 있어서, 다른 부분보다 넓은 상기 리이드 부분에 땜납의 습윤도를 향상하기 위해 표면처리 되는 리이드 프레임.
  34. 여러개의 리이드, 그 위에 반도체 칩을 탑재한 칩패드, 상기 칩패드를 지지하는 패드 서스펜딩 리이드 및 이들을 지지하는 프레임을 포함하고, 다른 부분보다 넓은 부분이 상기 리이드의 일부 또는 전부에 대해 각 리이드의 일부에 마련된 리이드 프레임.
  35. 제34항에 있어서, 다른 부분보다 넓은 사이 리이드 부분에 관통구멍이 마련되는 리이드 프레임.
  36. 제34항에 있어서, 다른 부분보다 넓은 상기 리이드 부분에 땜납의 습윤도를 향상하기 위해 표면처리 되는 리이드 프레임.
  37. 제34항에 있어서, 칩패드와 마주하는 인접 리이드 사이의 공간이 주기성을 가지는 리이드 프레임.
  38. 반도체 디바이스의 플라스틱 패키지의 내부의 리이드와 기판이 도전성 부재에 의해 서로 접속하고, 기판과 리이드의 접속부분이 플라스틱으로 측면에서 덮혀져 있고 구멍이 상기 반도체 디바이스 기판의 반대측의 상기 도전성 재료에 대응하는 위치에 형성되는 탑재기판.
  39. 제1,2 또는 25항과 같은 반도체 디바이스를 기판 위에 탑재하는 탑재기판.
  40. 제17항과 같은 반도체 디바이스를 탑재하는 탑재기판에 있어서, 상기 칩패드에 접속되는 도전성 재료는 납땜이고, 상기 반도체 디바이스는 상기 프린트 회로 기판 위에 마련되어 있는 와이어 패턴에 땜납되는 탑재기판.
  41. 프린트 회로 기판상에 제18항과 같은 반도체 디바이스를 탑재하는 탑재기판에 있어서, 상기 돌기와 상기 프린트 회로 기판은 서로 접촉한 상태로 탑재되어 있는 탑재기판.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940004332A 1993-03-17 1994-03-07 반도체 디바이스 및 그 제조방법과 리이드 프레임 및 탑재기판 KR0121735B1 (ko)

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