KR940006579B1 - Semicondoctor package - Google Patents
Semicondoctor package Download PDFInfo
- Publication number
- KR940006579B1 KR940006579B1 KR1019910019282A KR910019282A KR940006579B1 KR 940006579 B1 KR940006579 B1 KR 940006579B1 KR 1019910019282 A KR1019910019282 A KR 1019910019282A KR 910019282 A KR910019282 A KR 910019282A KR 940006579 B1 KR940006579 B1 KR 940006579B1
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- lead
- semiconductor package
- semiconductor
- semiconductor chip
- package
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
제1도는 종래 반도체 패키지의 단면도.1 is a cross-sectional view of a conventional semiconductor package.
제2도는 이 발명에 따른 반도체 패키지의 단면도이다.2 is a cross-sectional view of a semiconductor package according to the present invention.
이 발명은 반도체 패키지에 관한 것으로, 특히 패키지 몸통과 내부리이드를 관통하는 관통구를 도전물질로 채우고 외부로 소정부분을 돌출시켜 아웃리이드로 사용하는 반도체 패키지에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly, to a semiconductor package used as an outlead by filling a through hole penetrating through the package body and an inner lead with a conductive material and protruding a predetermined portion to the outside.
최근의 반도체장치의 고집적화, 메모리용량의 증가, 신호처리속도 및 소비전력의 증가 그리고 고밀도 실장의 요구등의 추세에 따라 반도체 패키지에 대한 연구도 점차로 활발해지고 있다.With the recent trend of high integration of semiconductor devices, increase in memory capacity, increase in signal processing speed and power consumption, and demand for high-density packaging, research on semiconductor packages is also increasingly active.
반도체장치의 고집적화 및 메모리 용량의 증가는 입출력 단자의 수를 증가시켜 반도체 패키지의 리이드의 배치가 어려워지고 있으며, 신호처리속도 및 소비전력의 증가로 반도체장치에서 발생하는 열의 방출을 고려하여야 한다. 또한 고밀도 실장을 위해 반도체 패키지를 다층으로 형성하는 적층패키지(Stack Package)방법이나 칩을 집적 인쇄회로기판(Pring Circuit Board ; 이하 PCB로 칭항)에 실장하는 방법(Chip OnBoard ; 이하 COB라 칭함) 등이 연구실행되고 있다.Higher integration of semiconductor devices and increased memory capacities increase the number of input / output terminals, making it difficult to arrange the leads of semiconductor packages. Consideration should be given to the release of heat generated in semiconductor devices due to the increase in signal processing speed and power consumption. In addition, a stack package method for forming a semiconductor package in multiple layers for high-density mounting, or a chip mounted on a Pring Circuit Board (hereinafter referred to as PCB) (Chip OnBoard; referred to as COB) This research is being carried out.
제1도는 종래 반도체 패키지의 단면도이다. 중심부에 사각형상의 다이패드(1)가 형성되어 있으며, 상기 다이패드(1)상에 반도체칩(3)이 실장되어 있다. 상기 다이패드(1)의 주변에 일정간격을 유지하여 리이드(8)가 형성되어 있다. 상기 리이드(6)는 반도체칩(3)과 본딩되는 내부리이드(4)와 절곡되어 PCB기판과 연결되는 외부리이드(5)로 구성되어 있다. 상기 반도체칩(3)상의 본딩패드(7)와 내부리이드(4)가 와이어(9)로 연결되어 있다. 반도체칩(3), 다이패드(1), 와이어(9) 및 내부리이드(4)를 감싸도록 패키지 몸통(10)이 형성되어 있다.1 is a cross-sectional view of a conventional semiconductor package. A rectangular die pad 1 is formed in the center portion, and the semiconductor chip 3 is mounted on the die pad 1. A lead 8 is formed around the die pad 1 while maintaining a predetermined interval. The lead 6 is composed of an inner lead 4 bonded to the semiconductor chip 3 and an outer lead 5 which is bent and connected to the PCB substrate. The bonding pad 7 and the inner lead 4 on the semiconductor chip 3 are connected by a wire 9. The package body 10 is formed to surround the semiconductor chip 3, the die pad 1, the wire 9, and the inner lead 4.
상기와 같이 반도체칩과 내부리이드가 와이어로 본딩되고, 외부리이드에 의해 PCB와 연결되는 종래의 반도체 패키지는 외부리이드가 PCB와 연결되므로 PCB의 면적을 많이 차지하여 실장밀도가 떨어지고, 불량발생시 패키지의 교체가 어려운 문제점이 있다.As described above, the conventional semiconductor package in which the semiconductor chip and the inner lead are bonded to the wire and connected to the PCB by the outer lead has a large area of the PCB because the outer lead is connected to the PCB, thus reducing the mounting density. There is a problem that is difficult to replace.
또한, 종래의 반도체 패키지는 패키지를 적층하기 위해서는 반도체 패키지의 소정부분에 적층되는 패키지의 입출력단자로 쓰기위한 홈을 따로 형성하여야 하므로 공정이 복잡한 문제점이 있다.In addition, in the conventional semiconductor package, in order to stack the package, a groove for writing as an input / output terminal of the package stacked on a predetermined portion of the semiconductor package must be separately formed, which causes a complicated process.
따라서, 이 발명의 목적은 PCB의 면적을 절감하여 실장밀도를 높일 수 있고, 불량발생시 교체가 용이한 반도체 패키지를 제공함에 있다.Accordingly, an object of the present invention is to provide a semiconductor package that can increase the mounting density by reducing the area of the PCB, it is easy to replace when a failure occurs.
이 발명의 다른 목적은 쉽게 적층할 수 있는 반도체 패키지를 제공함에 있다.Another object of the present invention is to provide a semiconductor package that can be easily stacked.
상기와 같은 목적들을 달성하기 위하여 이 발명은 반도체 패키지에 있어서, 회로가 형성되어 있는 반도체칩과, 상기 반도체칩과 범프가 연결되는 리이드와, 상기 반도체칩 및 리이드를 감싸는 몸체와, 상기 몸체의 소정부분에 형성된 관통구들과, 상기 관통구들을 메꾸고 의부로 소정부분 돌출되도록 형성된 도전체들을 구비하는 것을 특징으로 한다.In order to achieve the above objects, the present invention provides a semiconductor package comprising: a semiconductor chip in which a circuit is formed; a lead connected to the semiconductor chip and a bump; a body surrounding the semiconductor chip and the lead; And through-holes formed in the portion, and conductors formed to fill the through-holes and protrude to a predetermined portion.
제2도는 이 발명에 따른 반도체 패키지의 단면도이다. 소정회로가 형성되어 있는 반도체칩(11)의 표면에 리이드와의 접촉을 위해 범프(13)가 헝성되어 있으며, 상기 범프(13)가 반도체칩(11)과 리이드(15)을 연결하고 있다. 상기 반도체칩(11)과 리이드(15)는 칩이 리이드 위에 부착되는 COL(Chip On Lead), 리이드가 칩위에 부착되는 LOC(Lead On Chip)방식과 TAB(Tape Automated Banding) 방식등이 적용될 수 있다. 상기 반도체칩(11)과 리이드(15)를 감싸도록 폴리이미드(Polyimide)등과 같은 열경화성 수지로 몸체(17)가 형성되어 있다.2 is a cross-sectional view of a semiconductor package according to the present invention. A bump 13 is formed on the surface of the semiconductor chip 11 on which a predetermined circuit is formed to contact the lead, and the bump 13 connects the semiconductor chip 11 and the lead 15. The semiconductor chip 11 and the lead 15 may be applied to a chip on lead (COL) in which the chip is attached to the lead, a lead on chip (LOC) method in which the lead is attached to the chip, and a tape automated banding (TAB) method. have. The body 17 is formed of a thermosetting resin such as polyimide to surround the semiconductor chip 11 and the lead 15.
상기 몸체(17)의 소정부분에 리이드(15)를 관통하도록 관통구(Through Hole ; 18)가 형성되어 있으며, 상기 관통구(18)에 Ag 또는 Au등을 함유한 도전형 에폭시로 도전체(19)가 형성되어 있다. 상기 도전체(19)는 종래 반도체 패키지의 외부리이드의 역활을 한다. 상기 도전체(19)의 하부에 돌출부(20)가 형성되어 있으며, 상기 돌출부(20)는 상기 구조의 반도체 패키지를 PCB에 전기적, 기계적으로 연결한다.A through hole 18 is formed in a predetermined portion of the body 17 so as to penetrate the lead 15, and the conductive hole is made of a conductive epoxy containing Ag or Au in the through hole 18. 19) is formed. The conductor 19 serves as an external lead of a conventional semiconductor package. A protrusion 20 is formed below the conductor 19, and the protrusion 20 electrically and mechanically connects the semiconductor package of the structure to the PCB.
또한 상기 돌출부(20)가 형성된 반대쪽에는 반도체 패키지의 적층을 위한 홈(21)이 돌출부(20)와 같은 크기로 형성되어 있다. 상기 홈(21)에 의해 적층될 다른 반도체 패키지와 전기적, 기계적으로 연결된다. 상기에서 반도체칩(11)과 리이드(15)가 TAB방식으로 본딩될 경우 상기 관통구(18)는 테이프를 관통하도록 형성할 수도 있다. 메모리 반도체 패키지의 경우 반도체칩과 연결되지 않는 비접촉 리이드가 존재한다. 이 발명의 경우에는 리이드(15)를 관통하지 않고 단지 PCB와의 기계적 연결만을 위한 도전체(19)를 형성할 수도 있다.In addition, the groove 21 for stacking the semiconductor package is formed to the same size as the protrusion 20 on the opposite side where the protrusion 20 is formed. The groove 21 is electrically and mechanically connected to another semiconductor package to be stacked. In the case where the semiconductor chip 11 and the lead 15 are bonded by the TAB method, the through hole 18 may be formed to penetrate the tape. In the case of the memory semiconductor package, there is a non-contact lead that is not connected to the semiconductor chip. In the case of this invention, it is also possible to form the conductor 19 only for mechanical connection with the PCB without penetrating the lead 15.
상술한 바와 같이 이 발명은 외부리이드를 형성하지 않고 패키지 몸통과 리이드를 관통하는 돌출구를 가지는 도전체를 형성하여 PCB와의 전기적, 기계적 연결단자로 사용한다.As described above, the present invention forms a conductor having a protrusion through the package body and the lead without forming an external lead, and is used as an electrical and mechanical connection terminal with the PCB.
따라서 이 발명은 반도체 패키지가 차지하는 PCB의 면적을 절감하여 실장밀도를 높일 수 있고, 불량발생시 반도체 패키지의 교체가 용이한 이점이 있다.Therefore, the present invention can increase the mounting density by reducing the area of the PCB occupied by the semiconductor package, there is an advantage that it is easy to replace the semiconductor package in the event of a failure.
또한 이 발명은 쉽게 반도체 패키지를 적층할 수 있는 이점이 있다.In addition, the present invention has the advantage that the semiconductor package can be easily stacked.
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910019282A KR940006579B1 (en) | 1991-10-31 | 1991-10-31 | Semicondoctor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910019282A KR940006579B1 (en) | 1991-10-31 | 1991-10-31 | Semicondoctor package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR930009033A KR930009033A (en) | 1993-05-22 |
| KR940006579B1 true KR940006579B1 (en) | 1994-07-22 |
Family
ID=19322073
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019910019282A KR940006579B1 (en) | 1991-10-31 | 1991-10-31 | Semicondoctor package |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR940006579B1 (en) |
-
1991
- 1991-10-31 KR KR1019910019282A patent/KR940006579B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR930009033A (en) | 1993-05-22 |
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