KR930002390B1 - Mark transformation device for digital signal - Google Patents

Abstract

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Description

Code conversion device for recording and reproducing digital signals

1 is a block diagram of a code conversion device according to the present invention.

2 is a block diagram of a reproduction code conversion device according to the present invention.

3 is a detailed block diagram of a secondary code converter applied to the apparatus of the present invention.

4 is a detailed block diagram of an amplitude detector applied to the apparatus of the present invention.

5 is a block diagram of a conventional device.

6 is a block diagram of another embodiment of a conventional apparatus.

* Explanation of symbols for main parts of the drawings

1,15: Mapping code converter 2: Parallel-to-serial converter

3: secondary code converter 4: non-zero return inverter

5,8: record and play amplifier 6,7: record and playhead

9: moving unit 10: amplitude detector

11: clock recovery unit 12: shaping circuit

13: inverse converter 14: series-to-parallel converter

20,22: Buffer 21,13-1: Time controller

23,13-2: Counter 24: Inverter

25: multiplexer 26,27: OP amplifier

28: Orgate

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a code conversion device for recording and reproducing digital signals in a recording and reproduction system of a digital video cassette recorder using magnetic tapes and rotating heads. In particular, an 8-8 (bit-bit) mapping rule is used. By first performing code conversion, a few redundant bits per code are added to perform code conversion secondly, thereby enabling high-density digital magnetic recording and reproduction. As is well known, the frequency characteristics of the recording and reproducing systems of the video cassette recorder (VCR) usually have bandpass characteristics, and the reproduction heads have differential characteristics, so that they cannot be reproduced with low frequency components.

The reason is that it is difficult to transmit a very low frequency component by allowing electrical coupling between the signal circuit and the rotating head through the rotary transformer. In addition, the high frequency characteristics of the VCR are degraded by the gap loss between the head and the tape or the head gap loss, and also when the pulse variation is detected by the gap variation between the head and the tape and the level variation or jitter caused by external noise. This affects the waveform and generates ether.

Therefore, high density recording is required in a digital VCR. Therefore, a digital signal must be converted into a code signal having a waveform suitable for magnetic recording and reproduction characteristics. Among these codes, a number of schemes using block codes have been proposed, representative of which are 8-8 mapping nonzero return (NRZ) / nonzero return inversion (NRZ-I) conversion methods, and 8-9NRZ / NRZ-I. Conversion methods, 8-10 NRZ / NRZ / I conversion methods, and 8-1 NRZ / NRZ-I conversion methods.

However, the 8-10 and 8-14 conversion methods have more redundancy bits and have a narrower detection window at the time of playback than the 8-8 and 8-9 conversion methods even though the DC component is almost zero. There is a disadvantageous combination of high density recordings. Therefore, a block code that can minimize the DC component as small as possible to add redundant bits is required, which is basically 8-8 mapping codes, and various mapping rules for minimizing the DC component have appeared. . As an example, as in Japanese Patent Laid-Open No. 59-205858 shown in FIG. 5, a low pass filter 30 for removing distortion in sampling an image signal input from the video signal input terminal IW, and A / D converter 31 for converting the filtered video signal into a digital signal, a channel coder including an 8-8 code converter 32, a sample inversion non-inverting circuit 33, and an inversion non-inverting control circuit 34 ( 35), a CDS (Codeword Digital Sum) code is assigned and mapped to a code with a relatively high frequency in the recorded data, and the code is inverted and non-inverted for each unit.

As another example, the method proposed in Japanese Patent Laid-Open No. 60-178783 constitutes a conversion label having a predetermined quantization level number by selecting a code group having a large number of consecutive numbers of '1' or '0' at the beginning and end of the code. The table converts and records the input data into codes having a continuous number of '1' or '0' less than or equal to a predetermined value. As another example, the A / D and D / A converters 40 and 45, and the error correction encoder and decoder 41 and 46, as in Japanese Patent Laid-Open No. 61-73425 shown in FIG. And first and second diagrams 42 and 47 and polarity controllers 43 and 48 to optimize the weight order of the quantized code level for the n-bit code, and to reverse the strong code. To do it.

However, the above examples require complicated and complex mapping rules to minimize the DC component in the case of the 8-8 mapping transform which performs the code conversion without adding redundant bits in common. Nevertheless, only 8-8 mappings are required to record. In this case, it is relatively ineffective for the increase of the DC component that occurs frequently at the junction of adjacent codes, so DSV (Digital Sum Variation) or CDS (Codeword) for data between codes after conversion

It is necessary to add a means for inverting and non-inverting the sign by calculating the digital sum. The circuit for such a calculation is not only very complicated but also has a difficult problem of more accurately dealing with the polarity of the inverted data during reproduction.

The present invention has been made to eliminate the complexity of the mapping rule and the inefficiency of the inversion non-inverting control means when using the 8-8 mapping transformation, which is a conventional problem, and uses the existing 8-8 mapping rule. For the odd and odd levels of the quantization level, the division is assigned to the positive and negative levels, and the code is converted first to be separated into a signal having a high correlation by corresponding the code to the original code, and the first code conversion is performed. It is possible to record the data with less inversion between consecutive codes by configuring the data to be delayed by one bit period in 8-bit units so that the inversion between consecutive codes can be performed. Digital signal can be easily restored to the original code to effectively achieve high density digital magnetic recording and reproduction It is an object of the present invention to provide a code conversion device for recording and reproducing data.

Hereinafter, the configuration of the present invention with reference to the accompanying drawings in detail. The apparatus of the present invention assigns the positive and negative levels of the odd and odd numbers of the quantization level in the 8-bit digital code input from the input terminal IN as shown in FIGS. A mapping code converter (1) for first-order conversion into a parallel code so that the code corresponds to the original code to be separated into a strong correlation signal, and a parallel-serial for converting the parallel code converted by the mapping code converter (1) into a serial code; A second order that separates the serial code data converted by the converter 2 and the parallel-to-serial converter 2 into 8 bits and adds inverted bits from the last bit to suppress the DC component and convert the data into a 9-bit data string. A non-zero return inverter (4) for converting the magnetization state only when 1 is transmitted in the non-zero return inversion scheme from the code converter (3) and the 9-bit data output from the secondary code converter (3); remind Zero return inverter (4) outputs a predetermined write amplifier 5, the code conversion device at the time of the recording to amplify a recording signal for output to the recording head (6) of the; A reproduction amplifier 8 for amplifying the video signal reproduced from the reproduction head 7, a moving imager 9 for compensating for the image signal reproduced and amplified by the amplifier 8, and the moving imager 9 An amplitude detector (10) and a clock recoverer (11) for amplitude detection and clock regeneration in the compensated reproduced video signal, and a shaping circuit section for shaping the output data of the amplitude detector (10) and the playback clock of the clock recoverer (11) 12), an inverse transformer 13 which firstly inversely converts the added bits from the output circuits from the shaping circuit unit 12, and the serial code output removed by the inverse transformer 13 into parallel codes. And a serial-to-parallel converter 14 for conversion and a mapping code converter 15 for reconstructing the parallel code converted by the serial-parallel converter 14 to the original code. will be.

In addition, the secondary code converter 3 of the code conversion device described above is a clock that is generated so as to delay the time of 1 bit period in 8-bit units of serial code data divided into 8 bits as shown in FIG. A time controller 21 for controlling the control, a buffer 20 and 22 for temporarily latching serial code data converted by the control of the time controller 21, and alternately selecting and outputting the data in an 8-bit unit; A counter 23 for counting 8 bits of serial code data in units of 8 bits, an inverter 24 for inverting every last 8th bit counted by the counter 23, and the buffers 20 and 22. The multiplexer 25 multiplexes the bit inverted by the inverter 24 to the 8-bit data which is time-delayed by using the multiplexer 25.

In addition, the amplitude detector 10 of the reproduction code converter is a window comparator structure as shown in FIG. 4, and the moving picture data is recorded by comparing the positive reference voltage Va and the negative reference voltage Vb. Two OP amplifiers 26 and 27 for amplitude detection during reproduction at output Sc and each output compared in the OP amplifiers 26 and 27 as input sources for moving image output Sc. When the positive reference voltage Va and the moving device output Sc <negative polarity reference voltage Vb, a 'high' signal, and the negative reference voltage Vb <the synchronizer output Sc, <the positive reference It is provided with an or gate 28 for outputting a 'low' signal when the voltage Va. Referring to Figures 1 to 4 the effect of the present invention configured as described above is as follows.

First, as illustrated in FIG. 1, when the code conversion operation at the time of recording is described, when the digital code data from the input terminal IN is applied to the mapping code converter 1, the mapping code converter 1 converts the input digital code to 1. Convert to car The conversion rule of the mapping code converter 1 distinguishes the odd and odd numbers of the quantization level and assigns them to the positive (+) level and the negative (-) level, and the corresponding codes correspond to the circle codes so that the signal has a strong correlation. To be separated.

In this way, the first-order code is converted into a serial code by the parallel-to-serial converter 2 as a parallel code and applied to the secondary code converter 3. At this time, in the secondary code converter 3, as shown in FIG. 3, the time controller 21 delays the input data by 8 bit units by 1 bit period and alternately selects 8 bit units. When the serial code data is counted in units of 8 bits by (23) and outputted to the inverter 24, the inverter 24 inverts the last eighth bit counted by the counter 23 to the last of the delayed eight bits. DC multiplexing can be performed by adding only one bit to eight bits by means of the multiplexer 25 added after the bit so as to remove a sequence of '1' or '0' that may increase between the subsequent consecutive codes.

According to the second-order code conversion operation, the added bits are superior to the DC component suppression between adjacent codes even though redundant bits are added during the same 8-9 conversion. Accordingly, the write amplifier 5 converts the magnetization state only when '1' is transmitted by the nonzero return inverter 4 which performs nonzero return (NRZ) data recording after the secondary conversion in the secondary code converter 3. By recording through), it is possible to record with little inversion between consecutive codes.

On the other hand, in the case of reproducing the recording signal subjected to the code conversion at the time of recording, the video signal reproduced from the reproduction head 7 is reproduced by the reproduction amplifier 8 and the video player (similar to the code conversion device at the time of reproduction shown in FIG. 9) amplified and compensated, and applied to the amplitude detector 10 and the time controller 11 for amplitude detection.

At this time, the output Sc of the moving device 9 is a positive reference voltage Va and a negative reference voltage Vb in a window comparator composed of two OP amplifiers 26 and 27, respectively, as shown in FIG. The output of the OR gate 28 whose output value is compared and compared by Positive reference voltage (Va) or moving device output (Sc) <Negative reference voltage (Vb), '1' (high), and negative reference voltage (Vb) <Sync output (Sc) <positive Outputs '0' (low) when the polarity reference voltage (Va) is in order.

The output signal detected by the amplitude detector 10 in this manner is subjected to the inverse conversion of the shaped data formed by the shaping circuit section 12 composed of D flip flops together with the input clock regenerated from the clock recoverer 11. To the inverse transformer (13).

At the same time, the inverse converter 13 delays the bits in 9 bit units to remove 1 bit added by the time controller 13-1, and every 8 bits by the counter 13-2 therein. The counted data are alternately operated to remove one bit added to the last bit, and at the same time, inversely transformed to form a serial code.

Therefore, the first inversely transformed code data is converted into parallel code through the serial-to-parallel converter 4, and then restored by the mapping code converter 15 to the original code and output to the digital video cassette record.

As described above, according to the present invention, in addition to the conventional 8-8 mapping conversion rule, the digital magnetic recording and reproduction are performed by a simple rule and a secondary conversion that adds some redundant bits. Inefficiency by means of inversion, non-inversion, etc. can be reduced, and the conversion rule is simple, and since it adds arbitrary bits by simple bit inversion, it is not only very easy to realize circuitally but also by simple rules. As a result, the original code can be simply restored to the original code even during the inverse conversion process during playback, thereby making it possible to perform high-density digital magnetic recording reproduction more effectively.

Claims (4)

The 8-bit digital code input from the input terminal (IN) is assigned to the positive and negative levels for the odd and odd numbers of the quantization level. A mapping code converter 1 for first-order conversion into a parallel code so as to be separated, a parallel-to-serial converter 2 for converting the parallel code converted from the mapping code converter 1 into a serial code, and the parallel-to-serial converter ( A second code converter (3) for dividing the serial code data converted in 2) into 8 bits and adding a bit inverted in the last bit thereof to suppress a DC component and convert the serial code data into a 9-bit data sequence; The non-zero return inverter 4 converts the magnetization state only when 1 is transmitted in the non-zero return inversion scheme from the 9-bit data output from (3), and the output of the non-zero inverter 4 With record signal Width by the recording amplifier 5, the code conversion device at the time of recording is configured to output to the recording head (6) and; A recording and reproducing amplifier 8 for amplifying the video signal reproduced from the reproduction head 7, a moving imager 9 for compensating for the image signal reproduced and amplified by the reproducing amplifier 8, and the moving imager ( 9) Amplitude detector 10 and clock recoverer 11 for amplitude detection and clock regeneration in the reproduced video signal compensated through 9), and output data of the amplitude detector 10 and regenerated clock of clock recoverer 11 are formed. A shaped circuit section 12, an inverse converter 13 for first inverse transforming to remove the added bits from the output data shaped from the shaped circuit section 12, and serial code data removed from the inverse converter 13 Converts a serial-to-parallel converter 14 for converting the signal into a parallel code; and a mapping code converter l5 for reconstructing the parallel code converted by the serial-to-parallel converter 14 back to the original code. Of the digital signal Code conversion device for recording and playback. The time for controlling the clock generated according to claim 1, wherein the secondary code converter (3) of the code conversion device (100) controls the clock generated by delaying the time by 1 bit period in 8-bit units of serial code data separated by 8 bits. The controller 21, a buffer 20X22 for temporarily latch-controlling the serial code data converted by the time controller 21, and alternately selecting and controlling the output in 8-bit units, and 8-bit code data 8 bits. A counter 23 counting in units of 8 bits, an inverter 24 for inverting every last eighth bit counted by the counter 23, and 8-bit data delayed through the buffers 20 and 22; And a multiplexer (25) for multiplexing so that the bits inverted by the inverter (24) are added to the coder. The amplitude detector (10) of the code conversion device (100) according to claim 1, wherein the amplitude detector (10) of the code conversion device compares the positive polarity reference voltage (Va) with the negative polarity reference voltage (Vb) and reproduces the data at the moving image output (Sc). OP amplifiers 26 and 27 having a window comparator function to perform amplitude detection, and an OR gate 28 for ORing the outputs of the OP amplifiers 26 and 27 to the shaping circuit unit 12. A code conversion device for recording and reproducing a digital signal. The inverse transformer 13 is a counter 13-2 for counting 8 bits to remove 1 bit of data added when reproducing the recorded data, and 8 sequentially for 9-bit data. A code conversion device for recording and reproducing a digital signal provided with a time controller (13-1) for controlling to select alternately bit by bit.