KR900003668B1 - Method to synthesize and transmit clock signals of t.d.m. switching - Google Patents

Abstract

The circuit includes a synchronous signal genertor (13) for generating synchronous signal according to logic state of output signal of divider (12), a synthesizer (B1) for synthesizing reference clock signal and synchronous signal, a transmitter (14) for transmitting synthesized clock signal to transmitting cable, a receivcer circuit (15) for receiving synthesized clock signal, a dividing circuit (32) for dividing synthesized clock signal, and a counter (33) reset by synchronous signal for dividing reference clock signal into a few parts.

Description

Clock Signal Synthesis Transmission Method of Time Division Exchange

1 is a system block diagram according to a conventional clock signal transmission method.

2 is a timing diagram of each part of FIG. 1;

3 is a block diagram of a clock signal synthesis transmission and separation device according to the present invention.

4 is an operating waveform diagram of each part of FIG.

FIG. 5 is a detailed view showing one embodiment of a synthesis circuit, a separation circuit and a counter circuit during the third embodiment. FIG.

* Explanation of symbols for main parts of the drawings

11: oscillation circuit 12: frequency division circuit

13 synchronization signal generating circuit 14 transmission circuit

15: receiving circuit 16,33: counter circuit

31: synthetic circuit 32: separate circuit

51 AND gate 52 monostable multivibrator

53: delay circuit

54: Asynchronous Resetable Counter

The present invention relates to a clock signal transmission method of a time division switching system. In particular, in the transmission of a system basic clock and a synchronization signal required for a time division electronic switching system, two signals are synthesized by a transmitter in a single cable unlike a conventional transmission method. The present invention relates to a clock signal synthesis transmission method in which a transmitting unit and a receiving unit can separate and use it.

A conventional clock signal transmission method for transmitting a high frequency clock of a basic clock of a time division exchange and a low frequency clock, which is a synchronization signal in the exchange, using a coaxial cable is shown in the system block diagram of FIG. Here, the basic clock is a time base of the digital circuit in the switching system, and the synchronization signal is a signal for synchronizing the system internal devices. In the transmission of the clock signal having the same configuration as in the first diagram, crosstalk occurs between the high frequency clock signal and the low frequency clock signal. Therefore, the cable routing path should be separated. In addition, when the receiving unit divides the basic clock to generate various clock signals, the counter of the division circuit must be reset for synchronization of the entire system. In this case, the synchronization signal and the basic clock must have a specific phase relationship. However, due to the difference in transmission delay characteristics of the high frequency signal and the low frequency signal, there is a disadvantage in that timing adjustment is required for each receiver. Referring to FIG. 1 and FIG. 2, the waveforms of the basic clock 1 and the synchronization signal 3 have a constraint that they must have the same phase relationship as the second degree at the time of transmission. Depending on the transmission length of the basic clock cable and the synchronization signal cable, the deviation is very difficult to adjust, and there is a disadvantage that the waveform is distorted due to mutual interference between the two signals.

Accordingly, an object of the present invention is to provide a clock signal synthesis transmission scheme in which a system basic clock and a synchronization signal are combined in a transmitter and transmitted by one cable, and the receiver is separately used in clock signal transmission of a time division electronic switch. .

It is still another object of the present invention to prevent crosstalk of a signal by transmitting the system basic clock and a synchronous signal through a coaxial cable, and to remove a change in the phase relationship between the two signals due to a difference in transmission delay characteristics. In providing a way.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. 3 is a system block diagram of a clock signal synthesis transmission and separation device according to the present invention. The oscillation circuit 11 outputting a predetermined basic clock signal and the basic clock signal output from the oscillation circuit 11 are specified. A frequency division circuit 12 for dividing, a synchronization signal generation circuit 13 for outputting a predetermined synchronization signal corresponding to the output signal logic states of the oscillation circuit 11 and the frequency division circuit 12, and the basic clock signal A synthesis circuit 31 for synthesizing the signals and outputting a predetermined synthesis transmission clock signal, a transmission circuit 14 for outputting the synthesis transmission clock signal to a transmission cable, and a synthesis transmission transmitted from the transmission circuit 14 A reception circuit 15 for inputting a clock signal from a transmission cable, a separation circuit 32 for separating the composite transmission clock signal output from the reception circuit 15 into a synchronization signal and a basic clock signal, and outputting the synchronization signal; Reset at the same time as signal And a counter circuit 33 for dividing the basic clock signal by a predetermined division.

4 is an operation waveform diagram of each part shown in FIG. 3, and shows output signal states of each part indicated by (1) to (8) in the figure.

5 is a detailed circuit diagram and an operational waveform diagram according to an embodiment of FIG. 3, (a) is a circuit diagram of a synthesis circuit 31 formed of an AND gate 51, and an input / output waveform diagram thereof (b) Is a circuit diagram composed of a monostable multivibrator 52 and a delay circuit 53 and a counter circuit 33 composed of an asynchronous resetable counter 54 and an input / output waveform diagram thereof. .

Therefore, the operational relationship of the present invention with reference to the above-described configuration as follows.

The oscillation circuit 11 outputs a basic clock signal as shown in FIG.

The basic clock signal is divided by a predetermined frequency in the frequency division circuit 12 to form a division clock with a large period as shown in FIG. 4 (2), and this frequency division clock is used as the basis of the oscillation circuit 11 in the synchronization signal generation circuit 13. The operation is performed logically with the clock signal to form the synchronization signal of FIG. Here, the configuration of the oscillation circuit 11, the frequency divider circuit 12, and the synchronization signal generator circuit 13 for obtaining the synchronization signal shown in FIG. 4 (3) can be easily performed by those skilled in the art. In this case, a plurality of commercially available integrated circuits for logic elements can be used. When the basic clock signal 1 and the synchronization signal 3 are synthesized through the AND gate in the synthesis circuit 31, the basic clock signal 1 and the synchronization signal 3 are synthesized as shown in FIG. 4 (4), and are carried on the transmission cable through the transmission circuit 14. . Then, the reception circuit 15 receives the synthesized signal from the transmission cable and outputs it to the separation circuit 32 to recover the original basic clock signal and the synchronization signal. The separation circuit 32, which is composed of the monostable multivibrator 52 and the delay circuit 53 of FIG. 5 (b), monitors the input synthesized signal by the monostable multivibrator 52. The original synchronizing signal as shown in Fig. 2) is recovered, and at the same time, the delay circuit 53 outputs the synthesized signal as it is after a predetermined dimming delay and recovers the delayed synthesized signal as shown in FIG. This synthesized signal is used in place of the system basic clock 1 output from the oscillation circuit 11 as it is. That is, the counter circuit 16 shown in FIG. 1 of the conventional system uses the basic clock 6 and the synchronization signal 7 of FIG. 2, and this synchronization signal 7 is synchronized with the counter circuit 16. FIG. Since it is used as a type reset signal, it should have exactly the phase relationship as shown in FIG. 2. However, since the counter circuit 33 according to the present invention uses a counter circuit capable of asynchronous reset, the synchronization signal 7 is separated. ) Corresponds to one missing rising pulse section of the delayed composite signal 7 'and is used as a master reset of the division circuits 8 output from the counter circuit 33. do. The phase relationship between the synchronization signal 7 and the delayed synthesized signal 7 'is always constant because it is synthesized with the basic clock signal of the synchronization signal system of FIG. 7 as described above and transmitted through one transmission path. Accordingly, the problem of phase relationship change in the receiver is solved.

As described above, the present invention synthesizes and transmits the basic clock signal and the synchronization signal of the time division all-electronic exchanger, thereby reducing the amount of coaxial cable used, and the phase adjusting operation between the two signals at each receiver. There is no need to do it separately. In addition, as in the conventional method, the trouble of having to consider the path and length of two coaxial cables for each receiver in the system design is eliminated, and in particular, crosstalk between two signals can be fundamentally eliminated, so that a good transmission quality can be obtained. have.

Claims (2)

A clock signal transmission circuit of a time division electronic switch, comprising: an oscillation circuit (11) for outputting a predetermined basic clock signal, a divider circuit (12) for predetermined division of a basic clock signal output from the oscillation circuit (11), and A synchronizing signal generating circuit 13 for outputting a predetermined synchronizing signal corresponding to the output signal logic states of the oscillating circuit 11 and the frequency dividing circuit 12; and a predetermined synthesized transmission clock signal by synthesizing the basic clock signal and the synchronizing signal. A synthesizing circuit 31 for outputting a signal, a transmitting circuit 14 for outputting the synthesized transmission clock signal to a transmission cable, and a reception for inputting a synthesis transmission clock signal transmitted from the transmission circuit 14 from a transmission cable; A circuit 15, a separation circuit 32 which separates and outputs the synthesized transmission clock signal that is the output of the reception circuit 15 into a synchronization signal and a basic clock signal, and the basic clock being reset by the synchronization signal. Signal for a minute And a counter circuit 33 for outputting and synthesizing the basic clock signal and the synchronization signal in the synthesis circuit 31 and transmitting the synthesized clock signal through a single transmission cable as a synthesized clock signal, and separating the received synthesized clock signal from the separated signal. And a clock signal synthesis transmission method of a time division all-electronic exchange, characterized in that the circuit 32 recovers the original basic clock signal and the synchronization signal, respectively. 2. The circuit of claim 1, wherein the separation circuit (32) comprises a monostable multivibrator (52) for recovering a synchronization signal from the composite clock signal, and a delay circuit (53) for delaying and outputting the composite clock signal. A clock signal synthesis transmission method for a time division all-electronic exchange.

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