KR900007929B1 - Voltage ramp speed control circuitry - Google Patents

Abstract

The circuit for linearising the increasing speed of the voltage includes a transistor (16) responding to control signal (RP1-3), a transistor (19) discharging each node voltage, a transistor precharging nodes (21,22,23), a transistor (18) clamping the voltage level not to increase over the break-down voltage, and a transistor (20) applying the fourth node (24) voltage to an output terminal (40) . If the threshold voltage of the transistors are zero volt. the magnitudes of capacitors (C1-4) may be reduced. Also the capacitors may be replaced by the gate capacitance of the depletion transistor whose drain and source terminals are connected in common.

Description

Voltage Ramp Speed Control Circuit

1 (a-b) is a conventional voltage ramp circuit and input and output waveform diagram.

2 is a control signal generation circuit diagram according to the present invention.

3 is an input / output waveform diagram of FIG.

4 is a voltage ramp circuit diagram according to the present invention.

5 is an input / output waveform diagram of FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor circuits, and more particularly to circuits that linearly ramp an applied voltage when voltage is applied.

Circuits that ramp the voltage linearly have a lot of utility. For example, in a nonvolatile memory EEPROM (Electrically Erasable PROM), when a voltage rising time controlled voltage is applied to a memory cell using a voltage ramp circuit during programming, it is applied to a thin gate oxide layer under a floating gate of the nonvolatile memory cell. The stress caused by the electric field can be reduced.

When the program voltage is increased to close to the electronic tunneling speed of the thin gate oxide during programming, the stress of the electric field applied to the thin oxide by the floating gate charge and discharge of electrons may be reduced.

FIG. 1 (a) shows a conventional general voltage ramp control circuit using a resistor and a capacitor. FIG. 1 (b) is an input / output waveform diagram according to the time of FIG.

The voltage ramp circuit using the resistor and the capacitor forms a ramp curve whose output characteristic is Vo as shown in FIG. 1 (b) by the time constant of RC. However, such a circuit requires a large chip area in order to obtain the required time constant hundreds of microseconds, and the output characteristic is not linear, which makes it difficult to control accurate ramp speed.

Accordingly, an object of the present invention is to provide a voltage ramp speed control circuit having a linear rate of increase in voltage and a small consumption area.

It is still another object of the present invention to provide a voltage ramp speed control circuit having a proportional relationship between a clock frequency and a ramp speed of an output signal.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a circuit diagram of an embodiment of a control signal generator for voltage ramp speed control according to the present invention.

Referring to the drawings, when the? Signal and the RP3 signal to be described later are input, the RP1 signal is generated through the logic gate 1 which generates a signal of the "high" state when both signals are "low" state, and the logic gate ( The output of 1) generates an RP2 signal delayed by a predetermined time by continuously connecting the inverting gates 2 and 4, and the signal and the? Signal delaying the output of the logic gate through the inverting gates 2 and 5; Inputs the inverted signal through the inversion gate 3 and outputs the RP3 signal through the logic gate 6 which outputs the "high" state when the RP1 and RP2 are in the "low" state.

3 is an input / output waveform diagram of FIG. 2.

If the ø signal is "low" before the time t1, the output signal RP1 through the logic gate 1 is in the "high" state, and the output signal passing through the two inverting gates 2 and 4 is in the "high" state and is inverted. When the "high" signal output through (2) and (5) and the "high" signal inverting the? Signal are input, the logic gate 6 outputs the "low" state RP3 signal.

After the time t1, when the ø signal is "high", the RP1 signal through the logic gate 1 becomes "low" at the delayed signal t2, and the RP2 signal is "low" at the time t3 delayed by two inverting gates. State, and RP3 becomes "high" after the delayed time t3. When the ø signal is "low" after t5 hours, the RP1 signal becomes "high" at delayed time t6, the RP3 signal is also "low" at t6, and the RP2 signal is delayed at time t7 than the RP1 signal. It is in a "high" state.

The signals generated in the control signal generation circuit configured as shown in FIG. 2 are non-overlap waveforms.

4 is a specific circuit diagram of an embodiment of a voltage ramp circuit according to the present invention.

The RP1, RP2, and RP3 signals output from the control signal generator are supplied to and input to the third node 23, the second node 22, and the first node 21 through the capacitors C1, C2, and C3, respectively. The voltage Vi is input to the input node 25 through the input terminal 30. In addition, the reference voltage generated from the reference voltage generator 35 is supplied to the fourth node 24.

An N-MOS transistor 11 having a channel connected between the input node 30 and the second node 22 and a gate connected to the first node 21, the second node 22, and the fourth node. A channel is connected between the node 24 and the N-MOS transistor 13 having a gate connected to the third node 23 and a channel between the fourth node 24 and the first node 21. The N-MOS transistors 16 connected with the fourth node 24 connected to the gates are transfer transistors responding with the signals of the RP1, RP2, and RP3.

An N-MOS transistor 12 having a channel connected between the second node 22 and the input node 25 and a gate connected to the second node 22, a third node 23, and an input node. A channel is connected between the node 25 and the N-MOS transistor 15 having a gate connected to the third node 23 and a channel between the first node 21 and the fourth node 24. And a channel between the N-MOS transistor 17 having the gate connected to the first node 21, the fourth node 24 and the input node 25, and the gate connected to the fourth node 24. The transistors 19 connected to the transistors 19 are transistors for discharging the voltage of each node.

An N-MOS transistor 14 having a channel connected between the N-MOS transistor 13 and 16 and an input node 25 and a third node 23 and a gate connected to a fourth node 24. The transistors precharge the second node 22, the first node 21, and the third node 23, respectively.

The fourth node is precharged by the voltage generated by the reference voltage generator 35. In the N-MOS transistor 18 in which a channel is connected between the fourth node 24 and the power supply voltage terminal and the gate is grounded, the voltage level of the fourth node 24 is greater than or equal to the breakdown voltage of the transistor 18. It is a clamping transistor that does not increase.

In addition, the N-MOS transistor 20 connects the fourth node 24 to the gate and connects a channel between the input node 25 and the output terminal 40 to output the voltage of the fourth node 24 to the output terminal. 40 is a driver transistor to pass. When the transistor 20 is a depletion transistor, when the input voltage Vi is a high voltage, the maximum value of the input voltage can be linearly ramped to the output voltage Vo and transmitted.

The capacitor C4 connected between the fourth node 24 and the ground receives the amount of charge of the capacitor C2 according to the control signal. The transistors 11, 13, 14, 16 and 17 can be reduced in size by using capacitors having a threshold voltage of zero volts (0 volts). .

In addition, the capacitors C1, C2, C3, and C4 may be formed using a gate capacitance of a diplin transistor in which a drain and a source are bundled together, in addition to a common MOS capacitor, which is a bundle of a common MOS capacitor drain and a source. Those of ordinary skill will readily understand.

FIG. 5 (a) is a waveform diagram of the input voltage V1 supplied to the input terminal of FIG. 4 after inputting the control signal, and FIG. 5 (b) is a waveform diagram of the output voltage Vo output from the output terminal of FIG. .

4 will be described in detail with reference to FIGS. 3 and 5. In the initial state, the N-MOS transistors 16, 19, and 20 are turned on by the voltage generated by the reference voltage generator 35, and thus the first node 21 is charged to the reference voltage.

Even though the input voltage Vi is rapidly applied to the input terminal 30 at t10 hours, if RP1, RP2, or RP3 is not applied, the voltage Vo output to the output terminal 40 is the voltage of the fourth node of the reference voltage generator. Since Vr is supplied, the output voltage Vo becomes Vr-V20 (V20 is the threshold hold voltage of the MOS transistor 20).

First, when RP1 and RP2 are "low" and RP3 is "high" between time t4 and time t6, transistor 13 is "off" and transistor 11 is "on" and transistor 11 Is charged to capacitor C2. At times after t6, when RP1 and RP2 are in the "high" state and RP3 is in the "low" state, the transistor 11 is in the "off" state and the transistor 13 is in the "on" state to turn the transistor 13 on. Through this charge charged to C2 is transferred to C4.

The amount of charge transferred per cycle is V2.C2. V2 may be expressed as the voltage divided by the ratio of the parasitic capacitance Cp of the second node 22 and the capacitor C2 to the swing width of the RP2.

If the above charge transfer is repeated, the capacitor C4 is charged and the voltage V24 or Vr of the fourth node is increased by the charging of the capacitor C4.

At this time, since the output voltage Vo is V24-V20 or Vr-V20, the ramp of the output voltage is achieved by increasing the voltage value of the fourth node 24. The ramping speed of the output voltage Vo can be expressed as follows.

Where fø is the frequency of the ø signal.

Therefore, the ramp speed of the output voltage Vo becomes a constant that can be adjusted according to the frequency of the ø signal and the ratio of the capacitors C2 and C4, thereby enabling a ramp of the linear output voltage Vo.

As described above, the present invention can adjust the ramp speed and the slope of the voltage according to the frequency and the change of the capacitor, the transfer gate, and the control clock, and thus can be usefully used in a circuit requiring the ramp to have a constant slope.

In addition, since the present invention has a ramp speed of a voltage proportional to the frequency of the control clock, it can be used as a frequency-to-voltage ramp speed conversion circuit, and can also be used as a frequency counter in combination with a voltage level sensing circuit.

Claims (4)

A semiconductor device comprising: first capacitor means (C1), second capacitor means (C2), and a first input means for inputting first, second and third signals generated at a control signal generation circuit formed on the same substrate at one stage; A reference voltage supply terminal connected to the three capacitor means C3, the input terminal 30 and the output terminal 40, and a reference voltage generator 35 formed on the same substrate to supply a reference voltage, and an input terminal 30 ), An input node 25 connected to the second node, a second node 21 connected to the third capacitor means C3, a second node 22 connected to the second capacitor means C2, A third node 23 connected to the third capacitor means C3, a fourth node 24 connected to the reference voltage supply terminal, and a fourth node connected between the fourth node 24 and ground. The state of the input node 25 is connected between the capacitor means C4 and the input node 25 and the second node 22 in response to a signal supplied to the first node 21. Before the capacitor means (C2) Is connected between the first transfer means 11, the second node 22 and the fourth node 24, and the state of the second capacitor means C2 in response to the state of the first capacitor means C1. Is connected between the second transfer means 13 and the input node 35 and the second node 22 to transfer the fourth capacitor means C4 to the fourth capacitor means C4 to discharge the voltage of the second node at a predetermined time. A second discharge means 17 connected between the first discharge means 12 and the first node 21 and the fourth node 24 to discharge the voltage of the first node at a predetermined time; The third discharge means 15 connected to the third node 23 and the input node 25 to discharge the voltage of the third node 23 at a predetermined time, and the fourth node 24 and the input. Between the fourth discharge means 19 and the first node 21 and the fourth node 24, which are connected between the nodes 25 and discharge the voltage of the fourth node 24 at a predetermined time. First precharge means 16 connected to precharge the first node 21 with a reference voltage. A first insulated gate field effect transistor 14 having a channel connected between the third node 23 and the input node 25 and a gate connected to the fourth node 24, and an input node 25. Driver transistor 20 for outputting a predetermined signal according to the voltage state of the fourth capacitor means C4 by connecting a channel between the output terminal 40 and the gate and the fourth node 24; And a second insulated gate field effect transistor (18) for connecting a channel between the fourth node (24) and the power supply terminal and having a gate grounded to control the amount of charge of the fourth capacitor means (C4). Voltage ramp speed control circuit. 2. The circuit of claim 1 wherein the driver transistor (20) is a depletion transistor. 3. A zero volt dressing as claimed in claim 2, wherein only the first transfer number 11, the second transfer means 13, the second insulated gate field effect transistor 18 and the first precharge means 16 are zero volts. And a MOS transistor having a hold voltage. The depletion according to claim 2, wherein the first capacitor means C1, the second capacitor means C2, the third capacitor means C3, and the fourth capacitor means C4 have a common drain and source. Circuit characterized in that the transistor.

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