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KR890015157A - 고속 디지탈 신호처리 프로세서 - Google Patents

고속 디지탈 신호처리 프로세서 Download PDF

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Publication number
KR890015157A
KR890015157A KR1019890003321A KR890003321A KR890015157A KR 890015157 A KR890015157 A KR 890015157A KR 1019890003321 A KR1019890003321 A KR 1019890003321A KR 890003321 A KR890003321 A KR 890003321A KR 890015157 A KR890015157 A KR 890015157A
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data
output
input
storage means
coefficient
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KR1019890003321A
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KR0130772B1 (ko
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도오루 바지
히로쯔구 고지마
나리오 스미
요시무네 하기와라
신야 오바
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미다 가쓰시게
가부시끼가이샤 히다찌세이사꾸쇼
다께이 유끼오
히다찌디바이스엔지니어링 가부시끼가이샤
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Data Mining & Analysis (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Algebra (AREA)
  • Databases & Information Systems (AREA)
  • Computing Systems (AREA)
  • Computer Hardware Design (AREA)
  • Complex Calculations (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
  • Image Processing (AREA)

Abstract

내용 없음

Description

고속 디지탈 신호처리 프로세서
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도는 본 발명의 1실시예에 의한 프로세서의 회로블럭도. 제 5 도는 본 발명이 신호처리 알고리듬, 제10도는 본 발명의 1실시에에 사용되는 제어회로의 회로도.

Claims (2)

  1. 여러개의 데이타로 되는 열벡터 입력신호와 소정수의 계수데이터로 되는 매트릭스를 백터곱하는 것에 의해서 여러개의 데이타로 되는 열벡터 출력신호를 발생하기 위한 디지탈 신호처리 프로세서로서, 상기 열벡터 입력신호의 여러개의 데이타를 직렬로 수신하는 입력수단, 상기 입력수단에 의해 수신된 데이타를 제1의 사이클로 저장하는 제1저장수단, 상기 매트릭스의 상기 소정수의 계수 데이타를 기억하는 계수메모리수단, 상기 제1의 사이클보다 짧은주기를 갖는 제2의 사이클로 상기 계수메모리 수단에서 상기 소정수의 계수데이타중 메트릭스의 행방향의 데이타를 리드하고, 상기 리드된 데이타를 저장하는 제2 저장수단, 상기 제1 저장수단의 출력데이터와 상기 제2저장수단의 출력데이타를 승산하는 승산수단, 상기 승산수단의 출력에 접속된 제3저장수단, 상기 제3저장수단의 출력에 그 제1입력이 접속된 가산수단, 상기 가산수단의 제2입력에그 출력이 접속된 제4저장수단 및 상기 가산수단의 출력에 그 입력이 접속되고, 상기 제4 저장수단의 입력에 그 출력이 접속된 어큐뮬레이터 수단을 포함하는 디지탈 신호처리 프로세서.
  2. 특허청구의 범위 제1항에 있어서, 상기 계수메모리 수단은 그 입력, 그 출력이 독립적으로 엑세스가 가능한 멀티포트 메모리 수단인 디지탈 신호처리 프로세서.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019890003321A 1988-03-18 1989-03-17 고속디지탈신호처리프로세서 Expired - Fee Related KR0130772B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP63-63313 1988-03-18
JP63063313A JP2690932B2 (ja) 1988-03-18 1988-03-18 ディジタル信号処理プロセッサおよびディシタル信号処理プロセッサシステム

Publications (2)

Publication Number Publication Date
KR890015157A true KR890015157A (ko) 1989-10-28
KR0130772B1 KR0130772B1 (ko) 1998-04-15

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ID=13225666

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KR1019890003321A Expired - Fee Related KR0130772B1 (ko) 1988-03-18 1989-03-17 고속디지탈신호처리프로세서

Country Status (3)

Country Link
US (1) US4945506A (ko)
JP (1) JP2690932B2 (ko)
KR (1) KR0130772B1 (ko)

Families Citing this family (25)

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US5267185A (en) * 1989-04-14 1993-11-30 Sharp Kabushiki Kaisha Apparatus for calculating matrices
US5208770A (en) * 1989-05-30 1993-05-04 Fujitsu Limited Accumulation circuit having a round-off function
US5077677A (en) * 1989-06-12 1991-12-31 Westinghouse Electric Corp. Probabilistic inference gate
FR2656710A1 (fr) * 1989-12-29 1991-07-05 Radiotechnique Compelec Microcontroleur pour l'execution rapide d'un grand nombre d'operations decomposable en sequence d'operations de meme nature.
US5128888A (en) * 1990-04-02 1992-07-07 Advanced Micro Devices, Inc. Arithmetic unit having multiple accumulators
JPH05197741A (ja) * 1991-06-06 1993-08-06 Lsi Logic Corp インターリーブド乗算器累算器
US5245562A (en) * 1991-09-17 1993-09-14 The Johns Hopkins University Accumulating arithmetic memory integrated circuit
US5206822A (en) * 1991-11-15 1993-04-27 Regents Of The University Of California Method and apparatus for optimized processing of sparse matrices
US5204830A (en) * 1992-02-13 1993-04-20 Industrial Technology Research Institute Fast pipelined matrix multiplier
US6965644B2 (en) * 1992-02-19 2005-11-15 8×8, Inc. Programmable architecture and methods for motion estimation
US5524259A (en) * 1992-04-28 1996-06-04 Kabushiki Kaisha Toshiba Processor system having an external arithmetic device for high speed execution of computation of data
JPH06175821A (ja) * 1992-12-10 1994-06-24 Fujitsu Ltd 演算装置
JP3693367B2 (ja) * 1994-07-28 2005-09-07 富士通株式会社 積和演算器
KR100186918B1 (ko) * 1994-10-21 1999-05-01 모리시다 요이치 신호처리장치
JPH08241301A (ja) * 1995-03-07 1996-09-17 Nec Corp 直交変換処理装置
JP2636789B2 (ja) * 1995-03-31 1997-07-30 日本電気株式会社 マイクロプロセッサ
FR2745647B3 (fr) * 1996-03-01 1998-05-29 Sgs Thomson Microelectronics Coprocesseur d'arithmetique modulaire permettant de realiser des operations non modulaires rapidement
JPH1055352A (ja) * 1996-08-08 1998-02-24 Fuji Xerox Co Ltd 浮動小数点数累積加算装置
US6377619B1 (en) * 1997-09-26 2002-04-23 Agere Systems Guardian Corp. Filter structure and method
JP3524747B2 (ja) 1998-01-30 2004-05-10 三洋電機株式会社 離散コサイン変換回路
JP3547972B2 (ja) * 1998-01-30 2004-07-28 三洋電機株式会社 離散コサイン変換回路
JP3547971B2 (ja) 1998-01-30 2004-07-28 三洋電機株式会社 離散コサイン変換回路及びその動作方法
US7035892B2 (en) * 1999-12-10 2006-04-25 Broadcom Corporation Apparatus and method for reducing precision of data
US6895421B1 (en) * 2000-10-06 2005-05-17 Intel Corporation Method and apparatus for effectively performing linear transformations
US10795678B2 (en) * 2018-04-21 2020-10-06 Microsoft Technology Licensing, Llc Matrix vector multiplier with a vector register file comprising a multi-port memory

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61140213A (ja) * 1984-12-12 1986-06-27 Nec Corp ２次元デイジタルフイルタ
GB8431925D0 (en) * 1984-12-18 1985-01-30 Secr Defence Digital data processor
AU582632B2 (en) * 1985-04-05 1989-04-06 Raytheon Company Method and apparatus for addressing a memory by array transformations
EP0202633B1 (en) * 1985-05-17 1991-01-23 Nec Corporation Processing circuit capable of raising throughput of accumulation
JPS61296462A (ja) * 1985-06-25 1986-12-27 Yokogawa Medical Syst Ltd 高速デ−タ処理装置
US4787057A (en) * 1986-06-04 1988-11-22 General Electric Company Finite element analysis method using multiprocessor for matrix manipulations with special handling of diagonal elements
US4760517A (en) * 1986-10-17 1988-07-26 Integrated Device Technology, Inc. Thirty-two bit, bit slice processor

Also Published As

Publication number Publication date
US4945506A (en) 1990-07-31
JPH01237765A (ja) 1989-09-22
JP2690932B2 (ja) 1997-12-17
KR0130772B1 (ko) 1998-04-15

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