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KR890001155A - 반도체 장치 및 반도체 장치의 내장 방법 - Google Patents

반도체 장치 및 반도체 장치의 내장 방법 Download PDF

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Publication number
KR890001155A
KR890001155A KR1019880007240A KR880007240A KR890001155A KR 890001155 A KR890001155 A KR 890001155A KR 1019880007240 A KR1019880007240 A KR 1019880007240A KR 880007240 A KR880007240 A KR 880007240A KR 890001155 A KR890001155 A KR 890001155A
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KR
South Korea
Prior art keywords
semiconductor device
wafer
substrate
main surface
slit
Prior art date
Application number
KR1019880007240A
Other languages
English (en)
Other versions
KR970007840B1 (ko
Inventor
간지 오오쯔가
시게오 굴되
가쯔유기 사도우
히사시 나까무라
신이찌 쇼우지
Original Assignee
미다 가쓰시게
가부시기가이샤 히다찌 세이사꾸쇼
오노 미노루
히다찌초 에루 에스 아이 엔지니어링 가부시기가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP62157649A external-priority patent/JPS644032A/ja
Priority claimed from JP62157647A external-priority patent/JP2549659B2/ja
Priority claimed from JP62223962A external-priority patent/JPS6467928A/ja
Priority claimed from JP62257121A external-priority patent/JPH01100912A/ja
Application filed by 미다 가쓰시게, 가부시기가이샤 히다찌 세이사꾸쇼, 오노 미노루, 히다찌초 에루 에스 아이 엔지니어링 가부시기가이샤 filed Critical 미다 가쓰시게
Publication of KR890001155A publication Critical patent/KR890001155A/ko
Application granted granted Critical
Publication of KR970007840B1 publication Critical patent/KR970007840B1/ko

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Abstract

내용 없음

Description

반도체 장치 및 반도체 장치의 내장 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도는 발명의 제 1 실시예를 도시한 설명도.
제 2 도는 제 1 의 발명의 제 1 실시예를 도시한 주요부 단면도.
제 3 도는 제 1 의 발명의 제 1 실시예를 도시한 내장 상태의 사시도.

Claims (19)

  1. 회로가 구성되어 있는 주 표면을 갖는 웨이퍼 규모의 기판, 상기 기판의 가장 자리에서 중심을 향해 형성된 슬릿(3)과, 슬릿을 따라서 기판 주표면 도는 슬릿 측면에 배치된 여러개의 전극(5)를 포함하는 웨이퍼 규모의 반도체 장치.
  2. 특허청구의 범위 제 1 항에 있어서, 상기 슬릿(3)의 웨이퍼(1) 중심측 끝부분은 원형상인 웨이퍼 규모의 반도체 장치.
  3. 회로가 구성되어 있는 주 표면을 갖는 웨이퍼 규모의 기판, 상기 기판의 가장자리에 중심을 향해서 형성된 슬릿(3), 슬릿(3)을 따라서 기판 주 표면 또는 스릿 측면에 배치된 여러개의 전극(5)와, 슬릿을 갖고 상기 기판을 내장하기 위한 패키지(7)을 포함하는 웨이퍼 규모의 반도체 장치.
  4. 특허 청구의 범위 제 3 항에 있어서, 상기 전극(5)는 땜납 범프(5')를 거쳐서 저늑 리드(5")를 부착해서 되는 웨이퍼 규모의 반도체 장치.
  5. 주 표면에 집적 회로(14)를 구성한 웨이퍼 사이즈의 반도체 소자(20), 상기 반도체 소자의 가장자리를 피우도록 형성된 단면이자형상을 한 보강 고무(12), 상기 반도체 소자의 오리엔테이션 플랫부(13A)에 마련된 전극(15)를 포함하는 웨이퍼 규모의 반도체 장치.
  6. 특허청구의 범위 제 5항에 있어서, 상기 보강 고무 (12)는 실리콘 수지인 웨이퍼 규모의 반도체 장치.
  7. 주 표면에 집적 회로(14)를 구성한 웨이퍼 규모의 반도체 소자(20),상기 반도체 소자의 가장 자리를 끼우도록 형성된 보강 고무(12)에 있어서, 상기반도체 소자(20)의 주 표면의집적 회로(14)에는 입출력 단자가 형성되고, 상기 보강 고무(12)는 도전성 보강 고무(12A)와 절연성 보강 고무 (12B)로 되어, 상기 도전성 보강 고무와 절연성 보강 고무는 고대로 배치되고, 도전성 보강 고무는 상기 입출력 단자에 대응하도록 접속되어서 되는 웨이퍼 규모의 반도체 장치.
  8. 특허청구의 범위 제 7항에 있어서, 상기 도전성 보강 고무(12A) 는 부타디엔 아크릴로니트릴 공중합 고무인 웨이퍼 규모의 반도체 장치.
  9. 특허 청구의 범위 제 7 항에 있어서, 상기 절연성 보강 고무(12B)는 실리콘 수지인 웨이퍼 규모의 반도체 장치.
  10. 특허청구의 범위 제 7 항에 있어서, 상기 도전성 보강 고무(12A)와 입출력 단자 사이의 접속은 알루미늄 배선(16)에 의한 접속인 웨이퍼 규모의 반도체 장치.
  11. 회로가 구성된 주 표면과 그것에 대향하는 이면을 갖는 웨이퍼규모의 반도체 소자(20), 상기 반도체 소자를 접착, 고정하기 위한 절연 기판(21),상기 반도체 소자를 상기절연기판 위에 부착하기 위한 접착제(27), 상기 반도체 소자와 상기 절연 기판을 전기적으로 접속하기 위한 와이어(23), 상기 반도체 소자와 상기 와이어를봉하기위한 봉함 용재822), 상기 반도체 소자를 둘러싸는 위치에 마련된 프레임(24), 상기 프레임에 접합되어 반도체 소자와 봉합 용재를 밀봉하기 위한 캡(25)를 포함하는 웨이퍼 규모의 반도체 장치.
  12. 특허청구의 범위 제 11항에 있어서, 상기 절연 기판(21)은 여러개의 관통 구멍(29)를 갖는 웨이퍼 규모의 반도체 장치.
  13. 특허청구의 범위 제12항에 있어서, 상기 관통 구멍(29)는 그 표면에 형성된 금속 막을 갖는 웨이퍼 규모의 반도체 장치.
  14. 특허청구의 범위 제12항에 있어서, 상기 절연 기판(21)은 유리 또는 케플러 또는 실리카 유리 섬유 강화 비페닐 트리아진 기판 또는 동일 에폭시 기판 또는 폴리이미드 기관으로 되는 웨이퍼 규모의 반도체 장치.
  15. 특허청구의 범위 제11항에 있어서, 상기 접착제(27)은 유연한 가요성을 갖는 물질인 웨이퍼 규모의 반도체 장치.
  16. 특허 청구의 범위 제15항에 있어서, 상기 유연한 가요성을 갖는 물질은 실리콘계 겔 또는 실리콘계 고무인 웨이퍼 규모의 반도체 장치.
  17. 특허청구의 범위 제11항에 있어서, 상기 봉합용제(22)는 실리콘계 겔인 웨이퍼 규모의 반도체 장치.
  18. (a) 그 표면에서 이면까지 관통한 홈부문(35B)를 갖는 반도체 웨이퍼를 준비하는 공정, (b) 배선이 형성된 제1의 주 표면과 그것에 대향하도록 형성된 제2의 주 표면을 갖고, 여러개의절연층 및 배선층 및 전극 패드가 형성되어 있는 반도체 소자를 준비하는 공정, (c) 상기 반도체 웨이퍼에 상기 반도체 소자를 매입하는공저, (d) 상기 반도체 웨이퍼에 내부 배선을 형성하는 공정과 상기 반도체 소자 위에 접속용 배선 (38A)를 형성하는 공정을 동시에 행하는 공정으로되는 웨이퍼 규모의 반도체 장치의 제조방법.
  19. 특허청구의 범위 제18항에 있어서, 상기 반도체 소자의 배선 (38A, 38B)는 알루미늄막에 의해 구성되어 있는 웨이퍼 규모의 반도체 장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019880007240A 1987-06-26 1988-06-16 반도체 장치 KR970007840B1 (ko)

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
JP62-157647 1987-06-26
JP62157649A JPS644032A (en) 1987-06-26 1987-06-26 Semiconductor wafer and mounting thereof
JP62157647A JP2549659B2 (ja) 1987-06-26 1987-06-26 半導体装置
JP62-157649 1987-06-26
JP62-57647 1987-06-26
JP62223962A JPS6467928A (en) 1987-09-09 1987-09-09 Manufacture of semiconductor device
JP62-223962 1987-09-09
JP62-257121 1987-10-14
JP62257121A JPH01100912A (ja) 1987-10-14 1987-10-14 半導体集積回路装置

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KR890001155A true KR890001155A (ko) 1989-03-18
KR970007840B1 KR970007840B1 (ko) 1997-05-17

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JPH05152509A (ja) * 1991-11-27 1993-06-18 Hitachi Ltd 電子回路システム装置
US5266833A (en) * 1992-03-30 1993-11-30 Capps David F Integrated circuit bus structure
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MY114888A (en) * 1994-08-22 2003-02-28 Ibm Method for forming a monolithic electronic module by stacking planar arrays of integrated circuit chips
JPH08316364A (ja) * 1995-05-16 1996-11-29 Toshiba Corp 半導体装置
US6175124B1 (en) 1998-06-30 2001-01-16 Lsi Logic Corporation Method and apparatus for a wafer level system
GB0705287D0 (en) * 2007-03-20 2007-04-25 Conductive Inkjet Tech Ltd Electrical connection of components
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JPS6012744A (ja) * 1983-07-01 1985-01-23 Hitachi Ltd 半導体装置
JPS60257546A (ja) * 1984-06-04 1985-12-19 Mitsubishi Electric Corp 半導体装置及びその製造方法
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107305906A (zh) * 2016-04-21 2017-10-31 三星显示有限公司 柔性显示装置
CN107305906B (zh) * 2016-04-21 2023-08-15 三星显示有限公司 柔性显示装置

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