KR20240119806A - Display panel and display device including the same - Google Patents

Abstract

A display panel and a display device including the same are disclosed. The display panel includes subpixels of a first color; a subpixel of a second color; and subpixels of a third color. Each of the first to third color subpixels includes a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node, and is driven to supply current to the light emitting device. device; and a second capacitor connected between a constant voltage node to which a constant voltage is applied and the third node.

Description

Display panel and display device including the same {DISPLAY PANEL AND DISPLAY DEVICE INCLUDING THE SAME}

The present invention relates to a display panel and a display device including the same.

Electroluminescence displays can be divided into inorganic light emitting displays and organic light emitting displays depending on the material of the light emitting layer. The active matrix type organic light emitting display device includes an organic light emitting diode (hereinafter referred to as “OLED”) that emits light on its own, has a fast response speed, and has high luminous efficiency, brightness, and viewing angle. There is an advantage. In organic light emitting display devices, OLEDs are formed in each pixel. Organic light emitting display devices not only have a fast response speed and excellent luminous efficiency, brightness, and viewing angle, but also have excellent contrast ratio and color gamut because they can express black gradations in complete black.

There may be differences in the electrical characteristics of driving elements between pixels due to process deviations and element characteristic deviations resulting from the display panel manufacturing process. The difference in electrical characteristics of these driving elements may become larger as the driving time of the pixels elapses. To compensate for differences in electrical characteristics of driving elements between pixels, an internal compensation circuit may be added to the pixel circuit. The internal compensation circuit can sense the threshold voltage of the driving element, store it in a capacitor, and compensate the gate voltage of the driving element by the threshold voltage of the driving element.

The internal compensation circuit can be divided into a source follower circuit and a diode connection circuit. The source follower circuit has the advantage of securing sufficient sensing time because the threshold voltage sensing time of the driving element and the addressing time (or data writing time) when pixel data is written to the pixel are separated in time. However, data voltage may be lost in the source follower circuit.

The present invention aims to solve the above-described needs and/or problems.

The present invention provides a display panel that can prevent loss of data voltage and a display device including the same.

The object of the present invention is not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

A display panel according to an embodiment of the present invention includes a subpixel of a first color; a subpixel of a second color; and subpixels of a third color. Each of the first to third color subpixels includes a driving element including a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node; a light emitting element including an anode electrode connected to a fourth node and driven by current from the driving element; a first capacitor connected between the second node and the third node; and a second capacitor connected between a constant voltage node to which a constant voltage is applied and the third node, or between the third node and the fourth node. The capacity of the second capacitor is different for each color of the subpixels.

Each of the first to third color subpixels includes a first electrode to which a pixel driving voltage is applied, a gate electrode to which a first gate signal is applied, and a first switch element connected to the first node; And it may further include a second switch element including a first electrode connected to the third node, a gate electrode to which a second gate signal is applied, and a second electrode connected to the fourth node. The first color subpixel includes a 2-1 capacitor. The subpixel of the second color includes a 2-2 capacitor. The third color subpixel includes second-third capacitors. The anode electrode of the light emitting device is connected to the fourth node. The first color may be red, the second color may be green, and the third color may be blue. The capacity of the 2-3 capacitor may be larger than the capacity of each of the 2-1 and 2-2 capacitors, and the capacity of the 2-2 capacitor may be larger than the capacity of the 2-1 capacitor.

The display panel includes a pattern of a first metal layer disposed on a first insulating layer and connected to the first to third color subpixels; a second insulating layer covering the pattern of the first metal layer and the first insulating layer; Patterns of a second metal layer disposed on the second insulating layer and in each of the first to third color subpixels and separated between the subpixels; It may further include a third insulating layer covering the patterns of the second metal layer and the second insulating layer. The patterns of the second metal layer include a 2-1 capacitor electrode disposed in the first color subpixel; a 2-2 capacitor electrode disposed in the second color subpixel; and a 2-3 capacitor electrode disposed in the third color subpixel. The 2-3 capacitor electrode may be larger than each of the 2-1 and 2-2 capacitor electrodes, and the 2-2 capacitor electrode may be larger than the 2-1 capacitor electrode.

The constant voltage applied to the 2-1st to 2-3rd capacitors may be the same as or different from the pixel driving voltage.

Each of the first to third color subpixels has a first electrode connected to a data line to which a data voltage of pixel data is applied, a gate electrode to which a third gate signal is applied, and a second electrode connected to the second node. A third switch element including; a fourth switch element including a first electrode to which an initialization voltage is applied, a gate electrode to which a fourth gate signal is applied, and a second electrode connected to the second node; a fifth switch element including a first electrode to which a reference voltage is applied, a gate electrode to which a fifth gate signal is applied, and a second electrode connected to the fourth node; And it may include a first capacitor connected between the second node and the third node. Capacitances of the first capacitors in the first to third color subpixels may be the same.

The pixel circuits disposed in each of the first to third color subpixels may be driven in the following order: an initialization period, a sensing period, a data writing period, an anode reset period, and an emission period. The voltage of the first gate signal is the gate-on voltage during the initialization period, the sensing period, and the light emission period, the gate-off voltage during the anode reset period, and the gate-on voltage or the gate-off voltage during the data writing period. It can be. The voltage of the second gate signal may be the gate-on voltage during the initialization period, the anode reset period, and the light emission period, and may be the gate-off voltage during the sensing period and the data writing period. The voltage of the third gate signal may be the gate-on voltage during the data writing period and the gate-off voltage during the initialization period, the sensing period, the anode reset period, and the light emission period. The voltage of the fourth gate signal may be the gate-on voltage during the initialization period and the sensing period, and may be the gate-off voltage during the data writing period, the anode reset period, and the light emission period. The voltage of the fifth gate signal may be the gate-on voltage during the initialization period, the sensing period, the data writing period, and the anode reset period, and may be the gate-off voltage during the light emission period. Each of the first to fifth switch elements may be turned on in response to the gate-on voltage and may be turned off in response to the gate-off voltage.

Each of the first to third color subpixels may further include a first electrode to which a pixel driving voltage is applied, a gate electrode to which a first gate signal is applied, and a first switch element connected to the first node. there is. The first color subpixel includes a 2-1 capacitor. The subpixel of the second color includes a 2-2 capacitor. The third color subpixel includes second-third capacitors. The anode electrode of the light emitting device is connected to the third node. The first color may be red, the second color may be green, and the third color may be blue. The capacity of the 2-1 capacitor may be larger than the capacity of each of the 2-2 and 2-3 capacitors, and the capacity of the 2-2 capacitor may be larger than the capacity of the 2-3 capacitor.

The capacitor capacity of the light emitting device may be large in that order: the third color subpixel, the second color subpixel, and the first color subpixel. The constant voltage applied to the 2-1st to 2-3rd capacitors may be the same as or different from the pixel driving voltage.

Each of the first to third subpixels includes a first electrode connected to a data line to which a data voltage of pixel data is applied, a gate electrode to which a second gate signal is applied, and a second electrode connected to the second node. 2 switch elements; a third switch element including a first electrode to which an initialization voltage is applied, a gate electrode to which a third gate signal is applied, and a second electrode connected to the second node; a fourth switch element including a first electrode to which a reference voltage is applied, a gate electrode to which a fourth gate signal is applied, and a second electrode connected to the third node; And it may include a first capacitor connected between the second node and the third node. Capacitances of the first capacitors in the first to third subpixels may be the same.

The first color subpixel includes a 2-1 capacitor. The subpixel of the second color includes a 2-2 capacitor. The third color subpixel includes second-third capacitors. A pixel driving voltage is applied to the first node. The anode electrode of the light emitting device is connected to the third node.

The first color may be red, the second color may be green, and the third color may be blue. The capacity of the 2-1 capacitor may be larger than the capacity of each of the 2-2 and 2-3 capacitors, and the capacity of the 2-2 capacitor may be larger than the capacity of the 2-3 capacitor.

The capacitor capacity of the light emitting device may be large in that order: the third color subpixel, the second color subpixel, and the first color subpixel. The constant voltage applied to the 2-1st to 2-3rd capacitors may be the same as or different from the pixel driving voltage.

Each of the first to third subpixels includes a first electrode connected to a data line to which a data voltage of pixel data is applied, a gate electrode to which a first gate signal is applied, and a second electrode connected to the second node. 1 switch element; a second switch element including a first electrode to which an initialization voltage is applied, a gate electrode to which a second gate signal is applied, and a second electrode connected to the second node; a third switch element including a first electrode to which a reference voltage is applied, a gate electrode to which a third gate signal is applied, and a second electrode connected to the third node; And it may include a first capacitor connected between the second node and the third node. Capacitances of the first capacitors in the first to third subpixels may be the same.

A display device according to an embodiment of the present invention includes the display panel.

The present invention can implement a pixel circuit capable of high brightness, high efficiency, and low power operation.

The present invention optimizes the capacity of the second capacitor for each color of subpixels to reduce data voltage loss in a pixel circuit including a source follower internal compensation circuit, without increasing the data voltage and expanding the data voltage range. Pixels can be driven at high brightness.

The display device of the present invention overcomes the driving limitations of a pixel circuit including a source-follower type internal compensation circuit and can implement a high-brightness image with a relatively low data voltage.

The present invention reduces the size and cost of the drive IC in which the data driver is integrated, reduces the power consumption of the drive IC, enables low-power operation of the display device, and reduces the heat generation of the drive IC.

The effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims.

1 is a block diagram showing a display device according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view showing the cross-sectional structure of the display panel shown in FIG. 1.
FIG. 3A is a diagram showing an example of a second capacitor connected to subpixels.
FIG. 3B is a diagram showing another example of a second capacitor connected to subpixels.
Figure 4 is a plan view showing the second capacitor for each color of subpixels.
FIG. 5 is a cross-sectional view showing the cross-sectional structure of the second capacitor cut along the line “'” in FIG. 4.
Figure 6 is a circuit diagram showing a pixel circuit according to an embodiment of the present invention.
FIG. 7 is a waveform diagram showing gate signals applied to the pixel circuit shown in FIG. 6 and voltages of main nodes.
Figure 8 is a circuit diagram showing a pixel circuit according to another embodiment of the present invention.
FIG. 9 is a waveform diagram showing gate signals applied to the pixel circuit shown in FIG. 8 and voltages of main nodes.
Figure 10 is a circuit diagram showing a pixel circuit according to another embodiment of the present invention.
Figure 11 is a circuit diagram showing a pixel circuit according to another embodiment of the present invention.
FIG. 12 is a plan view showing second capacitors for each color of subpixels to which the pixel circuit shown in FIGS. 10 and 11 is applied.
FIG. 13 is a cross-sectional view showing the cross-sectional structure of the second capacitor taken along the line “B-B'” in FIG. 12.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms. The embodiments only serve to ensure that the disclosure of the present invention is complete, and those skilled in the art will be able to understand the present invention. It is provided to completely inform the scope of the invention, and the invention is only defined by the scope of the claims.

The shape, size, ratio, angle, number, etc. shown in the drawings for explaining embodiments of the present invention are illustrative, and the present invention is not limited to the matters shown in the drawings. Like reference numerals refer to substantially like elements throughout the specification. Additionally, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

When “provides,” “includes,” “has,” “consists of,” etc. mentioned in this specification are used, other parts may be added unless ‘only’ is used. If a component is expressed in the singular, it may be interpreted as plural unless specifically stated.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

Position between two components, such as 'on', 'on top', 'on the bottom', 'next to', '~ connect, couple', crossing, intersecting, etc. When relationships and interconnections are described, one or more other components may be interposed between the components, unless reference is made to 'immediately' or 'directly'.

If a temporal relationship is described as 'after', 'successfully after', 'after', 'before', etc., it may not be continuous on the time axis unless 'immediately' or 'directly' is used. .

First, second, etc. may be used to distinguish components, but the function or structure of these components is not limited by the ordinal number or component name in front of the component.

The following embodiments can be partially or fully combined or combined with each other, and various technological interconnections and drives are possible. Each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

In the display device of the present invention, the pixel circuit and the gate driving circuit may include a plurality of transistors. The transistor may be an Oxide TFT (Thin Film Transistor) containing an oxide semiconductor or a LTPS TFT containing Low Temperature Poly Silicon (LTPS). Hereinafter, the transistors constituting the pixel circuit and the gate driving circuit will be described focusing on an example implemented as an n-channel oxide TFT, but the present invention is not limited thereto.

A transistor is a three-electrode device including a gate, source, and drain. The source is an electrode that supplies carriers to the transistor. Within the transistor, carriers begin to flow from the source. The drain is the electrode through which carriers exit the transistor. In a transistor, the flow of carriers flows from the source to the drain. In the case of an n-channel transistor, because the carriers are electrons, the source voltage has a lower voltage than the drain voltage so that electrons can flow from the source to the drain. In an n-channel transistor, the direction of current flows from the drain to the source. In the case of a p-channel transistor, since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-channel transistor, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain may change depending on the applied voltage. Therefore, the invention is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as first and second electrodes.

The gate signal may include a pulse that swings between the gate on voltage and the gate off voltage. The gate-on voltage is set to a voltage higher than the threshold voltage of the transistor. The gate-off voltage is set to a voltage lower than the threshold voltage of the transistor.

The transistor turns on in response to the gate on voltage, while it turns off in response to the gate off voltage. In the case of an n-channel transistor, the gate-on voltage may be the gate high voltage and the gate-off voltage may be the gate low voltage.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings.

1 is a block diagram showing a display device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view showing the cross-sectional structure of the display panel shown in FIG. 1.

1 and 2, a display device according to an embodiment of the present invention includes a display panel 100, a display panel driving circuit for writing pixel data to pixels of the display panel 100, and pixels. and a power supply unit 140 that generates power necessary to drive the display panel driving circuit.

The display panel 100 may be a panel with a rectangular structure having a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. The display area AA of the display panel 100 includes a pixel array that displays an input image. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 that intersect the data lines 102, and pixels arranged in a matrix form. The display panel 100 may further include power lines commonly connected to pixels. The power lines are connected to the constant voltage lines of the pixel circuits to supply the pixels 101 with a constant voltage necessary to drive the pixels 101.

Each of the pixels 101 may be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel to implement color. Each of the pixels may further include a white subpixel. Each of the subpixels may include a pixel circuit implemented as a source follower internal compensation circuit as shown in FIGS. 6 to 11 . Each pixel circuit is connected to a data line, gate line, and power line. The pixel circuit may be implemented as a circuit including the source follower type internal compensation circuit shown in FIGS. 6 to 11, but is not limited thereto.

Pixels can be arranged as real color pixels and pentile pixels. Pentile pixels can implement higher resolution than real color pixels by driving two sub-pixels of different colors into one pixel (101) using a preset pixel rendering algorithm. The pixel rendering algorithm can compensate for insufficient color expression in each pixel with the color of light emitted from adjacent pixels.

The pixel array includes a plurality of pixel lines (L1 to Ln). Each of the pixel lines L1 to Ln includes one line of pixels arranged along the line direction (X-axis direction) in the pixel array of the display panel 100. Pixels placed in one pixel line share gate lines 103. Subpixels arranged in the column direction (Y) along the data line direction share the same data line 102. 1 horizontal period is the time divided by 1 frame period by the total number of pixel lines (L1 to Ln).

The display panel 100 may be implemented as a non-transmissive display panel or a transmissive display panel. A transmissive display panel can be applied to a transparent display device where an image is displayed on the screen and the actual object in the background is visible. The display panel 100 may be manufactured as a flexible display panel.

The cross-sectional structure of the display panel 100 may include a circuit layer (CIR), a light emitting element layer (EMIL), and an encapsulation layer (ENC) stacked on a substrate (SUBS) as shown in FIG. 2. there is.

The circuit layer (CIR) may include a TFT array including a pixel circuit connected to wires such as data lines, gate lines, and power lines, a demultiplexer array 112, and a gate driver 120. The circuit layer (CIR) includes a plurality of metal layers insulated with insulating layers interposed therebetween, and a semiconductor material layer. All transistors formed in the circuit layer (CIR) may be implemented as n-channel oxide TFTs, but are not limited to this.

The light emitting device layer (EMIL) may include a light emitting device (EL) driven by a pixel circuit. The light emitting device EL may include a red subpixel light emitting device, a green subpixel light emitting device, and a blue subpixel light emitting device. The light emitting device layer (EMIL) may further include a white subpixel light emitting device. The light emitting element layer (EMIL) in each subpixel may have a structure in which a light emitting element and a color filter are stacked. The light emitting elements EL of the light emitting element layer EMIL may be covered with multiple protective layers including an organic layer and an inorganic layer.

The encapsulation layer (ENC) covers the light emitting device layer (EMIL) to seal the circuit layer (CIR) and the light emitting device layer (EMIL). The encapsulation layer (ENC) may have a multi-insulating film structure in which organic and inorganic films are alternately stacked. The inorganic membrane blocks the penetration of moisture or oxygen. The organic film flattens the surface of the inorganic film. When an organic film and an inorganic film are stacked in multiple layers, the movement path of moisture or oxygen is longer compared to a single layer, so the penetration of moisture and oxygen that affects the light emitting device layer (EMIL) can be effectively blocked.

A touch sensor layer (omitted from the drawing) may be formed on the encapsulation layer (ENC), and a polarizing plate or color filter layer may be disposed thereon. The touch sensor layer may include capacitive touch sensors that sense touch input based on changes in capacitance before and after touch input. The touch sensor layer may include metal wiring patterns and insulating films that form the capacitance of the touch sensors. The insulating films can insulate the intersections of metal wiring patterns and flatten the surface of the touch sensor layer. The polarizer can improve visibility and contrast ratio by converting the polarization of external light reflected by the metal of the touch sensor layer and circuit layer. The polarizer may be implemented as a polarizer or circular polarizer in which a linear polarizer and a phase retardation film are bonded. A cover glass may be adhered onto the polarizer. The color filter layer may include red, green, and blue color filters. The color filter layer may further include a black matrix pattern. The color filter layer absorbs part of the wavelength of light reflected from the circuit layer and the touch sensor layer, taking the role of a polarizer and increasing the color purity of the image reproduced in the pixel array.

The power supply unit 140 generates direct current (DC) voltage (or constant voltage) required to drive the pixel array of the display panel 100 and the display panel driving circuit. The DC-DC converter may include a charge pump, regulator, buck converter, boost converter, etc. The power unit 140 adjusts the level of the direct current input voltage applied from the host system 200 to the gamma reference voltage (VGMA) and the gate-on voltage (VGH). Constant voltages such as gate-off voltage (VGL), pixel driving voltage (EVDD), pixel base voltage (EVSS), initialization voltage (Vinit), and reference voltage (Vref) can be generated. The gamma reference voltage (VGMA) is supplied to the data driver 110. The gate-on voltage (VGH) and gate-off voltage (VGL) are supplied to the level shifter 150 and the gate driver 120.

Constant voltages such as the pixel driving voltage (EVDD), pixel base voltage (EVSS), initialization voltage (Vinit), and reference voltage (Vref) are supplied to the pixels 101 through power lines commonly connected to the pixels 101. .

The power supply unit 140 may output a constant voltage (Vdc) applied to the second capacitor (Ca) shown in FIGS. 3A and 3B. The constant voltage (Vdc) may be a separate constant voltage, or may be replaced with a voltage such as another constant voltage applied to the pixel circuit, for example, the pixel driving voltage (EVDD).

The display panel driving circuit writes pixel data of the input image to the pixels of the display panel 100 under the control of a timing controller 130.

The display panel driving circuit includes a data driver 110 and a gate driver 120. The display panel driving circuit may further include a demultiplexer array 112 disposed between the data driver 110 and the data lines 102.

The demultiplexer array 112 sequentially supplies data voltages output from channels of the data driver 110 to the data lines 102 using a plurality of de-multiplexers (DEMUX). The demultiplexer may include a plurality of switch elements disposed on the display panel 100. If the demultiplexer is disposed between the output terminals of the data driver 110 and the data lines 102, the number of channels of the data driver 110 may be reduced. The demultiplexer array 112 may be omitted.

The display panel driving circuit may further include a touch sensor driving unit for driving the touch sensors. The touch sensor driver is omitted in FIG. 1. The data driver 110 and the touch sensor driver may be integrated into one drive IC (Integrated Circuit). In a mobile device or wearable device, the timing controller 130, power supply unit 140, data driver 110, etc. may be integrated into one drive IC.

The display panel driving circuit may operate in a low speed driving mode under the control of the timing controller 130. In the low-speed driving mode, the power consumption of the display panel 100 and the display panel driving circuit is reduced, so that the display device can be driven at low power. The low-speed driving mode can be set to analyze the input image and reduce power consumption of the display device when the input image does not change by a preset number of frames. The low-speed driving mode can reduce the power consumption of the display panel driving circuit and the display panel 100 by lowering the frame frequency at which pixel data is written to the pixels, that is, the refresh rate, when a still image is input for more than a certain period of time. there is. The low-speed drive mode is not limited to when a still image is input. For example, when the display device operates in standby mode or when a user command or input image is not input to the display panel driving circuit for more than a predetermined period of time, the display panel driving circuit may operate in a low-speed driving mode.

The data driver 110 receives pixel data of an input image received as a digital signal from the timing controller 130 and outputs a data voltage. The data driver 110 uses a digital to analog converter (DAC) to convert pixel data of the input image into a gamma compensation voltage every frame period in normal driving mode and outputs a data voltage (VDATA). In low-speed driving mode, the data driver 110 converts the pixel data of the input image into a gamma compensation voltage using the DAC only in the refresh frame, outputs a data voltage (VDATA), and drives in the hold frame. stops and does not output data voltage. In the low-speed drive mode, the pixels 101 charge the pixel data voltage in a refresh frame and maintain the previous data voltage in a hold frame.

The gamma reference voltage (VGMA) is divided into a gamma compensation voltage for each gray level through a voltage divider circuit. The gamma compensation voltage for each gray level is provided to the DAC of the data driver 110. The data voltage VDATA is output from each channel of the data driver 110 through an output buffer.

The gate driver 120 may be implemented as a gate in panel (GIP) circuit formed in the circuit layer (CIR) on the display panel 100 along with the TFT array and wires of the pixel array. The gate driver 120 may be placed on the bezel area (BZ), which is a non-display area of the display panel 100, or may be dispersed within the pixel array where the input image is reproduced.

The gate driver 120 is disposed on one or both non-display areas (BZ) of the display panel 100 with the display area of the display panel in between, and feeds the gate line by single feeding or double feeding. Gate pulses can be supplied to fields 103. The gate driver 120 sequentially outputs pulses of gate signals to gate lines under the control of the timing controller 130. The gate driver 120 can sequentially supply the signals to the gate lines 103 by shifting the gate signals using one or more shift registers.

The timing controller 130 may receive digital video data (DATA) of an input image and a timing signal synchronized therewith from the host system 200. The timing signal may include a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a clock (CLK), and a data enable signal (DE). Since the vertical period and horizontal period can be known by counting the data enable signal (DE), the vertical synchronization signal (Vsync) and horizontal synchronization signal (Hsync) can be omitted. The data enable signal (DE) has a period of 1 horizontal period (1H).

The host system 200 may be any one of a television (TV) system, a tablet computer, a laptop computer, a navigation system, a personal computer (PC), a home theater system, a mobile device, a wearable device, or a vehicle system. The host system 200 may scale an image signal from a video source to match the resolution of the display panel 100 and transmit it to the timing controller 130 along with a timing signal.

The timing controller 130 multiplies the input frame frequency by i and controls the operation timing of the display panel driving circuit with a frame frequency of input frame frequency x i (i is a natural number) Hz. The input frame frequency is 60Hz in the NTSC (National Television Standards Committee) method and 50Hz in the PAL (Phase-Alternating Line) method.

The host system 200 or the timing controller 130 may vary the refresh rate or frame frequency according to the motion or content characteristics of the input image, or may vary the refresh rate or frame frequency according to the content of the input image.

The timing controller 130 lowers the refresh frame frequency at which pixel data is written to pixels in the low-speed drive mode compared to the normal drive mode. For example, in normal driving mode, the refresh frame frequency at which pixel data is written to pixels may be any one of 60Hz, 120Hz, 144Hz, and 240Hz, and in low-speed driving mode, the refresh frame frequency is 60Hz or higher. It may be a lower frequency than that of the drive mode. The timing controller 130 may lower the driving frequency of the display panel driving circuit and the pixels by setting a number of hold frames after the refresh frame to lower the refresh rate of the pixels in the low-speed driving mode.

The timing controller 130 provides a data timing control signal for controlling the operation timing of the data driver 110 based on the timing signal received from the host system 200, and a MUX control for controlling the operation timing of the demultiplexer array 112. A gate timing control signal for controlling the operation timing of the gate driver 120 is generated. The timing controller 130 controls the operation timing of the display panel driving circuit and synchronizes the data driver 110, the demultiplexer array 112, the touch sensor driver, and the gate driver 120.

The MUX control signal and the gate timing control signal output from the timing controller 130 may be input to the demultiplexer array 112 and the gate driver 120 through the level shifter 150. The level shifter 150 may receive a gate timing control signal and generate a start pulse and shift clock. The start pulse and shift clock output from the level shifter 150 swing between the gate-on voltage (VGH) and the gate-off voltage (VGL) and are input to the shift register of the gate driver 120 through the clock lines (CL). You can.

Each of the pixels 101 includes at least a subpixel of a first color, a subpixel of a second color, and a subpixel of a third color. Each of the first to third subpixels includes a driving element that supplies current to the light emitting element, including a first electrode connected to the first node, a gate electrode connected to the second node, and a second electrode connected to the third node. do. Additionally, each of the first to third subpixels includes a second capacitor connected between a constant voltage line to which a constant voltage is applied and the third node. The capacity of the second capacitor is set differently for each color of subpixels. These features will be described in detail in the following examples.

3A and 3B are diagrams showing examples of second capacitors connected to subpixels.

Referring to FIGS. 3A and 3B, the subpixels (R, G, B) have data lines (DL1, DL2, DL3) to which data voltages (Vdata(R), Vdata(G), and Vdata(B)) are applied. And, it is connected to one or more gate lines (GL) to which the gate signal (GATE) is applied.

Each of the subpixels R, G, and B may include first and second capacitors. The first capacitor is omitted in FIGS. 3A and 3B. The second capacitor includes a 2-1 capacitor (Ca1), a 2-2 capacitor (Ca2), and a 2-3 capacitor (Ca3).

The red subpixel (R) includes the 2-1 capacitor (Ca1). The green subpixel (G) includes the 2-2 capacitor (Ca2). The blue subpixel (B) includes the second-third capacitor (Ca3).

The second capacitors (Ca1, Ca2, Ca3) shown in FIG. 3A are connected to the third node between the driving element (DT) and the light emitting element (EL) and the constant voltage (Vdc) as shown in FIGS. 6 and 10-11. It can be connected between the applied constant voltage lines, and when the data voltage of the pixel data is applied to the first capacitor of the pixel circuit and the gate electrode of the driving element, the transfer rate of the data voltage is increased to reduce the loss of the data voltage.

The second capacitors (Ca1, Ca2, Ca3) shown in FIG. 3B are connected to the third node between the driving element (DT) and the second switch element (T02) as shown in FIG. 8. It may be connected between the fourth node between and the light emitting element (EL), and when the second switch element (T02) is turned on during the boosting period, the third node and the fourth node become the same node and the second capacitor (Ca) The boosting speed becomes faster due to the invisible effect.

Within the limited size of the pixel 101, the second capacitors Ca1, Ca2, and Ca3 formed in each of the subpixels (R, G, and B) may be designed to have the same capacity. In this case, loss of data voltage may occur in some subpixels, for example, the blue subpixel B, because the capacity of the 2-3 capacitor Ca3 is not sufficient.

The current through which the light emitting device can emit light in the subpixels (R, G, B) may vary for each color. For example, the required current to drive the subpixels normally may be larger in the following order: red subpixel (R), green subpixel (G), and blue subpixel (B). For example, the required current of the red subpixel (R), green subpixel (G), and blue subpixel (B) at a color temperature of 6500K is 60~60% when these subpixels emit light at 1600nit. 70[nA], the green subpixel (G) can be 70~80[nA], and the blue subpixel (B) can be 150~160[nA].

When the second capacitors Ca1, Ca2, and Ca3 have the same capacity, the amount of data voltage loss in the pixels is large, so the voltage level of the data voltage output from the data driver 110 must be higher, and the minimum voltage of the data voltage must be higher. The voltage range between and maximum voltage must be increased. This not only increases the size and cost of the drive IC in which the data driver 110 is integrated, but also increases the power consumption and heat generation of the drive IC.

The present invention, as shown in FIGS. 6 and 8, in the case of a pixel circuit including a switch element (T02) between the driving element (DT) and the light emitting element (EL) that is turned on/off according to the light emission control signal (EM2), In response to different required currents in the subpixels (R, G, and B), the capacities of the second capacitors (Ca1, Ca2, and Ca3) may be set differently for each color of the subpixels. For example, the capacity of the 2-3 capacitor (Ca3) of the blue subpixel is larger than the capacity of the red and green 2-1 and 2-2 capacitors (Ca1, Ca2), and the 2-2 capacitor (Ca2) ) is larger than the capacity of the 2-1 capacitor (Ca1). In other words, the second capacitors Ca1, Ca2, and Ca3 have large capacities in that order: the red subpixel (R), the green subpixel (G), and the blue subpixel (B). For example, the capacities of the second capacitors Ca1, Ca2, and Ca3 may be designed to be Ca1=138[fF], Ca2=160[fF], and Ca3=225[fF], but are not limited thereto.

In another embodiment, the present invention provides, in the case of a pixel circuit without a switch element between the driving element (DT) and the light emitting element (EL) as shown in FIGS. 10 and 11, subpixels (R, G, B) ) and the capacitance of the light emitting element EL, the capacitances of the capacitors Ca1, Ca2, and Ca3 can be set differently for each color of the subpixels. In this case, it is desirable to design the capacities of the second capacitors Ca1, Ca2, and Ca3 to be large in the order of the blue subpixel (B), green subpixel (G), and red subpixel (R).

Figure 4 is a plan view showing the second capacitor for each color of subpixels. FIG. 5 is a cross-sectional view showing the cross-sectional structure of the second capacitor taken along the line “A-A'” in FIG. 4.

Referring to FIGS. 4 and 5 , the display panel 100 may include second capacitors Ca1, Ca2, and Ca3. The second capacitors Ca1, Ca2, and Ca3 may be disposed in the circuit layer CIR.

The display panel 100 includes a first insulating layer (INS1), a pattern (Mb) of the first metal layer disposed on the first insulating layer (INS1), a pattern (Mb) of the first metal layer, and a first insulating layer (INS1). a second insulating layer (INS2) covering the second insulating layer, patterns (Ma1, Ma2, Ma3) of the second metal layer disposed on the second insulating layer, and patterns (Ma1, Ma2, Ma3) of the second metal layer and the second insulating layer. It includes a third insulating layer (INS3) covering (INS2).

The pattern Mb of the first metal layer is connected to the subpixels R, G, and B without interruption, and the common capacitors Ca1, Ca2, and Ca3 are shared between the subpixels R, G, and B. It is an electrode (or lower electrode). A constant voltage (Vdc) or a pixel driving voltage (EVDD) is applied to the pattern (Mb) of the first metal layer. Accordingly, in the pixel circuit shown in FIGS. 6, 8, 10, and 11, the pattern (Mb) of the first metal layer includes a constant voltage line to which the constant voltage (Vdc) is applied, or a constant voltage line to which the pixel driving voltage (EVDD) is applied. .

The patterns (Ma1, Ma2, Ma3) of the second metal layer are formed as independent patterns or island patterns separated between neighboring subpixels (R, G, B). The patterns (Ma1, Ma2, Ma3) of the second metal layer include a 2-1 capacitor electrode (or upper electrode) (Ma1) disposed in the red subpixel (R), and a 2-2 disposed in the green subpixel (G). It is divided into a capacitor electrode (Ma2) and a second-third capacitor electrode (Ma3) disposed in the blue subpixel (B).

The 2-1 capacitor electrode Ma1 overlaps the pattern Mb of the first metal layer within the red subpixel R with the second insulating layer INS2 in between and faces the pattern Mb of the first metal layer. do. The 2-2 capacitor electrode Ma2 overlaps the pattern Mb of the first metal layer within the green subpixel G with the second insulating layer INS2 in between and faces the pattern Mb of the first metal layer. do. The 2-3 capacitor electrode Ma3 overlaps the pattern Mb of the first metal layer within the blue subpixel B with the second insulating layer INS2 in between and faces the pattern Mb of the first metal layer. do.

In the pixel circuit shown in FIGS. 6, 8, 10, and 11, the 2-1 capacitor electrode Ma1 includes the third node (DTS) of the red subpixel (R). The 2-2 capacitor electrode Ma2 includes the third node DTS of the green subpixel G. The 2-3rd capacitor electrode Ma3 includes the third node (DTS) of the blue subpixel (B).

In order to differentially apply the second capacitor capacity to the subpixels (R, G, and B) to which the pixel circuit shown in FIGS. 6 and 8 is applied, the red subpixel (R), green subpixel (G), and blue subpixel (B) The sizes of the capacitor electrodes (Ma1, Ma2, and Ma3) may increase in that order. In other words, the 2-3 capacitor electrode Ma3 is larger than the size of each of the 2-1 and 2-2 capacitor electrodes Ma1 and Ma2, and the 2-2 capacitor electrode Ma2 is the 2- It may be larger than 1 capacitor electrode (Ma1).

In the case of the pixel circuit shown in FIGS. 6 and 8, the third node (DTS) coupled with the second node (DTG) across the first capacitor (Cst) is floating, so the pixel When the data voltage (Vdata) of data is applied to the second node (DTG), the voltage of the third node (DTS) may change due to the influence of the data voltage (Vdata), and due to the influence of this coupling, the data voltage ( Loss of Vdata may occur. The second capacitors Ca1, Ca2, and Ca3 reduce the loss of the data voltage Vdata. The present invention differentially designs the capacities of the second capacitors (Ca1, Ca2, and Ca3) based on the current required for each color in the subpixels, without increasing the voltage level of the data voltage at high brightness. , B) can increase the luminance. As a result, the present invention reduces the size and cost of the drive IC in which the data driver 110 is integrated, reduces the power consumption of the drive IC, enables low-power operation of the display device, and reduces heat generation of the drive IC.

Figure 6 is a circuit diagram showing a pixel circuit according to an embodiment of the present invention. FIG. 7 is a waveform diagram showing the gate signal applied to the pixel circuit shown in FIG. 6 and the voltages of main nodes.

6 and 7, the pixel circuit includes a light-emitting element (EL), a driving element (DT) that drives the light-emitting element (EL), a plurality of switch elements (T01 to T05), a first capacitor (Cst), and a second capacitor (Ca). The driving element (DT) and switch elements (T01 to T05) can be implemented as n-channel oxide TFT.

The pixel circuit is connected to a data line (DL) to which the data voltage (Vdata) of pixel data is applied, and to gate lines (GL1 to GL5) to which gate signals (EM1, EM2, INIT, SCAN, and SENSE) are applied. The pixel circuit includes a first constant voltage line (PL1) to which the pixel driving voltage (EVDD) is applied, a second constant voltage line (PL2) to which the pixel base voltage (EVSS) is applied, and a third constant voltage line to which the initialization voltage (Vinit) is applied ( It is connected to power lines to which a direct current voltage (or constant voltage) is applied, such as PL3), a fourth constant voltage line (PL4) to which a reference voltage (Vref) is applied, and a fifth constant voltage line (PL5) to which a constant voltage (Vdc) is applied. Power lines to which constant voltage lines are connected on the display panel 100 may be commonly connected to all pixels. Constant voltage (Vdc) can be replaced with pixel driving voltage (EVDD). In this case, since the second capacitor Ca is connected to the first constant voltage line PL1 to which the pixel driving voltage EVDD is applied, the fifth constant voltage line PL5 may be omitted.

The voltage level of each of the constant voltages (EVDD, EVSS, Vinit, and Vref) applied to the pixel circuit may be set in consideration of the voltage margin for operation in the saturation region of the driving element DT. The voltage levels of constant voltages (EVDD, EVSS, Vinit, Vref) can be set to the condition EVDD > Vref > Vinit > EVSS. The constant voltage Vdc applied to the second capacitor Ca may be set to a voltage level higher than the reference voltage Vref.

The gate signals (EM1, EM2, INIT, SCAN, SENSE) include pulses that swing between the gate-on voltage (VGH) and the gate-off voltage (VGL). The gate-on voltage (VGH) may be set to a voltage level higher than the pixel driving voltage (EVDD), and the gate-off voltage (VGL) may be set to a voltage level lower than the pixel base voltage.

The gate signals (INIT, SENSE, SCAN, EM1, EM2) include a first emission control signal (hereinafter referred to as “signal”) (EM1), a second EM signal (EM2), a first scan signal (SCAN), It includes a second scan signal (INIT) and a third scan signal (SENSE). The first EM signal EM1 is the first gate signal, the second EM signal EM2 is the second gate signal, the first scan signal SCAN is the third gate signal, and the second scan signal INIT is the fourth gate signal. signal and the third scan signal (SENSE) can each be interpreted as a fifth gate signal.

The pixel circuit disposed in each subpixel may be driven in the following order: an initialization period (INI), a sensing period (SEN), a data writing period (WR), an anode reset period (AR), and an emission period (EMIS). The initialization period (INI), sensing period (SEN), data writing period (WR), anode reset period (AR), and emission period (EMIS) are based on the waveforms of the gate signals (EM1, EM2, INIT, SCAN, SENSE). It can be defined by A boosting period (BOOST) in which the voltage of the second and third nodes (DTG and DTS) increases may be included at the beginning of the emission period (EMIS).

The voltage of the first EM signal (EM1) is the gate-on voltage (VGH) during the initialization period (INI), the sensing period (SEN), and the emission period (EMIS), and the gate-off voltage (VGL) during the anode reset period (AR). am. The voltage of the first EM signal EM1 may be the gate-on voltage (VGH) or the gate-off voltage (VGL) during the data writing period (WR). The first switch element T01 is turned on in response to the gate-on voltage VGH of the first EM signal EM1 and turned off in response to the gate-off voltage VGL of the first EM signal EM1. .

The voltage of the second EM signal (EM2) is the gate-on voltage (VGH) during the initialization period (INI), anode reset period (AR), and emission period (EMIS), and is the gate-on voltage (VGH) during the sensing period (SEN) and data writing period (WR). is the gate-off voltage (VGL). The second switch element T02 is turned on in response to the gate-on voltage VGH of the second EM signal EM2 and turned off in response to the gate-off voltage VGL of the second EM signal EM2. .

The voltage of the first scan signal (SCAN) is generated as a pulse of the gate-on voltage (VGH) that is synchronized with the data voltage (Vdata) of the pixel data during the data writing period (WR), and during the other periods (INI, SEN, AR , EMIS) is the gate-off voltage (VGL). The third switch element T03 is turned on in response to the gate-on voltage VGH of the first scan signal SCAN and turned off in response to the gate-off voltage VGL of the first scan signal SCAN. .

The voltage of the second scan signal (INIT) is generated as a pulse of the gate-on voltage (VGH) during the initialization period (INI) and the sensing period (SEN), and is a gate-off voltage during other periods (WR, AR, EMIS). (VGL). The fourth switch element T04 is turned on in response to the gate-on voltage VGH of the second scan signal INIT and turned off in response to the gate-off voltage VGL of the second scan signal INIT. .

The voltage of the third scan signal (SENSE) is the gate-on voltage (VGH) during the initialization period (INI), sensing period (SEN), data writing period (WR), and anode reset period (AR), and the emission period (EMIS) is the gate-off voltage (VGL). The fifth switch element T05 is turned on in response to the gate-on voltage VGH of the third scan signal SENSE and turned off in response to the gate-off voltage VGL of the third scan signal SENSE. .

During the initialization period (INI), the initialization voltage (Vinit) is applied to the second node (DTG), and the reference voltage (Vref) is applied to the third node (DTS) to form the first capacitor (Cst) and the driving element (DT). The gate-source voltage (Vgs) is initialized. During the sensing period (SEN), the threshold voltage (Vth) of the driving element (DT) is sampled and stored in the first capacitor (Cst). During the data writing period (WR), the data voltage (Vdata) is applied to the second node (DTG), and the voltage charged in the first capacitor (Cst) is compensated to the data voltage (Vdata) by the threshold voltage of the driving element (DT). changes to During the anode reset period (AR), the reference voltage (Vref) is applied to the third node (DTS) and the fourth node (n4), so that the gate-source voltage (Vgs) of the driving element (DT) changes in the low-speed driving mode. It is suppressed. During the emission period (EMIS), a current path is formed between the first constant voltage line (PL1) and the second constant voltage line (PL2) and is generated according to the gate-source voltage (Vgs) of the driving element (DT). The light emitting element (EL) is driven by the current. The light emitting element EL may emit light according to the current from the driving element DT after the boosting period BOOST during the light emission period EMIS.

The driving element (DT) generates a current according to the gate-source voltage (Vgs) to drive the light emitting element (EL). The driving element DT includes a first electrode connected to the first node DTD, a gate electrode connected to the second node DTG, and a second electrode connected to the third node DTS.

The light emitting element (EL) can be implemented as OLED. The light emitting element EL includes an anode electrode, a cathode electrode, and an organic compound layer formed between these electrodes. The anode electrode of the light emitting device EL may be connected to the fourth node n4, and the cathode electrode may be connected to the second constant voltage line PL2 to which the pixel base voltage EVSS is applied. The light emitting element (EL) includes a capacitor (Cel) formed between an anode electrode and a cathode electrode.

The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), a light emission layer (EML), an electron transport layer (ETL), and an electron injection layer. , EIL), but is not limited thereto. When voltage is applied to the anode and cathode electrodes of the light emitting device (EL), holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) move to the light emitting layer (EML), forming excitons. At this time, visible light is emitted from the light emitting layer (EML). The light emitting device (EL) may be implemented in a tandem structure in which a plurality of light emitting layers are stacked. Tandem-structured light emitting elements (ELs) can improve the brightness and lifespan of pixels.

Considering the lifespan and required current of each color of the subpixels, the size and aperture ratio of the subpixels are different for each color, and accordingly, the capacitor capacity and size of the light emitting element EL may be different for each color of the subpixels.

The first capacitor (Cst) is connected between the second node (DTG) and the third node (DTS). The first capacitor Cst is initialized in the initialization period INI and then stores the threshold voltage Vth of the driving element DT in the sensing period SEN. The first capacitor (Cst) stores the data voltage (Vdata) of the pixel data compensated by the threshold voltage (Vth) of the driving element (DT) in the data writing period (WR), and then stores the data voltage (Vdata) of the pixel data in the anode reset period (AR) and the light emission period. The voltage (Vgs) between the gate and source of the driving element (DT) is maintained during (EMIS).

The second capacitor Ca may be connected between the fifth constant voltage line PL5 and the third node DTS, or between the first constant voltage line PL1 and the third node DTS. Prevents loss of data voltage (Vdata) during the data writing period (WR). The transfer rate (Data DR) of the data voltage (Vdata) is expressed in Equation 1 below.

Here, C _{DTS_par} is the parasitic capacity connected to the third node (DTS).

The larger the C _{DTS_hold} value, the less data voltage (Vdata) is transmitted and the loss of data voltage (Vdata) is reduced. Meanwhile, because the design area of the subpixel is limited, if the second capacitor Ca is designed with the same capacity in the subpixels, loss of data voltage may occur in the subpixel with a large current demand. The present invention considers the amount of current required for each color of the subpixels (R, G, B) and minimizes the loss of data voltage in all subpixels by relatively enlarging the second capacitor (Ca) in the subpixel with a large current requirement. And even without increasing the data voltage, the pixels can be made to emit high brightness.

The first switch element T01 is connected between the first constant voltage line PL1 to which the pixel driving voltage EVDD is applied and the first node DTD to set the gate-on voltage VGH of the first EM signal EM1. It turns on in response. When the first switch element T01 is turned on, the pixel driving voltage EVDD is applied to the first node DTD. The first switch element T01 is in an off state when the voltage of the first EM signal EM1 is the gate-off voltage VGL. The first switch element T01 includes a first electrode connected to the first constant voltage line PL1, a gate electrode connected to the first gate line GL1 to which the first EM signal EM1 is applied, and a first node DTD. It includes a second electrode connected to.

The second switch element T02 is connected between the third node DTS and the fourth node n4 and is turned on in response to the gate-on voltage VGH of the second EM signal EM2. When the second switch element T02 is turned on, the third node DTS is connected to the fourth node n4. The second switch element T02 is in an off state when the voltage of the second EM signal EM2 is the gate-off voltage VGL. The second switch element T02 is connected to a first electrode connected to the third node DTS, a gate electrode connected to the second gate line GL2 to which the second EM signal EM2 is applied, and a fourth node n4. It includes a connected second electrode.

The third switch element (T03) is connected between the data line (DL) to which the data voltage (Vdata) of the pixel data is applied and the second node (DTG) and is connected to the gate-on voltage (VGH) of the first scan signal (SCAN). It turns on in response. When the third switch element T03 is turned on, the data voltage Vdata is applied to the second node DTG. The third switch element T03 is in an off state when the voltage of the first scan signal SCAN is the gate-off voltage VGL. The third switch element T03 includes a first electrode connected to the data line DL, a gate electrode connected to the third gate line GL3 to which the first scan signal SCAN is applied, and a second node connected to DTG. Includes a second electrode.

The fourth switch element T04 is connected between the third constant voltage line PL3 to which the initialization voltage Vinit is applied and the second node DTG and is connected to the gate-on voltage VGH of the second scan signal INIT. It turns on in response. When the fourth switch element T04 is turned on, the initialization voltage Vinit is applied to the second node DTG. The fourth switch element T04 is in an off state when the voltage of the second scan signal INIT is the gate-off voltage VGL. The fourth switch element T04 includes a first electrode connected to the third constant voltage line PL3, a gate electrode connected to the fourth gate line GL4 to which the second scan signal INIT is applied, and a second node DTG. It includes a second electrode connected to.

The fifth switch element (T05) is connected between the fourth constant voltage line (PL4) to which the reference voltage (Vref) is applied and the fourth node (n4) and is connected to the gate-on voltage (VGH) of the third scan signal (SENSE). It turns on in response. When the fifth switch element T05 is turned on, the reference voltage Vref is applied to the fourth node n4. The fifth switch element T05 is in an off state when the voltage of the third scan signal SENSE is the gate-off voltage VGL. The fifth switch element T05 includes a first electrode connected to the fourth constant voltage line PL4, a gate electrode connected to the fifth gate line GL5 to which the third scan signal SENSE is applied, and a fourth node n4. It includes a second electrode connected to.

The ratio of the first capacitor (Cst) and the second capacitor (Ca) may vary depending on the color of the subpixels (R, G, and B). The ratio of the second capacitor (Ca) to the first capacitor (Cst), which minimizes data voltage loss and reduces the data voltage range so that subpixels can emit light with high brightness, is 1:1.5 in red:green:blue at a color temperature of 6500K. It could be 2. For example, in the red subpixel R, the capacitances of the first capacitor Cst and the second capacitor Ca have the same value. In comparison, the capacity of the second capacitor (Ca) in the green subpixel (G) is 1.5 times larger than the first capacitor (Cst), and the capacity of the second capacitor (Ca) in the blue subpixel (B) is greater than that of the first capacitor (Cst). It can be twice as large as (Cst). The capacity of the first capacitor Cst in all subpixels R, G, and B may be designed to have the same value. In this case, the capacity of the second capacitor Ca may be differentially applied to the subpixels R, G, and B in a ratio of 1:1.5:2 in red:green:blue. The capacity of the second capacitor Ca may be determined by the size of the electrode when the dielectric layer thickness of the capacitor is the same in the subpixels, as shown in FIGS. 4 and 5. Meanwhile, the above ratio may vary when the color temperature values are different.

Figure 8 is a circuit diagram showing a pixel circuit according to another embodiment of the present invention. FIG. 9 is a waveform diagram showing the gate signal applied to the pixel circuit shown in FIG. 8 and the voltages of main nodes. Components of the pixel circuit shown in FIG. 8 that are substantially the same as those of the pixel circuit of the above-described embodiment will be assigned the same reference numerals, and detailed description thereof will be omitted.

Referring to Figures 8 and 9, the pixel circuit includes a light-emitting element (EL), a driving element (DT) that drives the light-emitting element (EL), a plurality of switch elements (T01 to T05), a first capacitor (Cst), and a second capacitor (CA). The driving element (DT) and switch elements (T01 to T05) can be implemented as n-channel oxide TFT.

The pixel circuit is connected to a data line (DL) to which the data voltage (Vdata) of pixel data is applied, and to gate lines (GL1 to GL5) to which gate signals (EM1, EM2, INIT, SCAN, and SENSE) are applied. The pixel circuit includes a first constant voltage line (PL1) to which the pixel driving voltage (EVDD) is applied, a second constant voltage line (PL2) to which the pixel base voltage (EVSS) is applied, and a third constant voltage line to which the initialization voltage (Vinit) is applied ( It is connected to power lines to which direct current voltage (or constant voltage) is applied, such as PL3) and the fourth constant voltage line PL4 to which the reference voltage (Vref) is applied. Power lines to which constant voltage lines are connected on the display panel 100 may be commonly connected to all pixels.

The voltage level of each of the constant voltages (EVDD, EVSS, Vinit, and Vref) applied to the pixel circuit may be set in consideration of the voltage margin for operation in the saturation region of the driving element DT. The voltage levels of constant voltages (EVDD, EVSS, Vinit, Vref) can be set to the condition EVDD > Vref > Vinit > EVSS.

The gate signals (EM1, EM2, INIT, SCAN, SENSE) include pulses that swing between the gate-on voltage (VGH) and the gate-off voltage (VGL). The gate-on voltage (VGH) may be set to a voltage level higher than the pixel driving voltage (EVDD), and the gate-off voltage (VGL) may be set to a voltage level lower than the pixel base voltage.

The gate signals (INIT, SENSE, SCAN, EM1, EM2) include a first emission control signal (hereinafter referred to as “signal”) (EM1), a second EM signal (EM2), a first scan signal (SCAN), It includes a second scan signal (INIT) and a third scan signal (SENSE). The first EM signal EM1 is the first gate signal, the second EM signal EM2 is the second gate signal, the first scan signal SCAN is the third gate signal, and the second scan signal INIT is the fourth gate signal. signal and the third scan signal (SENSE) can each be interpreted as a fifth gate signal.

The pixel circuit disposed in each subpixel may be driven in the following order: an initialization period (INI), a sensing period (SEN), a data writing period (WR), an anode reset period (AR), and an emission period (EMIS). The initialization period (INI), sensing period (SEN), data writing period (WR), anode reset period (AR), and emission period (EMIS) are based on the waveforms of the gate signals (EM1, EM2, INIT, SCAN, SENSE). It can be defined by A boosting period (BOOST) in which the voltages of the second and third nodes (DTG and DTS) increase may be included at the beginning of the emission period (EMIS).

The voltage of the first EM signal (EM1) is the gate-on voltage (VGH) during the initialization period (INI), the sensing period (SEN), and the emission period (EMIS), and the gate-off voltage (VGL) during the anode reset period (AR). am. The voltage of the first EM signal EM1 may be the gate-on voltage (VGH) or the gate-off voltage (VGL) during the data writing period (WR). The first switch element T01 is turned on in response to the gate-on voltage VGH of the first EM signal EM1 and turned off in response to the gate-off voltage VGL of the first EM signal EM1. .

The voltage of the second EM signal (EM2) is the gate-on voltage (VGH) during the initialization period (INI), anode reset period (AR), and emission period (EMIS), and is the gate-on voltage (VGH) during the sensing period (SEN) and data writing period (WR). is the gate-off voltage (VGL). The second switch element T02 is turned on in response to the gate-on voltage VGH of the second EM signal EM2 and turned off in response to the gate-off voltage VGL of the second EM signal EM2. .

The voltage of the first scan signal (SCAN) is generated as a pulse of gate-on voltage (VGH) synchronized with the data voltage (Vdata) of pixel data during the data writing period (WR), and is a gate-off voltage (VGL) during other periods (INI, SEN, AR, EMIS). The third switch element (T03) is turned on in response to the gate-on voltage (VGH) of the first scan signal (SCAN), and is turned off in response to the gate-off voltage (VGL) of the first scan signal (SCAN).

The voltage of the second scan signal (INIT) is generated as a pulse of the gate-on voltage (VGH) during the initialization period (INI) and the sensing period (SEN), and is a gate-off voltage during other periods (WR, AR, EMIS). (VGL). The fourth switch element T04 is turned on in response to the gate-on voltage VGH of the second scan signal INIT and turned off in response to the gate-off voltage VGL of the second scan signal INIT. .

The voltage of the third scan signal (SENSE) is the gate-on voltage (VGH) during the initialization period (INI), sensing period (SEN), data writing period (WR), and anode reset period (AR), and the emission period (EMIS) is the gate-off voltage (VGL). The fifth switch element T05 is turned on in response to the gate-on voltage VGH of the third scan signal SENSE and turned off in response to the gate-off voltage VGL of the third scan signal SENSE. .

During the initialization period (INI), the initialization voltage (Vinit) is applied to the second node (DTG), and the reference voltage (Vref) is applied to the third node (DTS) to form the first capacitor (Cst) and the driving element (DT). The gate-source voltage (Vgs) is initialized. During the sensing period (SEN), the second switch element (T02) is turned off and the fifth switch element (T05) is turned on, so the current path between the third node (DTS) and the fourth node (n4) current path) is blocked and a reference voltage (Vref) is applied to the anode electrode of the light emitting element (EL). As a result, the residual charge of the light emitting device (EL) can be removed, and the phenomenon in which the ripple of the low potential power supply voltage (ELVSS) affects the anode and the third node (DTS) of the light emitting device (EL) can be prevented. It can be prevented.

During the sensing period (SEN), the voltage of the third node (DTS) increases, so that the voltage between the second and third nodes (DTG, DTS), that is, the gate-source voltage (Vgs) of the driving element (DT) increases. When the threshold voltage (Vth) is reached, the driving element (DT) is turned off and the threshold voltage (Vth) is sampled and stored in the first capacitor (Cst).

During the data writing period (WR), the data voltage (Vdata) is applied to the second node (DTG), and the voltage charged in the first capacitor (Cst) is compensated to the data voltage (Vdata) by the threshold voltage of the driving element (DT). changes to

During the anode reset period (AR), the reference voltage (Vref) is applied to the third node (DTS) and the fourth node (n4), so that the gate-source voltage (Vgs) of the driving element (DT) changes in the low-speed driving mode. It is suppressed.

During the boosting period (BOOST), the voltage of the second and third nodes (DTG, DTS) rises to the turn-on voltage of the light emitting device (EL), and at this time, the switch device (T02) turns on and turns on the third node (DTG, DTS). Since the node (DTS) and the fourth node (n4) are connected and become the same node, the boosting speed is increased without being affected by the second capacitor (CA) connected between the third node (DTS) and the fourth node (n4). do.

During the emission period (EMIS), a current path is formed between the first constant voltage line (PL1) and the second constant voltage line (PL2), and the pixel circuit operates as a source follower circuit to drive the driving element ( The light emitting element (EL) is driven by a current generated according to the gate-source voltage (Vgs) of DT). The light emitting element EL may emit light according to the current from the driving element DT after the boosting period BOOST during the light emission period EMIS.

The voltages of the first and second EM signals EM1 and EM2 may swing between the gate-on voltage (VGH) and the gate-off voltage (VGL) to improve low gray level expression in the light emission stage (Tem). The voltages of the first and second EM signals EM1 and EM2 may swing at a duty ratio set to a preset pulse width modulation (PWM) during the emission period EMIS.

The driving element (DT) generates a current according to the gate-source voltage (Vgs) to drive the light emitting element (EL). The driving element DT includes a first electrode connected to the first node DTD, a gate electrode connected to the second node DTG, and a second electrode connected to the third node DTS.

The light emitting element (EL) can be implemented as OLED. The light emitting element EL includes an anode electrode, a cathode electrode, and an organic compound layer formed between these electrodes. The anode electrode of the light emitting device EL may be connected to the fourth node n4, and the cathode electrode may be connected to the second constant voltage line PL2 to which the pixel base voltage EVSS is applied. The light emitting element (EL) may include a capacitor (Cel) formed between an anode electrode and a cathode electrode.

The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), a light emission layer (EML), an electron transport layer (ETL), and an electron injection layer. , EIL), but is not limited thereto. When voltage is applied to the anode and cathode electrodes of the light emitting device (EL), holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) move to the light emitting layer (EML), forming excitons. At this time, visible light is emitted from the light emitting layer (EML). The light emitting device (EL) may be implemented in a tandem structure in which a plurality of light emitting layers are stacked. Tandem-structured light emitting elements (ELs) can improve the brightness and lifespan of pixels.

The first capacitor (Cst) is connected between the second node (DTG) and the third node (DTS). The first capacitor Cst is initialized in the initialization period INI and then stores the threshold voltage Vth of the driving element DT in the sensing period SEN. The first capacitor (Cst) stores the data voltage (Vdata) of the pixel data compensated by the threshold voltage (Vth) of the driving element (DT) in the data writing period (WR), and then stores the data voltage (Vdata) of the pixel data in the anode reset period (AR) and the light emission period. The voltage (Vgs) between the gate and source of the driving element (DT) is maintained during (EMIS).

The second capacitor (CA) is connected between the third node (DTS) and the fourth node (n4). When the second switch element (T02) is turned on in the boosting period (BOOST), the third node (DTS) and the fourth node (n4) are shorted through the second switch element (T02) to be turned on. circuit) and become substantially the same node, the charge is discharged in the second capacitor (CA) and no additional charge is charged. Accordingly, the voltage boosting of the second and third nodes (DTG and DTS) during the boosting period (BOOST) is not affected by the second capacitor (CA) connected between the third node (DTS) and the fourth node (n4). No. As a result, the voltage boosting speed of the second node (DTG) and the third node (DTS) increases, thereby shortening the boosting period (BOOST).

Shortening the boosting period (BOOST) quickly increases the current amount of the light emitting device (EL), thereby reducing the luminance sensitivity of the light emitting device (EL) according to the voltage change of the third node (DTS). As a result, an effect similar to that of increasing the S-factor of the driving element DT can be obtained. S-factor can be interpreted as having the same meaning as “sub-threshold slope.” As S-factor increases, the threshold voltage and/or mobility deviation of the driving element, which causes deterioration of image quality in low grayscale areas, and the first capacitor Since the luminance of the light emitting element (EL) does not change sensitively due to the capacitance deviation of (Cst), constant voltage (EVDD, EVSS, Vinit, Vref) deviation, etc., the luminance and chromaticity of the pixels can be uniformly controlled in low gray levels.

Due to the shortening of the boosting period (BOOST), the current amount of the light emitting element (EL) can quickly increase. Shortening the boosting period (BOOST) can not only improve image quality at low gray levels, that is, when pixels are driven at low brightness, but also improve power consumption of the display device because the data voltage (Vdata) can be lowered without deteriorating image quality. You can.

The first switch element T01 is connected between the first constant voltage line PL1 to which the pixel driving voltage EVDD is applied and the first node DTD to set the gate-on voltage VGH of the first EM signal EM1. It turns on in response. When the first switch element T01 is turned on, the pixel driving voltage EVDD is applied to the first node DTD. The first switch element T01 is in an off state when the voltage of the first EM signal EM1 is the gate-off voltage VGL. The first switch element T01 includes a first electrode connected to the first constant voltage line PL1, a gate electrode connected to the first gate line GL1 to which the first EM signal EM1 is applied, and a first node DTD. It includes a second electrode connected to.

The second switch element T02 is connected between the third node DTS and the fourth node n4 and is turned on in response to the gate-on voltage VGH of the second EM signal EM2. When the second switch element T02 is turned on, the third node DTS is connected to the fourth node n4. The second switch element T02 is in an off state when the voltage of the second EM signal EM2 is the gate-off voltage VGL. The second switch element T02 is connected to a first electrode connected to the third node DTS, a gate electrode connected to the second gate line GL2 to which the second EM signal EM2 is applied, and a fourth node n4. It includes a connected second electrode.

The third switch element (T03) is connected between the data line (DL) to which the data voltage (Vdata) of the pixel data is applied and the second node (DTG) and is connected to the gate-on voltage (VGH) of the first scan signal (SCAN). It turns on in response. When the third switch element T03 is turned on, the data voltage Vdata is applied to the second node DTG. The third switch element T03 is in an off state when the voltage of the first scan signal SCAN is the gate-off voltage VGL. The third switch element T03 includes a first electrode connected to the data line DL, a gate electrode connected to the third gate line GL3 to which the first scan signal SCAN is applied, and a second node connected to DTG. Includes a second electrode.

The fourth switch element T04 is connected between the third constant voltage line PL3 to which the initialization voltage Vinit is applied and the second node DTG and is connected to the gate-on voltage VGH of the second scan signal INIT. It turns on in response. When the fourth switch element T04 is turned on, the initialization voltage Vinit is applied to the second node DTG. The fourth switch element T04 is in an off state when the voltage of the second scan signal INIT is the gate-off voltage VGL. The fourth switch element T04 includes a first electrode connected to the third constant voltage line PL3, a gate electrode connected to the fourth gate line GL4 to which the second scan signal INIT is applied, and a second node DTG. It includes a second electrode connected to.

The fifth switch element (T05) is connected between the fourth constant voltage line (PL4) to which the reference voltage (Vref) is applied and the fourth node (n4) and is connected to the gate-on voltage (VGH) of the third scan signal (SENSE). It turns on in response. When the fifth switch element T05 is turned on, the reference voltage Vref is applied to the fourth node n4. The fifth switch element T05 is in an off state when the voltage of the third scan signal SENSE is the gate-off voltage VGL. The fifth switch element T05 includes a first electrode connected to the fourth constant voltage line PL4, a gate electrode connected to the fifth gate line GL5 to which the third scan signal SENSE is applied, and a fourth node n4. It includes a second electrode connected to.

10 and 11 are circuit diagrams showing pixel circuits according to another embodiment of the present invention. In the pixel circuit shown in FIGS. 10 and 11, components that are substantially the same as those of the pixel circuit in the above-described embodiment will be assigned the same reference numerals, and detailed description thereof will be omitted.

Referring to FIG. 10, the pixel circuit includes a light-emitting element (EL), a driving element (DT) for driving the light-emitting element (EL), a plurality of switch elements (T11 to T14), a first capacitor (Cst), and a second Contains a capacitor (Ca). The driving element (DT) and switch elements (T11 to T14) can be implemented as n-channel oxide TFT.

The pixel circuit is connected to a data line (DL) to which the data voltage (Vdata) of pixel data is applied and to gate lines (GL1 to GL4) to which gate signals (EM, INIT, SCAN, and SENSE) are applied. The pixel circuit includes a first constant voltage line (PL1) to which the pixel driving voltage (EVDD) is applied, a second constant voltage line (PL2) to which the pixel base voltage (EVSS) is applied, and a third constant voltage line to which the initialization voltage (Vinit) is applied ( It is connected to power lines to which a direct current voltage (or constant voltage) is applied, such as PL3), a fourth constant voltage line (PL4) to which a reference voltage (Vref) is applied, and a fifth constant voltage line (PL5) to which a constant voltage (Vdc) is applied. Power lines to which constant voltage lines are connected on the display panel 100 may be commonly connected to all pixels. Constant voltage (Vdc) can be replaced with pixel driving voltage (EVDD). In this case, since the second capacitor Ca is connected to the first constant voltage line PL1 to which the pixel driving voltage EVDD is applied, the fifth constant voltage line PL5 may be omitted.

The gate signals (EM, INIT, SCAN, SENSE) include an EM signal (EM), a first scan signal (SCAN), a second scan signal (INIT), and a third scan signal (SENSE). The EM signal (EM1) is the first gate signal, the first scan signal (SCAN) is the second gate signal, the second scan signal (INIT) is the third gate signal, and the third scan signal (SENSE) is the fourth gate signal. Each can be interpreted as:

As described above, the driving period of the pixel circuit shown in FIG. 10 is divided into an initialization period (INI), a sensing period (SEN), a data writing period (WR), an anode reset period (AR), and an emission period (EMIS). You can lose. The initialization period (INI), sensing period (SEN), data writing period (WR), anode reset period (AR), and emission period (EMIS) are defined by the waveforms of the gate signals (EM, INIT, SCAN, SENSE). It can be.

The anode electrode of the light emitting device EL may be connected to the third node DTS, and the cathode electrode may be connected to the second constant voltage line PL2 to which the pixel base voltage EVSS is applied. The light emitting element (EL) includes a capacitor (Cel) formed between an anode electrode and a cathode electrode.

The first capacitor (Cst) is connected between the second node (DTG) and the third node (DTS). The second capacitor Ca may be connected between the fifth constant voltage line PL5 and the third node DTS, or between the first constant voltage line PL1 and the third node DTS.

The first switch element T11 is connected between the first constant voltage line PL1 to which the pixel driving voltage EVDD is applied and the first node DTD and responds to the gate-on voltage VGH of the EM signal EM. It turns on. The first switch element T11 is in an off state when the voltage of the EM signal EM is the gate-off voltage VGL. The EM signal (EM) may be applied as the first EM signal (EM1) shown in FIG. 7. The first switch element T11 includes a first electrode connected to the first constant voltage line PL1, a gate electrode connected to the first gate line GL1 to which the EM signal EM is applied, and a first node connected to DTD. Includes a second electrode.

The second switch element T12 is connected between the data line DL and the second node DTG and is turned on in response to the gate-on voltage VGH of the first scan signal SCAN shown in FIG. 7. . When the second switch element T12 is turned on, the data voltage Vdata is applied to the second node DTG. The second switch element T12 is in an off state when the voltage of the first scan signal SCAN is the gate-off voltage VGL. The second switch element T12 includes a first electrode connected to the data line DL, a gate electrode connected to the second gate line GL2 to which the first scan signal SCAN is applied, and a second node connected to DTG. Includes a second electrode.

The third switch element T13 is connected between the third constant voltage line PL3 and the second node DTG and turns on in response to the gate-on voltage VGH of the second scan signal INIT shown in FIG. 7. It comes on. When the third switch element T13 is turned on, the initialization voltage Vinit is applied to the second node DTG. The third switch element T13 is in an off state when the voltage of the second scan signal INIT is the gate-off voltage VGL. The third switch element T13 includes a first electrode connected to the third constant voltage line PL3, a gate electrode connected to the third gate line GL3 to which the second scan signal INIT is applied, and a second node DTG. It includes a second electrode connected to.

The fourth switch element T14 is connected between the fourth constant voltage line PL4 and the third node DTS and turns on in response to the gate-on voltage VGH of the third scan signal SENSE shown in FIG. 7. It comes on. When the fourth switch element T14 is turned on, the reference voltage Vref is applied to the third node DTS. The fourth switch element T14 is in an off state when the voltage of the third scan signal SENSE is the gate-off voltage VGL. The fourth switch element T14 includes a first electrode connected to the fourth constant voltage line PL4, a gate electrode connected to the fourth gate line GL4 to which the third scan signal SENSE is applied, and a third node DTS. It includes a second electrode connected to.

Referring to FIG. 11, the pixel circuit includes a light-emitting element (EL), a driving element (DT) for driving the light-emitting element (EL), a plurality of switch elements (T1 to T3), a first capacitor (Cst), and a second Contains a capacitor (Ca). The driving element (DT) and switch elements (T1 to T3) can be implemented as n-channel oxide TFT.

The pixel circuit is connected to a data line (DL) to which a data voltage (Vdata) of pixel data is applied, and gate lines (GL1 to GL3) to which gate signals (INIT, SCAN, and SENSE) are applied. The pixel circuit includes a first constant voltage line (PL1) to which the pixel driving voltage (EVDD) is applied, a second constant voltage line (PL2) to which the pixel base voltage (EVSS) is applied, and a third constant voltage line to which the initialization voltage (Vinit) is applied ( It is connected to power lines to which a direct current voltage (or constant voltage) is applied, such as PL3), a fourth constant voltage line (PL4) to which a reference voltage (Vref) is applied, and a fifth constant voltage line (PL5) to which a constant voltage (Vdc) is applied. Power lines to which constant voltage lines are connected on the display panel 100 may be commonly connected to all pixels. Constant voltage (Vdc) can be replaced with pixel driving voltage (EVDD). In this case, since the second capacitor Ca is connected to the first constant voltage line PL1 to which the pixel driving voltage EVDD is applied, the fifth constant voltage line PL5 may be omitted.

The gate signals INIT, SCAN, and SENSE include a first scan signal SCAN, a second scan signal INIT, and a third scan signal SENSE. The first scan signal SCAN can be interpreted as a first gate signal, the second scan signal INIT can be interpreted as a second gate signal, and the third scan signal SENSE can be interpreted as a third gate signal.

As described above, the driving period of the pixel circuit shown in FIG. 11 is divided into an initialization period (INI), a sensing period (SEN), a data writing period (WR), an anode reset period (AR), and an emission period (EMIS). You can lose. The initialization period (INI), sensing period (SEN), data write period (WR), anode reset period (AR), and emission period (EMIS) can be defined by the waveforms of the gate signals (INIT, SCAN, SENSE). there is.

The anode electrode of the light emitting device EL may be connected to the third node DTS, and the cathode electrode may be connected to the second constant voltage line PL2 to which the pixel base voltage EVSS is applied. The light emitting element (EL) includes a capacitor (Cel) formed between an anode electrode and a cathode electrode.

The first capacitor (Cst) is connected between the second node (DTG) and the third node (DTS). The second capacitor Ca may be connected between the fifth constant voltage line PL5 and the third node DTS, or between the first constant voltage line PL1 and the third node DTS.

The first switch element T1 is connected between the data line DL and the second node DTG and is turned on in response to the gate-on voltage VGH of the first scan signal SCAN. When the first switch element T1 is turned on, the data voltage Vdata is applied to the second node DTG. The first switch element T1 is in an off state when the voltage of the first scan signal SCAN is the gate-off voltage VGL. The first switch element T1 includes a first electrode connected to the data line DL, a gate electrode connected to the first gate line GL1 to which the first scan signal SCAN is applied, and a second node connected to the DTG. Includes a second electrode.

The second switch element T2 is connected between the third constant voltage line PL3 and the second node DTG and is turned on in response to the gate-on voltage VGH of the second scan signal INIT. When the second switch element T2 is turned on, the initialization voltage Vinit is applied to the second node DTG. The second switch element T2 is in an off state when the voltage of the second scan signal INIT is the gate-off voltage VGL. The second switch element T2 includes a first electrode connected to the third constant voltage line PL3, a gate electrode connected to the second gate line GL2 to which the second scan signal INIT is applied, and a second node DTG. It includes a second electrode connected to.

The third switch element T3 is connected between the fourth constant voltage line PL4 and the third node DTS and is turned on in response to the gate-on voltage VGH of the third scan signal SENSE. When the third switch element T3 is turned on, the reference voltage Vref is applied to the third node DTS. The third switch element T3 is in an off state when the voltage of the third scan signal SENSE is the gate-off voltage VGL. The third switch element T3 includes a first electrode connected to the fourth constant voltage line PL4, a gate electrode connected to the third gate line GL3 to which the third scan signal SENSE is applied, and a third node DTS. It includes a second electrode connected to.

In the case of the pixel circuits shown in FIGS. 10 and 11, there is no switch element between the driving element (DT) and the light emitting element (EL). In this case, since the second capacitor (Ca) and the capacitor (Cel) of the light emitting element (EL) are connected to the third node (DTS) during the data writing period (WR), these capacitors (Ca, Cel) are connected to the data voltage ( It affects the transfer rate of Vdata). For the pixel circuits shown in FIGS. 10 and 11, C _{DTS_hold} in Equation 1 is It can be expressed as

The size of the light emitting element (EL) is limited within the size of the subpixels (R, G, B). Accordingly, the capacitor Cel of the light emitting element EL is affected by the aperture ratio of the subpixels R, G, and B. The aperture ratio of the subpixels (R, G, B) is applied differently for each color in consideration of the lifespan of the light emitting element (EL). Among the subpixels (R, G, B), the blue subpixel (B), whose lifespan is of greatest concern, is larger than subpixels of other colors. Accordingly, the capacity of the capacitor Cel of the light emitting element EL formed in the blue subpixel B is larger than that of the subpixels R and B of other colors. For example, at a color temperature of 6500K, the aperture ratio of subpixels in red:green:blue may be 1:3~4:5~6. According to the aperture ratio of the subpixels for each color, the capacity of the capacitor Cel of the light emitting element EL increases in the following order: red subpixel (R), green subpixel (G), and blue subpixel (B). Accordingly, since the capacitor Cel of the light emitting element EL of the red subpixel R is smaller than that of the subpixels G and B of other colors, the transmission loss of the data voltage may increase.

In the case of the pixel circuits shown in FIGS. 10 and 11, considering the aperture ratio of different subpixels for each color, the capacity of the second capacitor (Ca) is the blue subpixel (B), green subpixel (G), and red subpixel. It is desirable to increase in order of (R). For example, in the subpixels (R, G, B) to which the pixel circuit shown in FIGS. 10 and 11 is applied, the capacity of the second capacitor (Ca) is differentially applied in red: green: blue at 2:1.5:1. However, it is not limited to this. The above ratio may vary when color temperature values are different.

FIG. 12 is a plan view showing second capacitors for each color of subpixels to which the pixel circuit shown in FIGS. 10 and 11 is applied. FIG. 13 is a cross-sectional view showing the cross-sectional structure of the second capacitor taken along the line “B-B'” in FIG. 12.

Referring to FIGS. 12 and 13 , the display panel 100 may include second capacitors Ca1, Ca2, and Ca3.

The pattern Mb of the first metal layer is connected to the subpixels R, G, and B without interruption, and the common capacitors Ca1, Ca2, and Ca3 are shared between the subpixels R, G, and B. It is an electrode (or lower electrode). A constant voltage (Vdc) or a pixel driving voltage (EVDD) is applied to the pattern (Mb) of the first metal layer. Accordingly, in the pixel circuit shown in FIGS. 10 and 11 , the pattern Mb of the first metal layer includes a constant voltage line to which the constant voltage Vdc is applied, or a constant voltage line to which the pixel driving voltage EVDD is applied.

The patterns (Ma1, Ma2, Ma3) of the second metal layer are formed as independent patterns or island patterns separated between neighboring subpixels (R, G, B). The patterns (Ma1, Ma2, Ma3) of the second metal layer include a 2-1 capacitor electrode (or upper electrode) (Ma1) disposed in the red subpixel (R), and a 2-2 disposed in the green subpixel (G). It is divided into a capacitor electrode (Ma2) and a second-third capacitor electrode (Ma3) disposed in the blue subpixel (B).

The 2-1 capacitor electrode Ma1 overlaps the pattern Mb of the first metal layer within the red subpixel R with the second insulating layer INS2 in between and faces the pattern Mb of the first metal layer. do. The 2-2 capacitor electrode Ma2 overlaps the pattern Mb of the first metal layer within the green subpixel G with the second insulating layer INS2 in between and faces the pattern Mb of the first metal layer. do. The 2-3 capacitor electrode Ma3 overlaps the pattern Mb of the first metal layer within the blue subpixel B with the second insulating layer INS2 in between and faces the pattern Mb of the first metal layer. do.

The 2-1 capacitor electrode Ma1 includes the third node DTS of the red subpixel R in the pixel circuit shown in FIGS. 10 and 11. The 2-2 capacitor electrode Ma2 includes the third node DTS of the green subpixel G in the pixel circuit shown in FIGS. 10 and 11. The 2-3 capacitor electrode Ma3 includes the third node DTS of the blue subpixel B in the pixel circuit shown in FIGS. 10 and 11.

In the case of the subpixels (R, G, B) to which the pixel circuit shown in FIGS. 10 and 11 is applied, the capacitor electrode is applied to the blue subpixel (B), green subpixel (G), and red subpixel (R) in that order. Their size may increase. In other words, the 2-1 capacitor electrode Ma1 is larger than the 2-2 and 2-3 capacitor electrodes Ma2 and Ma3, and the 2-2 capacitor electrode Ma2 is larger than the 2-3 capacitor electrode Ma2. It may be larger than (Ma3).

Since the contents of the specification described in the problem to be solved, the means to solve the problem, and the effect described above do not specify the essential features of the claim, the scope of the claim is not limited by the matters described in the content of the specification.

Although embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be made without departing from the technical spirit of the present invention. . Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but are for illustrative purposes, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive.

100: display panel 110: data driver
120: Gate driver 130: Timing controller
140: Power supply R: Red subpixel
G: Green subpixel B: Blue subpixel
C1: first capacitor Ca: second capacitor
Mb: Pattern of the first metal layer
Ma1, Ma2, Ma3: Pattern of the second metal layer (capacitor electrode)
INS1, INS2, INS3: Insulating layer EL: Light emitting element
DT: driving element
T01~T05, T11~T14, T1~T3: Switch elements
INI: Initialization period SEN: Sensing period
WR: data writing period AR: anode reset period
EMIS: Emission Period

Claims (22)

A subpixel of a first color;
a subpixel of a second color; and
comprising subpixels of a third color,
Each of the first to third color subpixels is,
A driving element including a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node;
a light emitting element including an anode electrode connected to a fourth node and driven by current from the driving element;
a first capacitor connected between the second node and the third node; and
A second capacitor connected between a constant voltage node to which a constant voltage is applied and the third node, or connected between the third node and the fourth node,
A display panel wherein the capacity of the second capacitor is different for each color of the subpixels. According to claim 1,
Each of the first to third color subpixels is,
a first electrode to which a pixel driving voltage is applied, a gate electrode to which a first gate signal is applied, and a first switch element connected to the first node; and
Further comprising a second switch element including a first electrode connected to the third node, a gate electrode to which a second gate signal is applied, and a second electrode connected to the fourth node,
The second capacitor is,
a 2-1 capacitor disposed in the first color subpixel;
a 2-2 capacitor disposed in the second color subpixel; and
The third color subpixel includes second-third capacitors,
The first color is red, the second color is green, and the third color is blue,
The capacity of the 2-3 capacitor is greater than the capacity of each of the 2-1 and 2-2 capacitors,
A display panel in which the capacity of the 2-2 capacitor is greater than the capacity of the 2-1 capacitor. According to claim 2,
A pattern of a first metal layer disposed on a first insulating layer and connected to the first to third color subpixels;
a second insulating layer covering the pattern of the first metal layer and the first insulating layer;
Patterns of a second metal layer disposed on the second insulating layer and in each of the first to third color subpixels and separated between the subpixels;
Further comprising a third insulating layer covering the patterns of the second metal layer and the second insulating layer,
The patterns of the second metal layer are,
a 2-1 capacitor electrode disposed in the first color subpixel;
a 2-2 capacitor electrode disposed in the second color subpixel; and
Includes 2-3 capacitor electrodes disposed in the third color subpixel,
The 2-3 capacitor electrode is larger than each of the 2-1 and 2-2 capacitor electrodes,
A display panel in which the 2-2 capacitor electrode is larger than the 2-1 capacitor electrode. According to claim 2,
A display panel wherein the constant voltage applied to the 2-1st to 2-3rd capacitors is equal to or different from the pixel driving voltage. According to claim 2,
Each of the first to third color subpixels is,
a third switch element including a first electrode connected to a data line to which a data voltage of pixel data is applied, a gate electrode to which a third gate signal is applied, and a second electrode connected to the second node;
a fourth switch element including a first electrode to which an initialization voltage is applied, a gate electrode to which a fourth gate signal is applied, and a second electrode connected to the second node;
A fifth switch element including a first electrode to which a reference voltage is applied, a gate electrode to which a fifth gate signal is applied, and a second electrode connected to the fourth node,
A display panel wherein capacitances of the first capacitors in the subpixels of the first to third colors are the same. According to claim 5,
The pixel circuit disposed in each of the first to third color subpixels is driven in the following order: an initialization period, a sensing period, a data writing period, an anode reset period, and an emission period,
The voltage of the first gate signal is the gate-on voltage during the initialization period, the sensing period, and the light emission period, the gate-off voltage during the anode reset period, and the gate-on voltage or the gate-off voltage during the data writing period. ego,
The voltage of the second gate signal is the gate-on voltage during the initialization period, the anode reset period, and the light emission period, and the gate-off voltage during the sensing period and the data writing period,
The voltage of the third gate signal is the gate-on voltage during the data writing period, and the gate-off voltage during the initialization period, the sensing period, the anode reset period, and the light emission period,
The voltage of the fourth gate signal is the gate-on voltage during the initialization period and the sensing period, and the gate-off voltage during the data writing period, the anode reset period, and the light emission period,
The voltage of the fifth gate signal is the gate-on voltage during the initialization period, the sensing period, the data writing period, and the anode reset period, and the gate-off voltage during the light emission period,
A display panel in which each of the first to fifth switch elements is turned on in response to the gate-on voltage and turned off in response to the gate-off voltage. According to claim 1,
Each of the first to third color subpixels is,
It further includes a first electrode to which a pixel driving voltage is applied, a gate electrode to which a first gate signal is applied, and a first switch element connected to the first node,
The second capacitor is,
a 2-1 capacitor disposed in the first color subpixel;
a 2-2 capacitor disposed in the second color subpixel; and
Including a 2-3 capacitor disposed in the third color subpixel,
The anode electrode of the light emitting device is connected to the third node,
The first color is red, the second color is green, and the third color is blue,
The capacity of the 2-1 capacitor is greater than the capacity of each of the 2-2 and 2-3 capacitors,
A display panel in which the capacity of the 2-2 capacitor is greater than the capacity of the 2-3 capacitor. According to claim 7,
A display panel in which the capacitor capacity of the light emitting device is large in that order: the third color subpixel, the second color subpixel, and the first color subpixel. According to claim 7,
A display panel wherein the constant voltage applied to the 2-1st to 2-3rd capacitors is equal to or different from the pixel driving voltage. According to claim 7,
Each of the first to third subpixels,
a second switch element including a first electrode connected to a data line to which a data voltage of pixel data is applied, a gate electrode to which a second gate signal is applied, and a second electrode connected to the second node;
a third switch element including a first electrode to which an initialization voltage is applied, a gate electrode to which a third gate signal is applied, and a second electrode connected to the second node; and
A fourth switch element including a first electrode to which a reference voltage is applied, a gate electrode to which a fourth gate signal is applied, and a second electrode connected to the third node,
A display panel wherein the first capacitors in the first to third subpixels have the same capacity. According to claim 1,
The second capacitor is,
a 2-1 capacitor disposed in the first color subpixel;
a 2-2 capacitor disposed in the second color subpixel; and
Including a 2-3 capacitor disposed in the third color subpixel,
A pixel driving voltage is applied to the first node,
The anode electrode of the light emitting device is connected to the third node,
The first color is red, the second color is green, and the third color is blue,
The capacity of the 2-1 capacitor is greater than the capacity of each of the 2-2 and 2-3 capacitors,
A display panel in which the capacity of the 2-2 capacitor is greater than the capacity of the 2-3 capacitor. According to claim 11,
A display panel in which the capacitor capacity of the light emitting device is large in that order: the third color subpixel, the second color subpixel, and the first color subpixel. According to claim 11,
A display panel wherein the constant voltage applied to the 2-1st to 2-3rd capacitors is equal to or different from the pixel driving voltage. According to claim 11,
Each of the first to third subpixels,
A first switch element including a first electrode connected to a data line to which a data voltage of pixel data is applied, a gate electrode to which a first gate signal is applied, and a second electrode connected to the second node;
a second switch element including a first electrode to which an initialization voltage is applied, a gate electrode to which a second gate signal is applied, and a second electrode connected to the second node; and
It includes a third switch element including a first electrode to which a reference voltage is applied, a gate electrode to which a third gate signal is applied, and a second electrode connected to the third node,
A display panel wherein the first capacitors in the first to third subpixels have the same capacity. A display panel including a plurality of data lines, a plurality of gate lines, a plurality of power lines, and a plurality of red subpixels, a plurality of green subpixels, and a plurality of blue subpixels;
a data driver that outputs a data voltage of pixel data to the data lines; and
It includes a gate driver that sequentially supplies gate signals to the gate lines,
Each of the subpixels includes a pixel circuit,
The pixel circuit is,
A driving element including a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node;
a light emitting element including an anode electrode connected to a fourth node and driven by current from the driving element;
a first capacitor connected between the second node and the third node; and
A second capacitor connected between a constant voltage node to which a constant voltage is applied and the third node, or connected between the third node and the fourth node,
A display device in which the capacity of the second capacitor is different for each color of the subpixels. According to claim 15,
Each of the subpixels is,
a first electrode to which a pixel driving voltage is applied, a gate electrode to which a first gate signal is applied, and a first switch element connected to the first node;
a second switch element including a first electrode connected to the third node, a gate electrode to which a second gate signal is applied, and a second electrode connected to the fourth node;
a third switch element including a first electrode connected to a data line to which a data voltage of pixel data is applied, a gate electrode to which a third gate signal is applied, and a second electrode connected to the second node;
a fourth switch element including a first electrode to which an initialization voltage is applied, a gate electrode to which a fourth gate signal is applied, and a second electrode connected to the second node; and
A fifth switch element including a first electrode to which a reference voltage is applied, a gate electrode to which a fifth gate signal is applied, and a second electrode connected to the fourth node,
The constant voltage applied to the second capacitor is the same as or different from the pixel driving voltage,
Capacitances of the first capacitors in the red subpixels, green subpixels, and blue subpixels are the same,
The capacity of the 2-3 capacitor of the blue subpixels is greater than the capacity of each of the 2-1 and 2-2 capacitors of the red and green subpixels,
A display device in which the capacity of the 2-2 capacitor of the green subpixels is greater than the capacity of the 2-1 capacitor of the red subpixels. According to claim 16,
The display panel is,
a pattern of a first metal layer disposed on a first insulating layer and connected to the red subpixels, the green subpixels, and the blue subpixels;
a second insulating layer covering the pattern of the first metal layer and the first insulating layer;
Patterns of a second metal layer disposed on the second insulating layer and disposed on each of the red subpixels, the green subpixels, and the blue subpixels to separate neighboring subpixels;
Further comprising a third insulating layer covering the patterns of the second metal layer and the second insulating layer,
The patterns of the second metal layer are,
a 2-1 capacitor electrode disposed in the red subpixel;
a 2-2 capacitor electrode disposed in the green sub-pixel; and
It includes second-third capacitor electrodes disposed in the blue subpixel,
The 2-3 capacitor electrode is larger than each of the 2-1 and 2-2 capacitor electrodes,
A display device in which the 2-2 capacitor electrode is larger than the 2-1 capacitor electrode. According to claim 15,
Each of the subpixels is,
a first electrode to which a pixel driving voltage is applied, a gate electrode to which a first gate signal is applied, and a first switch element connected to the first node;
a second switch element including a first electrode connected to a data line to which a data voltage of pixel data is applied, a gate electrode to which a second gate signal is applied, and a second electrode connected to the second node;
a third switch element including a first electrode to which an initialization voltage is applied, a gate electrode to which a third gate signal is applied, and a second electrode connected to the second node; and
It includes a fourth switch element including a first electrode to which a reference voltage is applied, a gate electrode to which a fourth gate signal is applied, and a second electrode connected to the third node,
The anode electrode of the light emitting device is connected to the third node,
The constant voltage applied to the second capacitor is the same as or different from the pixel driving voltage,
Capacitances of the first capacitors in the red subpixels, the green subpixels, and the blue subpixels are the same,
The capacitor capacity of the light emitting devices of the blue subpixels is greater than the capacitor capacity of the light emitting devices of the red subpixels and the green subpixels,
The capacitor capacity of the light emitting device of the green subpixels is greater than the capacitor capacity of the light emitting device of the red subpixels,
The capacity of the 2-1 capacitor of the red subpixels is greater than the capacity of each of the 2-2 and 2-3 capacitors of the green and blue subpixels,
A display device in which the capacity of the 2-2 capacitor of the green subpixels is greater than the capacity of the 2-3 capacitor of the blue subpixels. According to claim 15,
Each of the subpixels is,
A first switch element including a first electrode connected to a data line to which a data voltage of pixel data is applied, a gate electrode to which a first gate signal is applied, and a second electrode connected to the second node;
a second switch element including a first electrode to which an initialization voltage is applied, a gate electrode to which a second gate signal is applied, and a second electrode connected to the second node; and
It includes a third switch element including a first electrode to which a reference voltage is applied, a gate electrode to which a third gate signal is applied, and a second electrode connected to the third node,
The anode electrode of the light emitting device is connected to the third node,
A pixel driving voltage is applied to the first node,
The constant voltage applied to the second capacitor is the same as or different from the pixel driving voltage,
Capacitances of the first capacitors in the red subpixels, the green subpixels, and the blue subpixels are the same,
The capacitor capacity of the light emitting devices of the blue subpixels is greater than the capacitor capacity of the light emitting devices of the red subpixels and the green subpixels,
The capacitor capacity of the light emitting device of the green subpixels is greater than the capacitor capacity of the light emitting device of the red subpixels,
The capacity of the 2-1 capacitor of the red subpixels is greater than the capacity of each of the 2-2 and 2-3 capacitors of the green and blue subpixels, and the capacity of the 2-2 capacitor of the green subpixels is greater than the capacitance of each of the 2-2 and 2-3 capacitors of the green and blue subpixels. A display device larger than the capacity of the second-third capacitors of the blue subpixels. A driving element including a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node;
A light emitting device including an anode electrode connected to a fourth node and a cathode electrode to which a pixel base voltage is applied;
It includes a first electrode to which a pixel driving voltage is applied, a gate electrode to which a first EM signal is applied, and a second electrode connected to the first node to generate the constant voltage line in response to the gate-on voltage of the first EM signal. a first switch element connected to the first node;
The third node is connected in response to the gate-on voltage of the second EM signal, including a first electrode connected to the third node, a gate electrode to which the second EM signal is applied, and a second electrode connected to the fourth node. a second switch element connected to the fourth node;
Including a first electrode to which a data voltage is applied, a gate electrode to which a first scan pulse is applied, and a second electrode connected to the second node, the data voltage is converted to the second node in response to the gate-on voltage of the first scan pulse. A third switch element supplies power to node 2;
Including a first electrode to which an initialization voltage is applied, a gate electrode to which a second scan signal is applied, and a second electrode connected to the second node, the initialization voltage is applied to the second electrode in response to the gate-on voltage of the second scan signal. a fourth switch element supplying power to the node;
A first electrode connected to the fourth node, a gate electrode to which a third scan signal is applied, and a second electrode to which a reference voltage is applied are connected to the fourth node in response to the gate-on voltage of the third scan signal. A fifth switch element that supplies voltage;
A first capacitor connected between the second node and the third node: and
A pixel circuit including a second capacitor connected between the third node and the fourth node. According to claim 20,
The pixel circuit is driven in the following order: an initialization period, a sensing period, a data writing period, an anode reset period, and an emission period,
The voltage of the first gate signal is the gate-on voltage during the initialization period, the sensing period, and the light emission period, the gate-off voltage during the anode reset period, and the gate-on voltage or the gate-off voltage during the data writing period. ego,
The voltage of the second gate signal is the gate-on voltage during the initialization period, the anode reset period, and the light emission period, and the gate-off voltage during the sensing period and the data writing period,
The voltage of the third gate signal is the gate-on voltage during the data writing period, and the gate-off voltage during the initialization period, the sensing period, the anode reset period, and the light emission period,
The voltage of the fourth gate signal is the gate-on voltage during the initialization period and the sensing period, and the gate-off voltage during the data writing period, the anode reset period, and the light emission period,
The voltage of the fifth gate signal is the gate-on voltage during the initialization period, the sensing period, the data writing period, and the anode reset period, and the gate-off voltage during the light emission period,
A pixel circuit in which each of the first to fifth switch elements is turned on in response to the gate-on voltage and turned off in response to the gate-off voltage. According to claim 20,
The pixel circuit is driven in the following order: an initialization period, a sensing period, a data writing period, an anode reset period, and an emission period,
During the initialization period, the initialization voltage is applied to the second node and the reference voltage is applied to the third node,
During the sensing period, the threshold voltage of the driving element is stored in the first capacitor,
During the data writing period, the data voltage is applied to the second node,
During the anode reset period, the reference voltage is applied to the third node and the fourth node,
During the boosting period of the light emission period, the second switch element is turned on so that the third node and the fourth node are electrically connected to each other,
A pixel circuit in which the light emitting element emits light according to a current from a driving element after the boosting period.