KR20240076024A - Pixel circuit and display device including the same - Google Patents

Abstract

A pixel circuit and a display device including the same are disclosed. The pixel circuit of the present invention includes a first electrode connected to a first node to which a pixel driving voltage is applied, a gate electrode connected to a second node, and a driving element connected to a third node to drive a current to a light emitting element. a first switch element that turns on in response to the gate-on voltage of the first gate signal generated in the first step and supplies a first reference voltage to the second node; a second switch element that turns on in response to the gate-on voltage of the second gate signal generated in the second and third steps after the first step and supplies an initialization voltage to the second node; a third switch element that turns on in response to the gate-on voltage of the third gate signal generated in the first and second steps and supplies a second reference voltage to the third node; and a fourth switch element that is turned on in response to the gate-on voltage of the fourth gate signal in the fourth step after the third step and supplies a data voltage to the second node.

Description

Pixel circuit and display device including same {PIXEL CIRCUIT AND DISPLAY DEVICE INCLUDING THE SAME}

The present invention relates to a pixel circuit and a display device including the same.

Electroluminescence displays can be divided into inorganic light emitting displays and organic light emitting displays depending on the material of the light emitting layer. The active matrix type organic light emitting display device includes an organic light emitting diode (hereinafter referred to as “OLED”) that emits light on its own, has a fast response speed, and has high luminous efficiency, brightness, and viewing angle. There is an advantage. Organic light emitting displays have OLEDs (Organic Light Emitting Diodes, also known as OLEDs) formed in each pixel. Organic light emitting displays not only have a fast response speed and excellent luminous efficiency, brightness, and viewing angle, but also produce black gradations. Because it can be expressed in complete black, the contrast ratio and color reproduction rate are excellent.

Pixels of an organic light emitting display device include a pixel circuit including a driving element for driving an OLED and a capacitor connected to the driving element. The main node voltage of the pixel circuit may be different between subpixels due to the previous data voltage charged in the pixel circuit. Even if the main nodes of the pixel circuit are initialized within a limited time in this initial state, the voltages of the main nodes may not be uniform across all subpixels. In this case, crosstalk may be visible on the screen of the display panel.

The present invention aims to solve the above-described needs and/or problems.

The present invention provides a pixel circuit that can remove the influence of data voltage charged in a previous frame and prevent crosstalk from being recognized on the screen, and a display device including the same.

The problem of the present invention is not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

A pixel circuit according to an embodiment of the present invention includes a first electrode connected to a first node to which a pixel driving voltage is applied, a gate electrode connected to a second node, and a driving element connected to a third node to drive current to the light emitting device. ; a first switch element that turns on in response to the gate-on voltage of the first gate signal generated in the first step and supplies a first reference voltage to the second node; a second switch element that turns on in response to the gate-on voltage of the second gate signal generated in the second and third steps after the first step and supplies an initialization voltage to the second node; a third switch element that turns on in response to the gate-on voltage of the third gate signal generated in the first and second steps and supplies a second reference voltage to the third node; and a fourth switch element that is turned on in response to the gate-on voltage of the fourth gate signal in the fourth step after the third step and supplies a data voltage to the second node.

A display device of the present invention includes a display panel on which a plurality of data lines, a plurality of gate lines, a plurality of power lines, and a plurality of subpixels are arranged; a data driver that supplies data voltage to the data lines; a gate driver that supplies gate signals to the gate lines; and a power supply unit that outputs a constant voltage applied to the power lines. The constant voltage includes a pixel driving voltage, a pixel base voltage, a first reference voltage, an initialization voltage, and a second reference voltage. Each of the subpixels includes the pixel circuit.

In the present invention, after applying a first reference voltage to a second node to which the gate of the driving element is connected, an initialization voltage is applied to the second node to uniformly initialize the second node in each subpixel to provide a threshold voltage of the driving element. Sensing. As a result, the present invention can sense the threshold voltage of the driving element without being affected by the difference in the boosting level of the second node due to the data voltage charged in the previous frame, and thus can accurately compensate for the change in the threshold voltage of the driving element. and crosstalk defects can be improved.

The effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims.

1 is a circuit diagram showing a pixel circuit according to an embodiment of the present invention.
FIG. 2 is a waveform diagram showing the gate signal applied to the pixel circuit shown in FIG. 1 and the voltages of main nodes.
FIGS. 3A to 3C are diagrams showing a phenomenon in which ripple occurs in an initialization voltage in a pixel circuit of a comparative example.
Figure 4 is a plan view schematically showing power lines to which a first reference voltage and an initialization voltage are applied on the display panel.
Figure 5 is a block diagram showing a display device according to an embodiment of the present invention.
FIG. 6 is a cross-sectional view showing the cross-sectional structure of the display panel shown in FIG. 5.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms. The embodiments only serve to ensure that the disclosure of the present invention is complete, and those skilled in the art will be able to understand the present invention. It is provided to completely inform the scope of the invention, and the invention is only defined by the scope of the claims.

The shape, size, ratio, angle, number, etc. shown in the drawings for explaining embodiments of the present invention are illustrative, and the present invention is not limited to the matters shown in the drawings. Like reference numerals refer to substantially like elements throughout the specification. Additionally, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

When “provides,” “includes,” “has,” “consists of,” etc. mentioned in this specification are used, other parts may be added unless ‘only’ is used. If a component is expressed in the singular, it may be interpreted as plural unless specifically stated.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, ‘on ~’, ‘~on top’, ‘~below’, ‘~ next to’, ‘~connect, couple’, ‘intersection’ When the positional relationship and interconnection relationship between two components is described, such as '(crossing, intersecting)', etc., unless there is mention of 'immediately' or 'directly', there is one or more other components between the components. may be involved.

First, second, etc. may be used to distinguish components, but the function or structure of these components is not limited by the ordinal number or component name in front of the component.

The following embodiments can be partially or fully combined or combined with each other, and various technological interconnections and drives are possible. Each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

Each pixel is divided into a plurality of subpixels of different colors to implement color, and each subpixel includes a transistor used as a switch element or driving element. These transistors can be implemented as TFTs (Thin Film Transistors).

The driving circuit of the display device writes pixel data of the input image into pixels. The driving circuit of the flat panel display device includes a data driving circuit that supplies data signals to the data lines, and a gate driving circuit that supplies gate signals to the gate lines.

In the display device of the present invention, the pixel circuit and the gate driving circuit may include a plurality of transistors. The transistor may be an Oxide TFT containing an oxide semiconductor or a LTPS TFT containing Low Temperature Poly Silicon (LTPS). Hereinafter, the transistors constituting the pixel circuit and the gate driving circuit will be described focusing on an example implemented as an n-channel oxide TFT, but the present invention is not limited thereto.

A transistor is a three-electrode device including a gate, source, and drain. The source is an electrode that supplies carriers to the transistor. Within the transistor, carriers begin to flow from the source. The drain is the electrode through which carriers exit the transistor. In a transistor, the flow of carriers flows from the source to the drain. In the case of an n-channel transistor, because the carriers are electrons, the source voltage has a lower voltage than the drain voltage so that electrons can flow from the source to the drain. In an n-channel transistor, the direction of current flows from the drain to the source. In the case of a p-channel transistor, since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-channel transistor, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain may change depending on the applied voltage. Therefore, the invention is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as first and second electrodes.

The gate signal can swing between Gate On Voltage and Gate Off Voltage. The gate-on voltage is set to a voltage higher than the threshold voltage of the transistor. The gate-off voltage is set to a voltage lower than the threshold voltage of the transistor.

The transistor is turned on in response to the gate on voltage, while the transistor is turned off in response to the gate off voltage. In the case of an n-channel transistor, the gate-on voltage may be the gate high voltage and the gate-off voltage may be the gate low voltage.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings. In the following embodiments, the display device will be described focusing on the organic light emitting display device, but the present invention is not limited thereto. Additionally, the present invention is not limited by the names of components or signals in the following examples and claims.

1 is a circuit diagram showing a pixel circuit according to an embodiment of the present invention. FIG. 2 is a waveform diagram showing the gate signal applied to the pixel circuit shown in FIG. 1 and the voltages of main nodes.

1 and 2, the pixel circuit includes a light-emitting element (EL), a driving element (DT) that drives the light-emitting element (EL), a plurality of switch elements (T1 to T4), and a capacitor (Cst). do. The driving element (DT) and switch elements (T1 to T4) can be implemented as n-channel oxide TFT.

The pixel circuit is connected to a data line (DL) to which a data voltage (Vdata) is applied and gate lines to which gate signals (DINIT, INIT, SENSE, and SCAN) are applied. The pixel circuit includes a first constant voltage node PL1 to which the first reference voltage Vpre is applied, a second constant voltage node PL2 to which the initialization voltage Vinit is applied, and a third constant voltage node to which the second reference voltage Vref is applied. Connected to power nodes to which direct current voltage (or constant voltage) is applied, such as the node PL3, the fourth constant voltage node PL4 to which the pixel driving voltage is applied, and the fifth constant voltage node PL5 to which the pixel base voltage (EVSS) is applied. do. Power lines to which constant voltage nodes are connected on the display panel may be commonly connected to all pixels.

The pixel driving voltage EVDD is higher than the maximum voltage of the data voltage Vdata and is set to a voltage at which the driving element DT can operate in the saturation region. The first reference voltage (Vpre) and the initialization voltage (Vinit) are set to a voltage at which the driving element (DT) can be turned on, for example, a voltage within the voltage range between the maximum and minimum voltages of the data voltage (Vdata). You can. The first reference voltage (Vpre) may be set to the same voltage as the initialization voltage (Vinit). The pixel base voltage (ELVSS) is set to a voltage lower than the minimum voltage of the data voltage (Vdata). The second reference voltage (Vref) may be set to a voltage lower than the pixel base voltage (EVSS). The gate-on voltage (VGH) may be set to a voltage lower than the pixel driving voltage (EVDD) and higher than the maximum voltage of the data voltage, and the gate-off voltage (VGL) may be set to a voltage lower than the second reference voltage (Vref). The gate signals (DINIT, INIT, SENSE, SCAN) include pulses that swing between the gate-on voltage (VGH) and the gate-off voltage (VGL). The voltage applied to the pixel circuit is EVDD=20[V], EVSS=3[V], VGH=18[V], VGL=-6[V], Vpre = Vinit=4.34[V], Vref=0.5[V] ], Vdata = can be set to a voltage range of 4.5 [V] to 9 [V], but is not limited to this.

The light emitting element (EL) can be implemented as OLED. OLED includes an organic compound layer formed between an anode electrode connected to a third node (DTS) and a cathode electrode to which a pixel base voltage (EVSS) is applied. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), a light emission layer (EML), an electron transport layer (ETL), and an electron injection layer. , EIL), but is not limited thereto. When voltage is applied to the anode and cathode electrodes of an OLED, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) move to the light emitting layer (EML), forming excitons. At this time, visible light is emitted from the light emitting layer (EML). The light emitting element (EL) includes a capacitor (Cel) connected between an anode electrode and a cathode electrode. OLED used as a light emitting device (EL) may have a tandem structure in which a plurality of light emitting layers are stacked. OLED with a tandem structure can improve pixel brightness and lifespan.

The driving element (DT) generates current according to the gate-source voltage (Vgs) to drive the light emitting element (EL). The driving element DT includes a first electrode connected to the first node DTD, a gate electrode connected to the second node DTG, and a second electrode connected to the third node DTS. The first node (DTD) is directly connected to the fourth constant voltage node (PL4) to which the pixel driving voltage (EVDD) is applied, or is connected to the fourth constant voltage node (PL4) through another switch element controlled according to a light emission control signal omitted from the drawing. can be connected to The third node (DTS) may be directly connected to the anode electrode of the light emitting element (EL) or may be connected to the anode electrode through another switch element controlled according to a light emission control signal omitted from the drawing. The capacitor Cst is connected between the second node DTG and the third node DTS to store the gate-source voltage of the driving element DT.

The switch elements (T1 to T4) of the pixel circuit are a first switch element (T1) and a second gate that supply the first reference voltage (Vpre) to the second node (DTG) in response to the first gate signal (DINIT). A second switch element (T2) supplies an initialization voltage (Vinit) to the second node (DTG) in response to the signal (INIT), and a reference voltage (Vref) in response to the third gate signal (SENSE) to the third node ( a third switch element (T3) that supplies the data voltage (Vdata) of the pixel data to the second node (DTG) in response to the fourth gate signal (SCAN), and a fourth switch element (T4) that supplies the data to the second node (DTG). Includes.

The driving period of the pixel circuit can be divided into first to sixth stages (P1 to P6) defined by gate signals (DINIT, INIT, SENSE, and SCAN) as shown in FIG. 2. The first stage (P1) is approximately 1 horizontal period, the hold period between the end of the first stage (P1) and the start of the second stage (P1) is 2.5 horizontal periods, the second and third stages ( The combined period of P2 and P3) can be set to approximately 33 horizontal periods, and the fourth stage (P4) can be set to approximately 0.7 horizontal periods, but are not limited thereto. The combined period of the fifth and sixth stages (P5, P6) is the remaining period excluding the first to fourth stages (P1 to P4) from one frame period.

The first switch element T1 is turned on in response to the gate-on voltage VGH of the first gate signal DINIT in the first stage P1. When the first switch element T1 is turned on, the first constant voltage node PL1 to which the first reference voltage Vpre is applied is connected to the second node DTG. The first switch element T1 includes a first electrode connected to the first constant voltage node PL1, a gate electrode connected to the first gate line to which the first gate signal DINIT is applied, and a second node connected to the second node DTG. Contains 2 electrodes.

The second switch element T2 is turned on in response to the second gate signal INIT generated as the gate-on voltage VGH in the second stage P2 and the third stage P3. When the second switch element T2 is turned on, the second constant voltage node PL2 is connected to the second node DTG and the initialization voltage Vinit is applied to the second node DTG. The second switch element T2 includes a first electrode connected to the second constant voltage node PL2, a gate electrode connected to the second gate line to which the second gate signal INIT is applied, and a second electrode connected to the second node DTG. Contains 2 electrodes.

The third switch element T3 is turned on in response to the third gate signal SENSE generated as the gate-on voltage VGH in the first stage P1 and the second stage P2. When the third switch element T3 is turned on, the second reference voltage Vref is applied to the third node DTS. The third switch element T3 includes a first electrode connected to the third node DTS, a gate electrode connected to the third gate line to which the third gate signal SENSE is applied, and a gate electrode to which the second reference voltage Vref is applied. It includes a second electrode connected to the third constant voltage node PL3.

The fourth switch element T4 is turned on in response to the scan pulse of the fourth gate signal SCAN that is synchronized with the data voltage Vdata of the pixel data in the fourth step P4. Scan pulses are generated with gate-on voltage (VGH). When the first switch element T1 is turned on, the data line DL is connected to the second node DTG. Accordingly, the data voltage Vdata is applied to the second node DTG in the fourth step P4. The first switch element T1 includes a first electrode connected to the data line DL to which the data voltage Vdata is applied, a gate electrode connected to the fourth gate line to which the fourth gate signal SCAN is applied, and a second node. and a second electrode connected to (DTG).

In FIG. 2, 'DTG(@White)' refers to the second node (@White) that changes step by step in the pixel circuit in the current frame after the data voltage (Vdata) of the white grayscale value generated in the previous frame is applied to the second node (DTG). DTG) voltage. The data voltage (Vdata) of the white grayscale value is the maximum voltage in the data voltage range. In FIG. 2, 'DTG(@Black)' is a second node that changes step by step in the pixel circuit in the current frame after the data voltage (Vdata) of the black grayscale value generated in the previous frame is applied to the second node (DTG). (DTG) voltage. The data voltage (Vdata) of the black grayscale value is the minimum voltage in the data voltage range. The voltage boosting level of the second node (DTG) changes in the fifth and sixth stages depending on the voltage level of the data voltage (Vdata). As a result, when the pixel circuits are initialized, the voltage of the second node (DTG) may be affected by the previous data voltage and the deviation may increase.

In the first step (P1), the first and third switch elements (T1, T2) are turned on, while the second and fourth switch elements (T2, T4) are turned off. In the first step (P1), the driving element (DT) is turned on. In the first step (P1), since the voltage of the third node (DTS) is discharged to the second reference voltage (Vref), the light emitting element (EL) is turned off and does not emit light.

In the first stage (P1), a first constant voltage node to which a first reference voltage (Vpre) that does not affect sensing of the threshold voltage (Vth) of the driving element (DT) is applied is connected to the second node (DTG). In the first step (P1), the initialization voltage (Vinit) at the same voltage level as the first reference voltage (Vpre) may be applied to the second node (DTG). However, in this case, due to the ripple of the initialization voltage (Vinit) affected by the boosting level of the second node (DTG), the gate voltage of the driving element (DT) increases when sensing the threshold voltage of the driving element (DT). Changes may cause sensing errors.

The present invention is driven by initializing the voltage of the second node (DTG) with a separate first reference voltage (Vpre) separate from the initialization voltage (Vinit) for setting the gate voltage when sensing the threshold voltage of the driving element (DT). When sensing the device DT, the gate voltage of the driving device DT can be uniformly initialized to the initialization voltage Vinit. The boosting level of the second node (DTG) may vary due to the influence of the data voltage of the previous frame. Due to this, when the first constant voltage node PL1 is connected to the second node DTG, ripple may be generated in the first reference voltage Vpre depending on the boosting level of the second node DTG, but the driving element DT ), the voltage of the second node (DTG) may be uniformly initialized with the initialization voltage (Vinit) separated from the first reference voltage (Vpre). Ultimately, after the first reference voltage (Vpre) is applied to the second node (DTG) in all subpixels in the first step (P1), the initialization voltage (Vinit) is changed to the second reference voltage in the second step (P2). The second node (DTG) is initialized.

In the second stage P2, the second and third switch elements T2 and T3 are turned on, while the first and fourth switch elements T1 and T4 are turned off. In the second step (P2), the driving element (DT) is turned on. In the second step (P2), since the voltage of the third node (DTS) is discharged to the second reference voltage (Vref), the light emitting element (EL) is turned off and does not emit light.

In the third step (P3), the second switch element (T2) is turned on, while the first, third and fourth switch elements (T1, T3, T4) are turned off. In the third step (P3), the driving element (DT) is turned off until its gate-source voltage (Vgs) reaches the threshold voltage (Vth), and the threshold voltage (Vth) of the driving element (DT) is connected to the capacitor. (Cst) is charged. In the third step (P2), since the voltage of the third node (DTS) is discharged to the second reference voltage (Vref), the light emitting element (EL) is turned off and does not emit light. Accordingly, in the third step (P3), the threshold voltage (Vth) of the driving element (DT) is sensed. In the third step (P3), the voltage of the second node (DTG) is Vinit, and the voltage of the third node (DTS) is Vinit-Vth.

In the fourth step (P4), the fourth switch element (T4) is turned on, while the first, second and third switch elements (T1, T2, T3) are turned off. In the fourth step (P4), the voltage of the second node (DTG) changes to the data voltage (Vdata) of the current frame. In the fourth step (P4), the voltage of the third node (DTS) changes according to the mobility (μ) of the driving element (DT), so that the change or deviation in the mobility of the driving element (DT) in each subpixel is compensated. It can be. For example, when the mobility of the driving element DT is large within the preset time of the fourth stage P4, the voltage of the third node DTS increases and the gate-source voltage of the driving element DT ( Vgs) is reduced. On the other hand, when the mobility of the driving element DT is relatively small, the voltage of the third node DTS is lowered and the gate-source voltage Vgs of the driving element DT increases.

In the fifth step (P5), the first to fourth switch elements (T1 to T4) are turned off and the second and third nodes (DTG, DTS) are floating. At this time, the voltages of the second and third nodes (DTG, DTS) are boosted according to the data voltage (Vdata) compensated by the threshold voltage (Vth), and a current is sent to the light emitting device (EL) through the driving device (DT). is supplied to charge the capacitor (Cel) of the light emitting element (EL).

In the sixth step (P6), due to the current generated according to the gate-source voltage (Vgs) of the driving element (DT), the anode voltage of the light emitting element (EL) increases, thereby increasing the brightness corresponding to the grayscale value of the pixel data. The light emitting element (EL) emits light.

FIGS. 3A to 3C are diagrams showing a phenomenon in which ripple occurs in an initialization voltage in a pixel circuit of a comparative example.

3A and 3B, the pixel circuit of the comparative example includes a driving element (DT) that drives the light emitting element (EL), first to third switch elements (T01 to T03), and a capacitor (Cst). .

The switch elements (T01, T02, T03) of this pixel circuit include a first switch element (T01) that supplies an initialization voltage (Vinit) to the second node (DTG) in response to an initialization signal (INIT), and a scan signal (SCAN). ), and a second switch element (T02) that supplies the data voltage (Vdata) to the second node (DTG) in response to the ), and supplies the reference voltage (Vref) to the third node (DTS) in response to the sensing signal (SENSE). It includes a third switch element (T03). As shown in FIG. 3C, the driving period of this pixel circuit is an initialization stage (Pi) in which the pixel circuit is initialized, a sensing stage (Ps) in which the threshold voltage (Vth) of the driving element (DT) is sensed, and the data of the pixel data. It is divided into a data writing stage (Pw) in which pixel data is written into the pixel circuit by charging the voltage (Vdata), and a light emission stage after the data writing stage. In FIG. 3C, 'DTG(@White)' refers to the second node (@White) that changes step by step in the pixel circuit in the current frame after the data voltage (Vdata) of the white grayscale value generated in the previous frame is applied to the second node (DTG). DTG) voltage. 'DTG(@Black)' refers to the data voltage (Vdata) of the black gradation value generated in the previous frame being applied to the second node (DTG), and then the second node (DTG) changing step by step in the pixel circuit in the current frame. It is voltage.

After the data writing step (Pw), the voltage of the second node (DTG) is boosted, and the boosting voltage level varies depending on the voltage level of the data voltage (Vdata). For example, when the data voltage Vdata of the white grayscale value is charged in the second node DTG, the boosting voltage level of the second node DTG may be 10.9V as shown in FIG. 3A. On the other hand, when the data voltage Vdata of the black grayscale value is charged in the second node DTG, the boosting voltage level of the second node DTG may be 3.53V as shown in FIG. 3B. The initialization voltage (Vinit) may be 4.34V. When the boosting voltage of the second node (DTG) is different, the current (I) flows due to the voltage difference between the second node (DTG) and the second constant voltage node (PL2) in the initialization step (Vinit), and the current amount and current direction change. . Because of this, if there is no switch element for switching the first reference voltage (Vpre), the initialization voltage in the initialization step (Pi) is increased by the boosting voltage of the second node (DTG) boosted according to the data voltage of the previous frame, as shown in FIG. 3C. As (Vinit) changes, the gate voltage of the driving element (DT) changes. As a result, the threshold voltage (Vth) of the driving element (DT) sensed within the limited time of the sensing stage (Ps) may be inaccurate.

In the pixel circuit of the present invention, since the voltage of the second node (DTG) is initialized before the initialization step with a separate first reference voltage (Vpre) separate from the initialization voltage (Vinit), the second node (DTG) of the initialization voltage (Vinit) It does not change depending on the boosting voltage of DTG). As a result, the second node (DTG) can be uniformly initialized to the initialization voltage (Vinit) that is not affected by the previous data voltage (Vdata) in all subpixels before the threshold voltage of the driving element (DT) is sensed. there is.

Figure 4 is a plan view showing first and second power lines arranged on the display panel.

Referring to FIG. 4, the display panel 100 includes a plurality of power lines. The power lines include a first power line PL10 for supplying the first reference voltage Vpre to the subpixels, and a second power line PL20 for supplying the initialization voltage Vinit to the subpixels. .

The screen of the display panel 100 includes a pixel array in which an input image is reproduced. The pixel array may include a plurality of subpixels arranged in a matrix form. Each of the subpixels includes the pixel circuit shown in FIG. 1.

The first power line PL10 and the second power line PL20 may be wires with a mesh structure on the screen of the display panel 100. The first power line PL10 and the second power line PL20 are separated on the display panel 100 with an insulating layer therebetween. The first power line PL10 is commonly connected to the first constant voltage node PL1 of all subpixels. The second power line PL20 is commonly connected to the second constant voltage node PL2 of all subpixels.

The voltage of the first reference voltage Vpre may fluctuate due to temporary ripple generation depending on the boosting voltage level of the second node DTG where the data voltage of the previous frame is charged. Since the initialization voltage Vinit is electrically separated from the first reference voltage Vpre and must not be affected by the first reference voltage Vpre, the second power line PL20 and the first power line PL10 are insulated. It is desirable to maintain .

The constant voltage applied to the display panel 100 may vary depending on the screen position of the display panel 100 due to RC delay due to the resistance of the power line and parasitic capacitance connected to the power line. It is desirable to minimize the RC delay of the initialization voltage Vinit so that the line width W of the second power line PL20 to which the initialization voltage Vinit is applied is designed to be large across the entire screen of the display panel 100. For example, the line width W of the second power line PL20 may be greater than or equal to the line width of the first power line PL10. The line width (W) of the second power line PL20 may be 25 μm or more, for example, 25 μm to 40 μm.

In Figure 4, a chip on film (COF) is connected to the display panel 100. The chip-on-film (COF) may be connected to the output terminal connector of a printed circuit board (PCB) and adhered to the display panel 100. The drive IC mounted on chip-on-film (COF) supplies data voltage (Vdata) to data lines. In FIG. 4, “SCAN direction” is the shift direction of the scan pulse of the fourth gate signal (SCAN). The data voltage (Vdata) of pixel data is charged to the pixels of the display panel according to the scan pulse that is sequentially shifted in units of pixel lines.

Figure 5 is a block diagram showing a display device according to an embodiment of the present invention. FIG. 6 is a cross-sectional view showing the cross-sectional structure of the display panel shown in FIG. 5.

5 and 6, a display device according to an embodiment of the present invention includes a display panel 100, a display panel driver for writing pixel data to pixels of the display panel 100, and pixels. and a power supply unit 140 that generates power required to drive the display panel driver.

The display panel 100 may be a panel with a rectangular structure having a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. The display panel 100 includes a pixel array that displays an input image on a screen. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 that intersect the data lines 102, and pixels arranged in a matrix form. The display panel 100 may further include power lines commonly connected to pixels. The power lines supply the pixels 101 with a constant voltage necessary to drive the pixels 101. For example, the display panel 100 includes a power line to which a pixel driving voltage (EVDD) is applied, a power line to which a low-potential pixel base voltage (EVSS) is applied, and a power line to which a first reference voltage (Vpre) is applied (PL10). ), a power line PL20 to which the initialization voltage Vinit is applied, and a power line to which the second reference voltage Vref is applied may be disposed.

The cross-sectional structure of the display panel 100 may include a circuit layer 12, a light emitting device layer 14, and an encapsulation layer 16 stacked on the substrate 10, as shown in FIG. 15. You can.

The circuit layer 12 may include a TFT array including a pixel circuit connected to wires such as data lines, gate lines, and power lines, a demultiplexer array 112, and a gate driver 120. The pixel circuit may be implemented as the pixel circuit shown in FIG. 1. The wiring and circuit elements of the circuit layer 12 may include a plurality of insulating layers, two or more metal layers separated with the insulating layer in between, and an active layer containing a semiconductor material. All transistors formed in the circuit layer 12 can be implemented as n-channel oxide TFTs.

The light emitting device layer 14 may include a light emitting device (EL) driven by a pixel circuit. The light emitting device EL may include a red (R) light emitting device, a green (G) light emitting device, and a blue (B) light emitting device. In another embodiment, the light emitting device layer 14 may include a white light emitting device and a color filter. The light emitting elements EL of the light emitting element layer 14 may be covered with multiple protective layers including an organic layer and an inorganic layer.

The encapsulation layer 16 covers the light emitting device layer 14 to seal the circuit layer 12 and the light emitting device layer 14. The encapsulation layer 16 may have a multi-insulating film structure in which organic films and inorganic films are alternately stacked. The inorganic membrane blocks the penetration of moisture or oxygen. The organic film flattens the surface of the inorganic film. When the organic film and the inorganic film are stacked in multiple layers, the movement path of moisture or oxygen becomes longer compared to a single layer, so the penetration of moisture and oxygen affecting the light emitting device layer 14 can be effectively blocked.

A touch sensor layer (omitted from the drawing) may be formed on the encapsulation layer 16, and a polarizing plate or color filter layer may be disposed thereon. The touch sensor layer may include capacitive touch sensors that sense touch input based on changes in capacitance before and after touch input. The touch sensor layer may include metal wiring patterns and insulating films that form the capacitance of the touch sensors. The insulating films can insulate the intersections of metal wiring patterns and flatten the surface of the touch sensor layer. The polarizer can improve visibility and contrast ratio by converting the polarization of external light reflected by the metal of the touch sensor layer and circuit layer. The polarizer may be implemented as a polarizer or circular polarizer in which a linear polarizer and a phase retardation film are bonded. A cover glass may be adhered onto the polarizer. The color filter layer may include red, green, and blue color filters. The color filter layer may further include a black matrix pattern. The color filter layer absorbs part of the wavelength of light reflected from the circuit layer and the touch sensor layer, taking the role of a polarizer and increasing the color purity of the image reproduced in the pixel array.

The pixel array includes a plurality of pixel lines (L1 to Ln). Each of the pixel lines L1 to Ln includes one line of pixels arranged along the line direction (X-axis direction) in the pixel array of the display panel 100. Pixels placed in one pixel line share gate lines 103. Subpixels arranged in the column direction (Y) along the data line direction share the same data line 102. One horizontal period is the time divided by one frame period (1FR) by the total number of pixel lines (L1 to Ln).

The display panel 100 may be implemented as a non-transmissive display panel or a transmissive display panel. A transmissive display panel can be applied to a transparent display device where an image is displayed on the screen and the actual object in the background is visible. The display panel 100 may be manufactured as a flexible display panel.

Each of the pixels 101 may be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel to implement color. Each of the pixels may further include a white subpixel. Each of the subpixels may be implemented with any one of the above-described pixel circuits. Hereinafter, pixel may be interpreted in the same sense as subpixel. Each pixel circuit is connected to data lines, gate lines, and power lines.

Pixels can be arranged as real color pixels and pentile pixels. Pentile pixels can implement higher resolution than real color pixels by driving two sub-pixels of different colors into one pixel (101) using a preset pixel rendering algorithm. The pixel rendering algorithm can compensate for insufficient color expression in each pixel with the color of light emitted from adjacent pixels.

The power supply unit 140 uses a DC-DC converter to generate direct current (DC) voltage (or constant voltage) required to drive the pixel array of the display panel 100 and the display panel driver. The DC-DC converter may include a charge pump, regulator, buck converter, boost converter, etc. The power unit 140 adjusts the level of the direct current input voltage applied from a host system (not shown) to the gamma reference voltage (VGMA) and the gate-on voltage (VGH). Constant voltages such as gate-off voltage (VGL), pixel driving voltage (EVDD), pixel base voltage (EVSS), first reference voltage (Vpre), initialization voltage (Vinit), and second reference voltage (Vref) may be generated. The gamma reference voltage (VGMA) is supplied to the data driver 110. The gate-on voltage (VGH) and gate-off voltage (VGL) are supplied to the gate driver 120. Constant voltages such as the pixel driving voltage (EVDD), pixel base voltage (EVSS), first reference voltage (Vpre), initialization voltage (Vinit), and second reference voltage (Vref) are connected to the power line commonly connected to the pixels 101. It is supplied to the pixels 101 through these.

It is preferable that the first reference voltage (Vpre) and the initialization voltage (Vinit) are constant voltages of the same voltage level, but are output independently through pins of different channels in the power supply unit 140 so that they are electrically separated. For example, the power unit 140 may include a first channel through which the first reference voltage Vpre is output, and a second channel through which the initialization voltage Vinit is output, separated from the first channel.

The display panel driver writes pixel data of the input image to the pixels of the display panel 100 under the control of a timing controller 130.

The display panel driver includes a data driver 110 and a gate driver 120. The display panel driver may further include a demultiplexer array 112 disposed between the data driver 110 and the data lines 102.

The demultiplexer array 112 sequentially supplies data voltages output from channels of the data driver 110 to the data lines 102 using a plurality of de-multiplexers (DEMUX). The demultiplexer may include a plurality of switch elements disposed on the display panel 100. If the demultiplexer is disposed between the output terminals of the data driver 110 and the data lines 102, the number of channels of the data driver 110 may be reduced. Demultiplexer array 112 may be omitted.

The display panel driver may further include a touch sensor driver for driving touch sensors. The touch sensor driver is omitted in FIGS. 5 and 6. The data driver 110 and the touch sensor driver may be integrated into the drive IC (DIC) shown in FIG. 4. In a mobile device or wearable device, the timing controller 130, power supply unit 140, data driver 110, etc. may be integrated into one drive IC.

The display panel driver may operate in a low speed driving mode under the control of the timing controller 130. The low-speed driving mode can be set to analyze the input image and reduce power consumption of the display device when the input image does not change by a preset number of frames. The low-speed driving mode can reduce the power consumption of the display panel driver and the display panel 100 by lowering the frame frequency, that is, the refresh rate, at which pixel data is written to the pixels when a still image is input for more than a certain period of time. . The low-speed drive mode is not limited to when a still image is input. For example, when the display device operates in standby mode or when a user command or input image is not input to the display panel driving circuit for more than a predetermined period of time, the display panel driving circuit may operate in a low-speed driving mode.

The data driver 110 receives pixel data of an input image received as a digital signal from the timing controller 130 and outputs a data voltage. The data driver 110 generates a data voltage (Vdata) by converting pixel data of the input image into a gamma compensation voltage every frame period using a digital to analog converter (DAC). The gamma reference voltage (VGMA) is divided into a gamma compensation voltage for each gray level through a voltage divider circuit. The gamma compensation voltage for each gray level is provided to the DAC of the data driver 110. The data voltage Vdata is output from each channel of the data driver 110 through an output buffer.

The gate driver 120 may be implemented as a gate in panel (GIP) circuit formed on the circuit layer 12 on the display panel 100 along with the TFT array and wires of the pixel array. The gate driver 120 may be placed on the bezel area (BZ), which is a non-display area of the display panel 100, or may be dispersed within the pixel array where the input image is reproduced. The gate driver 120 sequentially outputs gate signals to the gate lines 103 under the control of the timing controller 130. The gate driver 120 can sequentially supply the signals to the gate lines 103 by shifting the gate signals using a shift register. The gate driver 120 includes a first shift register generating a first gate signal DINIT, a second shift register generating a second gate signal INIT, and a third shift register generating a third gate signal SENSE. , and a fourth shift register that generates a fourth gate signal (SCAN).

The timing controller 130 receives digital video data (DATA) of an input image and a timing signal synchronized therewith from the host system. The timing signal may include a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a clock (CLK), and a data enable signal (DE). Since the vertical period and horizontal period can be known by counting the data enable signal (DE), the vertical synchronization signal (Vsync) and horizontal synchronization signal (Hsync) can be omitted. The data enable signal (DE) has a period of 1 horizontal period (1H).

The host system may be any one of a television (TV) system, tablet computer, laptop computer, navigation system, personal computer (PC), home theater system, mobile device, wearable device, or vehicle system. The host system can scale the image signal from the video source to match the resolution of the display panel 100 and transmit it to the timing controller 130 along with the timing signal.

The timing controller 130 may control the operation timing of the display panel driver at a frame frequency of input frame frequency x i (i is a natural number) Hz by multiplying the input frame frequency by i times in normal driving mode. The input frame frequency is 60Hz in the NTSC (National Television Standards Committee) method and 50Hz in the PAL (Phase-Alternating Line) method.

The host system or timing controller 130 can vary the frame frequency according to the movement or content characteristics of the input image.

The timing controller 130 lowers the frame rate at which pixel data is written to pixels in the low-speed drive mode compared to the normal drive mode. For example, the frame frequency at which pixel data is written to pixels in the normal driving mode may be a frequency of 60Hz or higher, for example, 60Hz, 120Hz, 144Hz, 240Hz, etc., and the frame frequency in the low-speed driving mode is the normal driving mode. It can be set to a lower frequency than that of . The timing controller 130 may lower the driving frequency of the display panel driver by lowering the frame frequency in order to lower the refresh rate of pixels in the low-speed driving mode.

The timing controller 130 controls the data timing control signal for controlling the operation timing of the data driver 110 and the operation timing of the demultiplexer array 112 based on the timing signals (Vsync, Hsync, DE) received from the host system. A control signal for controlling the operation of the gate driver 120 and a gate timing control signal for controlling the operation timing of the gate driver 120 are generated. The timing controller 130 controls the operation timing of the display panel driver and synchronizes the data driver 110, the demultiplexer array 112, the touch sensor driver, and the gate driver 120.

The gate timing control signal generated from the timing controller 130 may be input to the shift register of the gate driver 120 through a level shifter (not shown). The level shifter can receive a gate timing control signal, generate a start pulse and a shift clock, and provide them to the shift registers of the gate driver 120.

Since the contents of the specification described in the problem to be solved, the means to solve the problem, and the effect described above do not specify the essential features of the claim, the scope of the claim is not limited by the matters described in the content of the specification.

Although embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be made without departing from the technical spirit of the present invention. . Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but are for illustrative purposes, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive. The scope of protection of the present invention should be interpreted in accordance with the claims, and all technical ideas within the equivalent scope should be interpreted as being included in the scope of rights of the present invention.

100: display panel 110: data driver
120: Gate driver 130: Timing controller
140: Power supply unit EL: Light-emitting element of the pixel circuit
DINIT: first gate signal INIT: second gate signal
SENSE: Third gate signal SCAN: Fourth gate signal
DT: Driving element of the pixel circuit Cst: Capacitor of the pixel circuit
T1~T4: Switch element of pixel circuit
P1: first stage P2: second stage
P3: Third stage P4: Fourth stage
P5: 5th stage P6: 6th stage

Claims (13)

a first electrode connected to a first node to which a pixel driving voltage is applied, a gate electrode connected to a second node, and a driving element connected to a third node to drive current to the light emitting element;
a first switch element that turns on in response to the gate-on voltage of the first gate signal generated in the first step and supplies a first reference voltage to the second node;
a second switch element that turns on in response to the gate-on voltage of the second gate signal generated in the second and third steps after the first step and supplies an initialization voltage to the second node;
a third switch element that turns on in response to the gate-on voltage of the third gate signal generated in the first and second steps and supplies a second reference voltage to the third node;
a fourth switch element that is turned on in response to the gate-on voltage of the fourth gate signal in a fourth step after the third step and supplies a data voltage to the second node; and
Includes a capacitor connected between the second node and the third node,
A pixel circuit in which a pixel base voltage is applied to a cathode electrode of the light emitting device. According to claim 1,
The pixel driving voltage is a constant voltage higher than the maximum voltage of the data voltage,
The first reference voltage and the initialization voltage are constant voltages set to a voltage between the maximum and minimum voltages of the data voltage,
The pixel base voltage is a constant voltage lower than the minimum voltage of the data voltage,
The second reference voltage is a constant voltage lower than the pixel base voltage,
The first to fourth gate signals include pulses swinging between the gate-on voltage and the gate-off voltage,
The gate-on voltage is lower than the pixel driving voltage and higher than the maximum voltage of the data voltage,
The gate-off voltage is a voltage lower than the second reference voltage,
A pixel circuit in which the first to fourth switch elements are turned off in response to a gate-off voltage. According to claim 1,
A pixel circuit wherein the first reference voltage has the same voltage level as the initialization voltage. According to claim 2,
A pixel circuit in which the voltage of the second node is boosted in the fifth step after the fourth step. According to claim 1,
The first switch element includes a first electrode connected to a first constant voltage node to which the first reference voltage is applied, a gate electrode to which the first gate signal is applied, and a second electrode connected to the second node,
The second switch element includes a first electrode connected to a second constant voltage node to which the initialization voltage is applied, a gate electrode to which the second gate signal is applied, and a second electrode connected to the second node,
The third switch element includes a first electrode connected to the third node, a gate electrode to which the third gate signal is applied, and a second electrode connected to a third constant voltage node to which the second reference voltage is applied,
The fourth switch element is a pixel circuit including a first electrode connected to a data line to which the data voltage is applied, a gate electrode to which the fourth gate signal is applied, and a second electrode connected to the second node. A display panel including a plurality of data lines, a plurality of gate lines, a plurality of power lines, and a plurality of subpixels;
a data driver that supplies data voltage to the data lines;
a gate driver that supplies gate signals to the gate lines; and
It includes a power supply unit that outputs a constant voltage applied to the power lines,
The constant voltage includes a pixel driving voltage, a pixel base voltage, a first reference voltage, an initialization voltage, and a second reference voltage,
Each of the subpixels is,
a first electrode connected to a first node to which the pixel driving voltage is applied, a gate electrode connected to a second node, and a driving element connected to a third node to drive current to the light emitting device;
a first switch element that is turned on in response to the gate-on voltage of the first gate signal generated in the first step and supplies the first reference voltage to the second node;
a second switch element that turns on in response to the gate-on voltage of the second gate signal generated in the second and third steps after the first step and supplies the initialization voltage to the second node;
a third switch element that is turned on in response to the gate-on voltage of the third gate signal generated in the first and second steps and supplies the second reference voltage to the third node;
a fourth switch element that is turned on in response to the gate-on voltage of the fourth gate signal in a fourth step after the third step and supplies the data voltage to the second node; and
Includes a capacitor connected between the second node and the third node,
A display device in which the pixel base voltage is applied to a cathode electrode of the light emitting device. According to claim 6,
The pixel driving voltage is a constant voltage higher than the maximum voltage of the data voltage,
The first reference voltage and the initialization voltage are constant voltages set to a voltage between the maximum and minimum voltages of the data voltage,
The pixel base voltage is a constant voltage lower than the minimum voltage of the data voltage,
The second reference voltage is a constant voltage lower than the pixel base voltage,
The first to fourth gate signals include pulses swinging between the gate-on voltage and the gate-off voltage,
The gate-on voltage is lower than the pixel driving voltage and higher than the maximum voltage of the data voltage,
The gate-off voltage is a voltage lower than the second reference voltage,
A display device in which the first to fourth switch elements are turned off in response to a gate-off voltage. According to claim 6,
The first reference voltage has the same voltage level as the initialization voltage. According to claim 7,
The first switch element includes a first electrode connected to a first constant voltage node to which the first reference voltage is applied, a gate electrode to which the first gate signal is applied, and a second electrode connected to the second node,
The second switch element includes a first electrode connected to a second constant voltage node to which the initialization voltage is applied, a gate electrode to which the second gate signal is applied, and a second electrode connected to the second node,
The third switch element includes a first electrode connected to the third node, a gate electrode to which the third gate signal is applied, and a second electrode connected to a third constant voltage node to which the second reference voltage is applied,
The fourth switch element includes a first electrode connected to a data line to which the data voltage is applied, a gate electrode to which the fourth gate signal is applied, and a second electrode connected to the second node. According to clause 9,
The display panel is,
a first power line to which the first reference voltage is applied and connected to first constant voltage nodes of the subpixels; and
a second power line to which the second reference voltage is applied and connected to second constant voltage nodes of the subpixels;
A display device in which the first power line and the second power line are separated and insulated from each other with an insulating layer therebetween. According to claim 10,
A display device wherein the line width of the second power line is greater than or equal to the line width of the first power line. According to claim 11,
A display device wherein the second power line has a line width between 25μm and 40μm. According to claim 6,
The power supply unit,
a first channel through which the first reference voltage is output; and
A display device outputting the initialization voltage and including a second channel separated from the first channel.