KR20240104918A - Display panel and display device - Google Patents

Abstract

Embodiments of the present disclosure relate to display panels and display devices, and more specifically, to a first active layer and a second active layer, a gate insulating film disposed on the first and second active layers, and a gate insulating film disposed on the gate insulating film. , a first gate electrode disposed on the first active layer, a second gate electrode disposed on the second active layer, a first source electrode and a first drain electrode disposed on the second gate electrode, and a second active layer. a second source electrode and a second drain electrode electrically connected to the layer, a first passivation layer disposed on the first source electrode, a first drain electrode, a second source electrode, and a second drain electrode, and a first passivation layer disposed on the first passivation layer. A display panel and a display device that can improve the electrical characteristics of a transistor can be provided by including a blocking layer, where the blocking layer overlaps the entire first active layer and a portion of the second active layer.

Description

Display panel and display device {DISPLAY PANEL AND DISPLAY DEVICE}

Embodiments of the present disclosure relate to display panels and display devices.

Thin film transistors are widely used as switching devices or driving devices in the electronic device field.

In particular, since thin film transistors can be manufactured on glass or plastic substrates, they can be driven in display devices such as liquid crystal display devices or organic light emitting display devices. It is widely used as a device or switching device.

However, at least some of the devices used in the display panel have characteristics that are sensitive to light or hydrogen, which causes a problem in that the electrical characteristics of the devices change.

Embodiments of the present disclosure relate to a display panel and a display device having a structure in which a blocking layer overlapping a transistor is disposed so that the amount of light and hydrogen incident on the transistor can be adjusted depending on the type of transistor.

Embodiments of the present disclosure relate to a display panel and a display device that can improve the electrical characteristics of a driving transistor and the reliability of a scan transistor through a blocking layer disposed on at least some of the transistors.

Embodiments of the present disclosure include a first active layer and a second active layer disposed on a substrate, a gate insulating film disposed on the first and second active layers, a gate insulating film, and a first active layer. A second gate electrode disposed on the first gate electrode and the second active layer, an interlayer insulating film disposed on the first and second gate electrodes, and a second gate electrode disposed on the interlayer insulating film and spaced apart from each other, but electrically connected to the first active layer. 1 A source electrode and a first drain electrode, a second source electrode and a second drain electrode electrically connected to the second active layer, disposed on the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode A display panel may be provided including a first passivation layer and a blocking layer disposed on the first passivation layer, wherein the blocking layer overlaps the entire first active layer and a portion of the second active layer.

Embodiments of the present disclosure are disposed on a substrate and include a first active layer, a first gate electrode disposed on the first active layer, a first source electrode and a first drain electrode disposed on the first gate electrode. 1 transistor, a second gate electrode disposed under the first active layer of the first transistor, a second active layer disposed under the second gate electrode, and a second disposed on the same layer as the first source electrode and the first drain electrode. A display device may be provided including a second transistor including a source electrode and a second drain electrode, and a blocking layer overlapping with the entire first active layer of the first transistor, wherein the blocking layer does not overlap the second transistor. .

According to embodiments of the present disclosure, a display panel and a display device having a structure in which a blocking layer overlapping a transistor is disposed so that the amount of light and hydrogen incident on the transistor can be adjusted depending on the type of transistor can be provided.

According to embodiments of the present disclosure, a display panel and display device having high efficiency and long lifespan are provided by improving the electrical characteristics of the driving transistor and improving the reliability of the scan transistor through a blocking layer disposed on at least some of the transistors. can do.

1 is a system configuration diagram of a display device according to embodiments of the present disclosure.
2 is an equivalent circuit of a subpixel of a display device according to embodiments of the present disclosure.
3 is another equivalent circuit of a subpixel of a display device according to embodiments of the present disclosure.
FIG. 4 is a diagram illustrating a light shield within a subpixel of a display device according to embodiments of the present disclosure.
FIG. 5 is a plan view illustrating the structure of one subpixel disposed in the display area of a display panel according to embodiments of the present disclosure.
Figure 6 is a plan view schematically showing a structure in which a first transistor and a blocking layer overlap.
Figure 7 is a plan view schematically showing a structure in which a second transistor and a blocking layer overlap.
Figure 8 is a plan view schematically showing a structure in which a fourth transistor and a blocking layer overlap.
FIG. 9 is a diagram showing how the threshold voltage (Vth) value of a transistor changes depending on the ratio of the overlapping area between the open area of the transistor and the blocking layer.
Figure 10 is a diagram showing the VGS and IDS curves of the transistor according to the ratio of the overlapping area between the open area of the transistor and the blocking layer.
FIG. 11 is a diagram illustrating the structures of a cross section taken along AB in FIG. 6, a cross section cut along CD in FIG. 7, and a cross section cut along EF in FIG. 8.
FIG. 12 is a diagram illustrating a cross-sectional structure of a display panel according to embodiments of the present disclosure.
FIG. 13 is a diagram illustrating a cross-sectional structure of a display area of a display panel according to embodiments of the present disclosure.
FIG. 14 is a diagram illustrating a cross-sectional structure of a display panel according to embodiments of the present disclosure.

Hereinafter, some embodiments of the present disclosure will be described in detail with reference to illustrative drawings. In adding reference numerals to components in each drawing, identical components may have the same reference numerals as much as possible even if they are shown in different drawings. Additionally, in describing the present disclosure, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present disclosure, the detailed description may be omitted. When “comprises,” “has,” “consists of,” etc. mentioned in the specification are used, other parts may be added unless “only” is used. When a component is expressed in the singular, it can also include the plural, unless specifically stated otherwise.

Additionally, in describing the components of the present disclosure, terms such as first, second, A, B, (a), and (b) may be used. These terms are only used to distinguish the component from other components, and the nature, sequence, order, or number of the components are not limited by the term.

In the description of the positional relationship of components, when two or more components are described as being “connected,” “coupled,” or “connected,” the two or more components are directly “connected,” “coupled,” or “connected.” ", but it should be understood that two or more components and other components may be further "interposed" and "connected," "combined," or "connected." Here, other components may be included in one or more of two or more components that are “connected,” “coupled,” or “connected” to each other.

In the explanation of temporal flow relationships related to components, operation methods, production methods, etc., for example, temporal precedence relationships such as “after”, “after”, “after”, “before”, etc. Or, when a sequential relationship is described, non-continuous cases may be included unless “immediately” or “directly” is used.

On the other hand, when a numerical value or corresponding information (e.g. level, etc.) for a component is mentioned, even if there is no separate explicit description, the numerical value or corresponding information is related to various factors (e.g. process factors, internal or external shocks, It can be interpreted as including the error range that may occur due to noise, etc.).

Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the attached drawings.

1 is a system configuration diagram of a display device 100 according to embodiments of the present disclosure.

Referring to FIG. 1 , a display device 100 according to embodiments of the present disclosure may include a display panel 110 and a driving circuit for driving the display panel 110 .

The driving circuit may include a data driving circuit 120 and a gate driving circuit 130, and may further include a controller 140 that controls the data driving circuit 120 and the gate driving circuit 130.

The display panel 110 may include a substrate SUB and signal wires such as a plurality of data lines DL and a plurality of gate lines GL disposed on the substrate SUB. The display panel 110 may include a plurality of subpixels (SP) connected to a plurality of data lines (DL) and a plurality of gate lines (GL).

The display panel 110 may include a display area DA where an image is displayed and a non-display area NDA where an image is not displayed and is located outside the display area DA. In the display panel 110, a plurality of subpixels (SP) for displaying an image are disposed in the display area (DA), and the driving circuits 120, 130, and 140 are electrically connected to the non-display area (NDA). The driving circuits 120, 130, and 140 may be connected or mounted, and a pad portion to which an integrated circuit or printed circuit, etc., may be connected may be disposed.

The data driving circuit 120 is a circuit for driving a plurality of data lines DL and can supply data signals to the plurality of data lines DL. The gate driving circuit 130 is a circuit for driving a plurality of gate lines GL and can supply gate signals to the plurality of gate lines GL. The controller 140 may supply a data control signal (DCS) to the data driving circuit 120 to control the operation timing of the data driving circuit 120. The controller 140 may supply a gate control signal (GCS) to the gate driving circuit 130 to control the operation timing of the gate driving circuit 130 .

The controller 140 controls the scanning operation to start according to the timing implemented in each frame, and converts the input image data input from the outside to fit the data signal format used in the data driving circuit 120 to produce the converted image data. (Data) can be supplied to the data driving circuit 120, and data driving can be controlled to proceed at an appropriate time according to the scanning timing.

The controller 140 uses a gate start pulse (GSP: Gate Start Pulse), a gate shift clock (GSC), and a gate output enable signal (GOE: Gate Output Enable signal) to control the gate driving circuit 130. ) can output various gate control signals (GCS: Gate Control Signal), etc.

The controller 140 uses a source start pulse (SSP), a source sampling clock (SSC), and a source output enable signal (SOE) to control the data driving circuit 120. ) can output various data control signals (DCS: Data Control Signal), etc.

The controller 140 may be implemented as a separate component from the data driving circuit 120, or may be integrated with the data driving circuit 120 and implemented as an integrated circuit.

The data driving circuit 120 receives image data Data from the controller 140 and supplies a data voltage to the plurality of data lines DL, thereby driving the plurality of data lines DL. Here, the data driving circuit 120 is also called a source driving circuit.

This data driving circuit 120 may include one or more source driver integrated circuits (SDIC).

For example, each source driver integrated circuit (SDIC) is connected to the display panel 110 using Tape Automated Bonding (TAB), Chip On Glass (COG), or Chip On Panel ( It may be connected to the bonding pad of the display panel 110 using a COP (Chip On Panel) method, or may be implemented using a Chip On Film (COF) method and connected to the display panel 110.

The gate driving circuit 130 may output a gate signal of a turn-on level voltage or a gate signal of a turn-off level voltage according to the control of the controller 140. The gate driving circuit 130 may sequentially drive a plurality of gate lines GL by sequentially supplying a gate signal with a turn-on level voltage to the plurality of gate lines GL.

The gate driving circuit 130 is connected to the display panel 110 using a tape automated bonding (TAB) method, or is connected to a bonding pad of the display panel 110 using a chip on glass (COG) or chip on panel (COP) method. Pad) or may be connected to the display panel 110 according to the chip-on-film (COF) method. Alternatively, the gate driving circuit 130 may be a gate in panel (GIP) type and may be formed in the non-display area NDA of the display panel 110. The gate driving circuit 130 may be disposed on or connected to the substrate SUB. That is, if the gate driving circuit 130 is a GIP type, it may be disposed in the non-display area NDA of the substrate SUB. The gate driving circuit 130 may be connected to the substrate SUB in the case of a chip-on-glass (COG) type, chip-on-film (COF) type, etc.

Meanwhile, at least one of the data driving circuit 120 and the gate driving circuit 130 may be disposed in the display area DA. For example, at least one of the data driving circuit 120 and the gate driving circuit 130 may be arranged not to overlap the subpixels SP, and may be partially or entirely aligned with the subpixels SP. They may also be placed overlapping.

When a specific gate line (GL) is opened by the gate driving circuit 130, the data driving circuit 120 converts the image data (Data) received from the controller 140 into an analog data voltage to generate a plurality of data lines. It can be supplied as (DL).

The data driving circuit 120 may be connected to one side (eg, the upper or lower side) of the display panel 110. Depending on the driving method, panel design method, etc., the data driving circuit 120 may be connected to both sides (e.g., upper and lower sides) of the display panel 110, or may be connected to two or more of the four sides of the display panel 110. It may be possible.

The gate driving circuit 130 may be connected to one side (eg, left or right) of the display panel 110. Depending on the driving method, panel design method, etc., the gate driving circuit 130 may be connected to both sides (e.g., left and right) of the display panel 110, or may be connected to two or more of the four sides of the display panel 110. It may be possible.

The controller 140 may be a timing controller used in typical display technology, or a control device that can further perform other control functions, including a timing controller, and may be a control device different from the timing controller. It may be a circuit within the control device. The controller 140 may be implemented with various circuits or electronic components, such as an Integrated Circuit (IC), Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit (ASIC), or Processor.

The controller 140 may be mounted on a printed circuit board, a flexible printed circuit, etc., and may be electrically connected to the data driving circuit 120 and the gate driving circuit 130 through a printed circuit board, a flexible printed circuit, etc.

The display device 100 according to embodiments of the present disclosure may be a display including a back light unit such as a liquid crystal display, an Organic Light Emitting Diode (OLED) display, a quantum dot display, or a micro LED ( It may be a self-luminous display such as a Micro Light Emitting Diode (Micro Light Emitting Diode) display.

When the display device 100 according to embodiments of the present disclosure is an OLED display, each subpixel (SP) may include an organic light emitting diode (OLED) that emits light as a light emitting device. When the display device 100 according to embodiments of the present disclosure is a quantum dot display, each subpixel SP may include a light emitting device made of quantum dots, which are semiconductor crystals that emit light on their own. When the display device 100 according to embodiments of the present disclosure is a micro LED display, each subpixel (SP) emits light on its own and may include a micro LED (Micro Light Emitting Diode) made of an inorganic material as a light emitting element. there is.

2 is an equivalent circuit of a subpixel (SP) of the display device 100 according to embodiments of the present disclosure, and FIG. 3 is another equivalent circuit of the subpixel (SP) of the display device 100 according to embodiments of the present disclosure. It is a circuit.

Referring to FIG. 2, each of the plurality of subpixels (SP) disposed on the display panel 110 of the display device 100 according to embodiments of the present disclosure includes a light emitting element (ED), a driving transistor (DRT), and a scanning transistor. (SCT) and a storage capacitor (Cst).

Referring to FIG. 2, the light emitting element (ED) includes a pixel electrode (PE) and a common electrode (CE), and may include a light emitting layer (EL) located between the pixel electrode (PE) and the common electrode (CE). there is.

The pixel electrode PE of the light emitting element ED may be an electrode disposed in each subpixel SP, and the common electrode CE may be an electrode commonly disposed in all subpixels SP. Here, the pixel electrode (PE) may be an anode electrode and the common electrode (CE) may be a cathode electrode. Conversely, the pixel electrode (PE) may be a cathode electrode and the common electrode (CE) may be an anode electrode.

For example, the light emitting device (ED) may be an organic light emitting diode (OLED), a light emitting diode (LED), or a quantum dot light emitting device.

The driving transistor DRT is a transistor for driving the light emitting device ED, and may include a first node N1, a second node N2, and a third node N3.

The first node (N1) of the driving transistor (DRT) may be a source node (source electrode) or a drain node (drain electrode) of the driving transistor (DRT), and may also be electrically connected to the pixel electrode (PE) of the light emitting element (ED). can be connected The second node (N2) of the driving transistor (DRT) may be the drain node (drain electrode) or the source node (source electrode) of the driving transistor (DRT), and the driving voltage line (DVL) that supplies the driving voltage (EVDD). can be electrically connected to. The third node N3 of the driving transistor DRT may be a gate node (gate electrode) of the driving transistor DRT and may be electrically connected to the source node or drain node of the scanning transistor SCT.

The scanning transistor (SCT) is controlled by the scanning gate signal (SCAN), which is a type of gate signal, and may be connected between the third node (N3) of the driving transistor (DRT) and the data line (DL). In other words, the scanning transistor (SCT) is turned on or off according to the scanning gate signal (SCAN) supplied from the scanning gate line (SCL), which is a type of gate line (GL), and the data line (DL) The connection between the third node N3 and the driving transistor DRT can be controlled.

The scanning transistor (SCT) is turned on by the scanning gate signal (SCAN) having a turn-on level voltage, and transmits the data voltage (Vdata) supplied from the data line (DL) to the third node of the driving transistor (DRT). You can forward it to (N3).

Here, when the scanning transistor (SCT) is an n-type transistor, the turn-on level voltage of the scanning gate signal (SCAN) may be a high level voltage. When the scanning transistor (SCT) is a p-type transistor, the turn-on level voltage of the scanning gate signal (SCAN) may be a low level voltage.

The storage capacitor Cst may be connected between the third node N3 and the first node N1 of the driving transistor DRT. The storage capacitor (Cst) is charged with a charge corresponding to the voltage difference between both ends and plays the role of maintaining the voltage difference between both ends for a set frame time. Accordingly, the corresponding subpixel SP may emit light during a set frame time.

Referring to FIG. 3 , each of the plurality of subpixels SP disposed on the display panel 110 of the display device 100 according to embodiments of the present disclosure may further include a sensing transistor (SENT).

The sensing transistor (SENT) is controlled by the sensing gate signal (SENSE), which is a type of gate signal, and may be connected between the first node (N1) of the driving transistor (DRT) and the reference voltage line (RVL). In other words, the sensing transistor (SENT) is turned on or turned off according to the sensing gate signal (SENSE) supplied from the sensing gate line (SENL), which is another type of gate line (GL), to generate the reference voltage line ( The connection between RVL) and the first node (N1) of the driving transistor (DRT) can be controlled.

The sensing transistor (SENT) is turned on by the sensing gate signal (SENSE) having a turn-on level voltage, and applies the reference voltage (Vref) supplied from the reference voltage line (RVL) to the first voltage of the driving transistor (DRT). It can be delivered to node (N1).

In addition, the sensing transistor (SENT) is turned on by the sensing gate signal (SENSE) having a turn-on level voltage, so that the voltage of the first node (N1) of the driving transistor (DRT) is connected to the reference voltage line (RVL). It can be delivered to .

Here, when the sensing transistor SENT is an n-type transistor, the turn-on level voltage of the sensing gate signal SENSE may be a high level voltage. When the sensing transistor SENT is a p-type transistor, the turn-on level voltage of the sensing gate signal SENSE may be a low level voltage.

The function of the sensing transistor (SENT) to transfer the voltage of the first node (N1) of the driving transistor (DRT) to the reference voltage line (RVL) can be used when driving to sense the characteristic value of the subpixel (SP). In this case, the voltage transmitted to the reference voltage line RVL may be a voltage for calculating the characteristic value of the subpixel SP or a voltage reflecting the characteristic value of the subpixel SP.

Each of the driving transistor (DRT), scanning transistor (SCT), and sensing transistor (SENT) may be an n-type transistor or a p-type transistor. In this disclosure, for convenience of explanation, the driving transistor (DRT), scanning transistor (SCT), and sensing transistor (SENT) are each n-type.

The storage capacitor (Cst) is not a parasitic capacitor (e.g. Cgs, Cgd), which is an internal capacitor that exists between the gate node and the source node (or drain node) of the driving transistor (DRT). ) may be an external capacitor intentionally designed outside of the capacitor.

The scanning gate line (SCL) and the sensing gate line (SENL) may be different gate lines (GL). In this case, the scanning gate signal (SCAN) and the sensing gate signal (SENSE) may be separate gate signals, and the on-off timing of the scanning transistor (SCT) in one subpixel (SP) and the sensing transistor (SENT) may be different from each other. On-off timing may be independent. That is, the on-off timing of the scanning transistor (SCT) and the on-off timing of the sensing transistor (SENT) within one subpixel (SP) may be the same or different.

Alternatively, the scanning gate line (SCL) and the sensing gate line (SENL) may be the same gate line (GL). That is, the gate node of the scanning transistor (SCT) and the gate node of the sensing transistor (SENT) within one subpixel (SP) may be connected to one gate line (GL). In this case, the scanning gate signal (SCAN) and the sensing gate signal (SENSE) may be the same gate signal, and the on-off timing of the scanning transistor (SCT) in one subpixel (SP) and the on-off timing of the sensing transistor (SENT) may be the same. The off timing may be the same.

The structure of the subpixel SP shown in FIGS. 2 and 3 is only an example and may be modified in various ways by including one or more transistors or one or more capacitors.

In addition, in FIGS. 2 and 3, the subpixel structure is explained assuming that the display device 100 is a self-luminous display device. However, when the display device 100 is a liquid crystal display device, each subpixel SP is a transistor. and pixel electrodes.

FIG. 4 is a diagram illustrating a light shield (LS) within a subpixel (SP) of the display device 100 according to embodiments of the present disclosure.

Referring to FIG. 4 , in the subpixel SP of the display device 100 according to embodiments of the present disclosure, the driving transistor DRT may have unique characteristics such as threshold voltage and mobility. When the intrinsic characteristics of the driving transistor (DRT) change, the current driving ability (current supply performance) of the driving transistor (DRT) changes, and the light emission characteristics of the corresponding subpixel (SP) may also change.

The device characteristics (e.g., threshold voltage, mobility, etc.) of the driving transistor (DRT) may change as the driving time of the driving transistor (DRT) passes. In addition, when light is irradiated to the driving transistor (DRT), especially when light is irradiated to the channel region of the driving transistor (DRT), the device characteristics (e.g., threshold voltage, mobility, etc.) of the driving transistor (DRT) may change. It may change.

Therefore, as shown in FIG. 4, in order to reduce changes in device characteristics (e.g., threshold voltage change, mobility change, etc.) of the driving transistor (DRT), a light shield (LS) is installed near the driving transistor (DRT). may be formed. For example, the light shield LS may be formed under the channel region of the driving transistor DRT.

Meanwhile, in addition to blocking light, the light shield LS may be formed under the channel region of the driving transistor DRT and serve as a body of the driving transistor DRT.

A body effect may occur in the driving transistor (DRT). In order to reduce the influence of this body effect, the light shield (LS), which serves as the body of the driving transistor (DRT), It may be electrically connected to the first node (N1). Here, the first node N1 of the driving transistor DRT may be a source node of the driving transistor DRT.

Meanwhile, the light shield LS may be disposed not only under the channel region of the driving transistor DRT, but also under the channel region of other transistors (eg, SCT, SENT).

In the display area DA of the display panel 110 according to embodiments of the present disclosure, transistors DRT, SCT, and SENT may be disposed for each subpixel SP. When the gate driving circuit 130 is formed as a GIP (Gate In Panel) type in the non-display area (NDA) of the display panel 110 according to embodiments of the present disclosure, the GIP type gate driving circuit 130 A plurality of transistors may be disposed in the non-display area NDA of the display panel 110.

FIG. 5 is a plan view illustrating the structure of one subpixel SP disposed in the display area DA of the display panel 110 according to embodiments of the present disclosure.

Referring to FIG. 5 , the subpixel SP of the display panel 110 according to embodiments of the present disclosure may include an emission area EA and a non-emission area that is an area other than the emission area EA.

The light emitting area EA is an area corresponding to the opening of the bank BK, and may be an area where the anode electrode PE overlaps the opening of the bank BK.

A circuit unit for driving a light-emitting device disposed in the light-emitting area EA may be disposed in the non-emission area NEA.

The circuit unit may include a plurality of signal lines (511, 512, 513, 514, 515, 516, 517), a plurality of transistors (T1, T2, T3), and a storage capacitor (Cst).

Specifically, the display panel 110 includes a first signal line 511, a second signal line 512, and a third signal line 513 extending in a first direction, and having a direction intersecting the first direction. It may include a fourth signal line 514 and a fifth signal line 515 extending in the second direction.

Here, the first signal line 511 may be a driving voltage line, the second signal line 512 may be a data line, the third signal line 513 may be a reference voltage line, and the fourth and fifth signal lines ( 514 and 515) may be scan lines, but embodiments of the present disclosure are not limited thereto.

Additionally, referring to FIG. 5 , the display panel 110 according to embodiments of the present disclosure may include a first extension line 516 and a second extension line 517, at least a portion of which extends in a second direction. . The first extension line 516 may be a signal line electrically connected to the first signal line 511, and the second extension line 517 may be a signal line electrically connected to the third signal line.

A first transistor (T1), a second transistor (T2), a third transistor (T3), and a storage capacitor (Cst) may be disposed in the circuit part of the subpixel SP.

In FIG. 5, the first transistor T1 may be a driving transistor (DRT), the second transistor T2 may be a scan transistor (SCAN), and the third transistor T3 may be a sense transistor.

Referring to FIG. 5 , the first transistor T1 may include a first active layer ACT1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1.

Referring to FIG. 5 , the first source electrode S1 may have the same configuration as the first extension line 516, but embodiments of the present disclosure are not limited thereto.

Additionally, referring to FIG. 5 , a light shield LS that overlaps the channel area of the first active layer ACT1 may be disposed below the first active layer ACT1.

The second transistor T2 may include a second active layer ACT2, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2.

The second gate electrode (G2) may have the same configuration as the fourth signal line 514, and the second source electrode (S1) may be integral with the first gate electrode (G1). However, in an embodiment of the present disclosure They are not limited to this.

The third transistor T3 may include a third active layer ACT3, a third gate electrode G3, a third source electrode S3, and a third drain electrode D3.

The third gate electrode G3 may have the same configuration as the fifth signal line 514, and the third drain electrode D3 may have the same configuration as the second extension line 517. However, embodiments of the present disclosure It is not limited to this.

Referring to FIG. 5 , each of the first transistor T1, the second transistor T2, and the third transistor T3 may overlap the blocking layer 520.

Additionally, referring to FIG. 5, the storage capacitor Cst may include a plurality of storage capacitor electrodes, and the light shield LS, the first active layer ACT1, and the blocking layer 520 each overlap to form the storage capacitor. It can act as an electrode.

The blocking layer 520 according to embodiments of the present disclosure may include a metal material. For example, the blocking layer 520 includes aluminum (Al), gold (Au), silver (Ag), copper (Cu), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta), It may include a metal such as titanium (Ti) or an alloy thereof.

This blocking layer 520 can prevent light and hydrogen (H) from being incident on the active layer of a plurality of transistors disposed in the display panel 110, thereby preventing changes in the threshold voltage characteristics of the transistors.

At least one active layer among the active layers of the plurality of transistors disposed in the display panel 110 according to embodiments of the present disclosure may include an oxide semiconductor material. An oxide semiconductor material is a semiconductor material whose conductivity is controlled and the band gap is adjusted by doping the oxide material, and may generally be a transparent semiconductor material with a wide band gap. For example, oxide semiconductor materials include IGZO (Indium gallium zinc oxide), ZnO (zinc oxide), IGO (Indium Gallium Oxide), IZO (Indium Zinc Oxide), CdO (cadmium oxide), InO (indium oxide), ZTO ( It may include zinc tin oxide), ZITO (zinc indium tin oxide), IGZTO (Indium gallium zinc tin oxide), etc.

For example, the first to third active layers (ACT1, ACT2, and ACT3) may include an oxide semiconductor material, and the transistor including the first to third active layers (ACT1, ACT2, and ACT3) may be an oxide thin film. It can be called a transistor (oxide thin film transistor).

At least one of the first transistor (T1), the second transistor (T2), and the third transistor (T3) has a different area overlapping with the blocking layer 520, and the remaining two transistors overlap with the blocking layer 520. It may be different from the area.

For example, as shown in FIG. 5, the area where the first transistor (T1) overlaps the blocking layer 520 is the area where the second and third transistors (T2 and T3) each overlap with the blocking layer 520. It can be larger than the area.

In other words, transistors disposed in the display panel 110 according to embodiments of the present disclosure may have different areas overlapping with the blocking layer 520 depending on the type.

The first transistor in FIG. 5 may be a driving transistor (DRT) disposed in the display area DA, the second transistor T2 may be a scan transistor (SCAN) disposed in the display area DA, and the third transistor T2 may be a scan transistor (SCAN) disposed in the display area DA. The transistor T3 may be a sense transistor SENSE disposed in the display area DA.

In addition, although not shown in FIG. 5, a number of transistors may be disposed in the non-display area NDA of FIG. 1.

For example, a plurality of fourth transistors may be disposed in the area where the gate driving circuit of the non-display area NDA is disposed, and the plurality of fourth transistors may also overlap the blocking layer.

Refer to FIGS. 6 to 8 for a structure in which each of the first to third transistors T1, T2, and T3 disposed in the display area DA and the fourth transistor disposed in the non-display area NDA overlaps a blocking layer. After reviewing, it is as follows.

FIG. 6 is a plan view schematically showing a structure in which a first transistor and a blocking layer overlap, FIG. 7 is a plan view schematically showing a structure in which a second transistor and a blocking layer overlap, and FIG. 8 is a plan view schematically showing a structure in which a second transistor and a blocking layer overlap. This is a plan view schematically showing the structure with overlapping blocking layers.

In addition, although the arrangement relationship between the second transistor T2 and the blocking layer 520 is shown in FIG. 7, the arrangement relationship between the third transistor T3 and the blocking layer 520 is similar to that of the second transistor T2 shown in FIG. ) may be the same as the arrangement relationship between the blocking layer 520. Accordingly, the following description will focus on the arrangement relationship between the second transistor T2 and the blocking layer 520.

Referring to FIGS. 6 to 8 , the area where the first transistor (T1) and the blocking layer 520 overlap each other are the area where the second transistor (T2) and the blocking layer 520 overlap each other, and the area where the fourth transistor (T2) overlaps. The area where (T4) and the blocking layer 520 overlap each other may be larger.

Specifically, referring to FIGS. 6 to 8, the area where the first active layer ACT1 of the first transistor T1 overlaps the blocking layer 520 is the second active layer (ACT1) of the second transistor T2. The area where ACT2) overlaps with the blocking layer 520 may be larger than the area where the fourth active layer (ACT4) of the fourth transistor (T4) overlaps with the blocking layer 520.

In addition, the area where the fourth active layer (ACT4) of the fourth transistor (T4) of FIG. 8 overlaps with the blocking layer 520 is the area where the second active layer (ACT2) of the second transistor (T2) of FIG. 7 is blocked. It may be larger than the area overlapping with the layer 520.

Here, the area where the first active layer (ACT1) and the blocking layer 520 overlap each other is another configuration of the first transistor (T1) between the first active layer (ACT1) and the blocking layer 520 (e.g., the first It may include a region where the gate electrode (G1), the first source electrode (S1), and the first drain electrode (D1) are disposed and the first active layer (ACT1) and the blocking layer 520 overlap.

The area where the second active layer (ACT2) and the blocking layer 520 overlap each other is another configuration of the second transistor (T2) between the second active layer (ACT2) and the blocking layer 520 (e.g., the second gate electrode). (G2), the second source electrode (S2), and the second drain electrode (D2) may include a region where the second active layer (ACT2) and the blocking layer 520 overlap.

The area where the fourth active layer (ACT4) and the blocking layer 520 overlap each other is another configuration of the fourth transistor (T4) between the fourth active layer (ACT4) and the blocking layer 520 (e.g., the fourth gate electrode). (G4), the fourth source electrode (S4), and the fourth drain electrode (D4) may include a region where the fourth active layer ACT42 and the blocking layer 520 overlap.

The blocking layer 520 may serve to prevent light from entering or hydrogen penetrating into the active layers (ACT1, ACT2, and ACT4).

Meanwhile, when a change (Vth shift) in the threshold voltage of the first transistor T1, which is a driving transistor among the plurality of transistors disposed in the display panel 110, occurs, the light emitting device electrically connected to the first transistor T1 Since the current applied to changes, it may be important to ensure that the threshold voltage of the first transistor T1 does not change.

As shown in FIGS. 6 to 8, since the area where the first active layer (ACT1) overlaps the blocking layer (520) is the largest, the amount of light incident on the first active layer (ACT1) and the amount of hydrogen penetrating are It may be less than the 2nd and 4th active layers (ACT2, ACT4). Through this, it is possible to prevent the threshold voltage of the first transistor T1 from changing due to light or hydrogen.

In addition, since the fourth transistor (T4) is a transistor that is more sensitive to changes in threshold voltage than the second transistor (T2), the area where the fourth active layer (ACT4) overlaps the blocking layer 520 is the second active layer (ACT2). ) may be larger than the area overlapping with the blocking layer 520.

The second transistor T2 may not be significantly affected by changes in threshold voltage compared to the first transistor T1 and the fourth transistor T4. Although not shown in the drawing, the third transistor T3 may also be less affected by changes in threshold voltage than the first and fourth transistors T1 and T4.

On the other hand, if too much hydrogen flows into the oxide semiconductor material, there is a problem that the threshold voltage changes. However, if it flows in an appropriate amount, the reliability of the transistor can be improved by protecting (passivation) defects in the oxide semiconductor material. there is.

Referring to FIGS. 6 to 8, the second active layer ACT2 has a smaller area overlapping with the blocking layer 520 than the first and fourth active layers ACT1 and ACT4, so the first and fourth active layers ACT2 The amount of hydrogen inflow may be greater than that of the layers (ACT1, ACT4).

However, as mentioned earlier, if too much hydrogen flows into the second active layer (ACT2), the threshold voltage changes over a large range, which may cause problems with the reliability of the second transistor (T2). , a portion of the second active layer (ACT2) may also overlap the blocking layer 520.

In addition, since the first transistor T1 including the first active layer ACT1 is a transistor directly related to the driving current of the light emitting device, the first active layer ACT1 must be maintained without changing the threshold voltage. It can be designed to block hydrogen inflow.

Additionally, referring to FIGS. 6 to 8 , the first gate electrode G1 of the first transistor T1, the second gate electrode G2 of the second transistor T2, and the fourth electrode of the fourth transistor T4 At least a portion of each gate electrode G4 may overlap the blocking layer 520 .

6 to 8, the area where the first gate electrode G1 of the first transistor T1 overlaps the blocking layer 520 is the area of the second gate electrode G2 of the second transistor T2. The area overlapping with the blocking layer 520 and the fourth gate electrode G4 of the fourth transistor T4 may be larger than the area overlapping with the blocking layer 520 .

Additionally, each of the second gate electrode G2 of the second transistor T2 and the fourth gate electrode G4 of the fourth transistor T4 may not overlap the blocking layer 520 .

As the area where the gate electrode overlaps with the blocking layer 520 containing metal increases, the RC road may increase.

In order to prevent light or hydrogen from entering the active layers (ACT1, ACT2, ACT4) of each transistor (T1, T2, T4), a blocking layer 520 may be disposed on each transistor (T1, T2, T4). In this case, the first transistor T1, which needs to block hydrogen inflow, must have a large area overlapping with the blocking layer 520. Accordingly, the first gate electrode G1 can have a structure that overlaps the blocking layer 520. there is.

On the other hand, since the second transistor (T2) and the fourth transistor (T4) are less sensitive to hydrogen than the first transistor (T1), the second and fourth transistors (T2, T4) have a blocking layer 520. It may be sufficient to overlap only in some areas.

Accordingly, a portion of each of the second active layer (ACT2) and fourth active layer (ACT4) is formed to block some of the hydrogen and light flowing into the second and fourth transistors (T2, T4) and prevent RC delay. It may not overlap with the blocking layer 520. Specifically, the area where the second active layer (ACT2) overlaps the second gate electrode (G2) and the area where the fourth active layer (ACT4) overlaps the fourth gate electrode (G4) are formed with the blocking layer 520 and There may be some overlap.

Additionally, referring to FIGS. 6 to 8 , the area where the blocking layer 520 overlaps the first source electrode S1 and the first drain electrode D1 of the first transistor T1 is the area of the blocking layer 520. It is larger than the area overlapping with the second source electrode (S2) and the second drain electrode (D2) of the second transistor (T2), and the blocking layer 520 is connected to the fourth source electrode (S4) of the fourth transistor (T4). and may be larger than the area overlapping with the fourth drain electrode D4.

Additionally, referring to FIGS. 7 and 8 , the area where the blocking layer 520 overlaps the second source electrode (S2) and the second drain electrode (D2) of the second transistor (T2) is the area where the blocking layer 520 overlaps. It may be smaller than the area overlapping with the fourth source electrode S4 and the fourth drain electrode D4 of the fourth transistor T4.

Through this, a smaller amount of light and hydrogen can flow into the first transistor (T1) than the second and fourth transistors (T2 and T4), and a smaller amount of light and hydrogen can flow into the fourth transistor (T4) than the second transistor (T2). Light and hydrogen can flow in.

Referring to Figures 6 and 8, the blocking layer 520, which serves to prevent hydrogen and light from flowing into the transistor or to allow an appropriate amount of hydrogen to flow into the transistor, may be made of various shapes.

For example, referring to FIG. 6, the shape of the blocking layer 520 in the area overlapping the first transistor T1 may be a non-mesh type, and the open area may be It can be made in the form of a plate without a plate.

Additionally, referring to FIGS. 7 and 8 , the blocking layer 520 may have a plurality of open areas in each area overlapping with the second transistor T2 and the fourth transistor T4. . Here, the open area may mean an area where the light blocking layer 520 is not disposed on the transistor.

However, since the amount of hydrogen allowed to flow is different depending on the type of transistor, as shown in FIGS. 7 and 8, the blocking layer 520 disposed on the second transistor T2 has the area of the open area and the second transistor. 4 The area of the open area of the blocking layer 520 disposed on the transistor T4 may be different.

Additionally, as shown in FIG. 7 , multiple open areas with different areas may be disposed in one transistor, such as the blocking layer 520 disposed on the second transistor T2.

As described above, the amount of hydrogen flowing into the transistor varies depending on the area of the open area of the blocking layer 520 overlapping the transistor, which may affect the characteristics of the transistor.

Accordingly, with reference to FIGS. 9 and 10 , the electrical characteristics of the transistor that change depending on the area of the open area of the blocking layer 520 are examined as follows.

FIG. 9 is a diagram showing how the threshold voltage (Vth) value of a transistor changes depending on the ratio of the overlapping area between the open area of the transistor and the blocking layer. Figure 10 is a diagram showing the VGS and IDS curves of the transistor according to the ratio of the overlapping area between the open area of the transistor and the blocking layer.

9 and 10, the light blocking layer 520 is disposed on the transistor TR, and the ratio of the area where the open area OP of the light blocking layer 520 overlaps with the transistor TR is 36% to 53%. In the case of %, it can be seen that there is almost no change in the threshold voltage (Vth) of the transistor (TR).

In addition, referring to FIGS. 9 and 10 , when the ratio of the area where the open area (OP) of the light blocking layer 520 overlaps the transistor (TR) is greater than 53% (e.g., the area of the open area is 63% and In the case of 77%), it can be seen that the threshold voltage (Vth) of the transistor (TR) significantly shifts negatively.

In other words, as the area of the open area (OP) of the light blocking layer 520 increases, the amount of hydrogen flowing into the transistor (TR) increases, and this causes the threshold voltage (Vth) of the transistor (TR) to shift. , the characteristics of the transistor may deteriorate.

Accordingly, the ratio of the area where the open area OP of the light blocking layer 520 shown in FIGS. 7 and 8 overlaps with each of the second transistor T2 and the fourth transistor T4 may be 36% to 53%. there is.

Next, referring to FIG. 11, the structure in which each of the first transistor, the second transistor, and the fourth transistor and the light blocking layer overlap is examined in detail as follows.

FIG. 11 is a diagram showing the structure of a cross section taken along line A-B of FIG. 6, a cross section cut along C-D of FIG. 7, and a cross section cut along E-F of FIG. 8.

Referring to FIG. 11 , a light shield LS may be disposed on the substrate SUB.

A first active layer (ACT1), a second active layer (ACT2), and a fourth active layer (ACT4) may be disposed on the light shield LS. Each of the first active layer (ACT1), the second active layer (ACT2), and the fourth active layer (ACT4) may include an oxide semiconductor material.

Although FIG. 11 shows a structure in which each of the first active layer (ACT1), the second active layer (ACT2), and the fourth active layer (ACT4) is a single layer, embodiments of the present disclosure are not limited thereto, and have at least one The active layer may have a multi-layer structure.

Referring to FIG. 11 , a gate insulating layer GI may be disposed on each of the first active layer ACT1, the second active layer ACT2, and the fourth active layer ACT4.

The first gate electrode G1 may be disposed on the gate insulating layer GI disposed on the first active layer ACT1.

The second gate electrode G2 may be disposed on the gate insulating layer GI disposed on the second active layer ACT2.

The fourth gate electrode G4 may be disposed on the gate insulating layer GI disposed on the fourth active layer ACT4.

The gate insulating layer (GI) may be formed by etching through a process using plasma, and in this process, the first active layer (ACT1), the second active layer (ACT2), and the fourth active layer (ACT4) each form a channel region. Conductivity of the remaining areas can be achieved.

The gate electrodes G1, G2, and G4 may overlap the channel regions of the overlapping active layers ACT1, ACT2, and ACT3.

An interlayer dielectric (ILD) may be disposed on the substrate (SUB) on which the gate electrodes (G1, G2, and G4) are disposed. The interlayer dielectric (ILD) may cover the gate electrodes (G1, G2, and G4).

On this interlayer dielectric (ILD), the first source electrode (S1) and the first drain electrode (D1) of the first transistor (T1) are disposed to be spaced apart from each other, and the second source electrode (S2) of the second transistor (T2) and the second drain electrode D2 may be arranged to be spaced apart from each other, and the fourth source electrode S4 and the fourth drain electrode D4 of the fourth transistor T4 may be arranged to be spaced apart from each other.

Referring to FIG. 11 , each of the first source electrode S1 and the first drain electrode D1 may be electrically connected to the first active layer ACT1 through a contact hole formed in the interlayer dielectric layer ILD. Each of the second source electrode S2 and the second drain electrode D2 may be electrically connected to the second active layer ACT2 through a contact hole formed in the interlayer dielectric layer ILD. Each of the fourth source electrode S4 and the fourth drain electrode D4 may be electrically connected to the fourth active layer ACT4 through a contact hole formed in the interlayer insulating layer ILD.

A first passivation layer (PAS1) is formed on the source electrodes (S1, S2, S4) and drain electrodes (D1, D2, D4) of the first transistor (T1), the second transistor (T2), and the fourth transistor (T4), respectively. can be placed.

Referring to FIG. 11 , a blocking layer 520 may be disposed on the first passivation layer (PAS1).

A second passivation layer (PAS2) may be disposed on the blocking layer 520.

The second passivation layer (PAS2) may be an insulating layer containing hydrogen. This second passivation layer PAS2 may serve to supply hydrogen to areas other than the channel areas of the active layers disposed in the display panel 110.

The amount of charge of a thin film transistor containing an oxide semiconductor can be determined by the hydrogen content compared to the composition of the metal contained in the oxide semiconductor. Hydrogen can act as a carrier in an oxide semiconductor, so the higher the hydrogen content, the higher the charge mobility and the improved reliability of the transistor.

The second passivation layer (PAS2) may be an insulating film containing nitride, for example, silicon nitride (SiNx) or silicon oxynitride (SiON), but the second passivation layer (PAS2) according to embodiments of the present disclosure The material of the layer (PAS2) is not limited to this.

In addition, the configuration in which the second passivation layer (PAS2) contains hydrogen is only an example, and the blocking layer 520 prevents the hydrogen contained in the components disposed on the blocking layer 520 from excessively entering the active layer of the transistors. It can play a role in preventing the inflow of water.

Referring to FIG. 11, the blocking layer 520 disposed on the first transistor T1 includes the first active layer ACT1, the first gate electrode G1, and the first source electrode ( S1) and the first drain electrode (D1), respectively.

Specifically, the blocking layer 520 disposed on the first transistor T1 includes the entire first active layer ACT1, the entire first gate electrode G1, the entire first source electrode S1, and the entire first active layer ACT1. 1 may overlap with the entire drain electrode (D1).

In this way, the blocking layer 520 disposed on the first transistor (T1) overlaps the entire first transistor (T1), so that the blocking layer 520 effectively blocks hydrogen generated from the second passivation (PAS2), etc. By blocking, the electrical characteristics of the first transistor T1 can be maintained from changing.

However, the structure of the display panel according to embodiments of the present disclosure is not limited to this, and the blocking layer 520 disposed on the first transistor T1 includes the entire first active layer ACT1 and the first gate electrode. It may overlap the entirety of (G1), and may also overlap with a portion of the first source electrode (S1) or a portion of the first drain electrode (D1).

Referring to FIG. 11, the blocking layer 520 disposed on the second transistor T2 may be disposed to overlap a portion of the area where the second transistor T2 is disposed.

Specifically, as shown in FIG. 11 , the blocking layer 520 overlapping the second transistor T2 may have a plurality of patterns disposed on the first passivation layer PAS1 in cross-section.

This blocking layer 520 may overlap a portion of the second active layer ACT2.

Additionally, the blocking layer 520 may overlap a portion of the second source electrode S2 and the second drain electrode D2.

The blocking layer 520 may be disposed between the second gate electrode G2 and the second source electrode S2 and overlap the second active layer ACT2.

The blocking layer 520 may be disposed between the second gate electrode G2 and the second drain electrode D2 and overlap the second active layer ACT2.

Additionally, referring to FIG. 11 , the blocking layer 520 may not overlap the second gate electrode G2.

Through this structure, the blocking layer 520 is disposed on the second transistor T2 and appropriately blocks the inflow of light and hydrogen incident on the second active layer ACT2, while overlapping with the second gate electrode G2. This can prevent RC delay from occurring.

Referring to FIG. 11, the blocking layer 520 disposed on the fourth transistor T4 also has a partial area where the fourth transistor T4 is disposed, like the blocking layer 520 disposed on the second transistor T2. It can be placed to overlap.

The blocking layer 520 overlapping the fourth transistor T4 may be in the form of a plurality of patterns disposed on the first passivation layer PAS1 in cross-section.

This blocking layer 520 may overlap a portion of the fourth active layer ACT4.

Additionally, the blocking layer 520 may overlap a portion of the fourth source electrode S4 and the fourth drain electrode D4.

The blocking layer 520 may be disposed between the fourth gate electrode G4 and the fourth source electrode S4 and overlap the fourth active layer ACT4.

Referring to FIG. 11 , the blocking layer 520 may not overlap the fourth gate electrode G4.

Through this structure, the blocking layer 520 is disposed on the fourth transistor T4 to block the inflow of light and hydrogen incident on the fourth active layer ACT4, and the blocking layer 520 is connected to the fourth gate electrode. It can prevent RC delay from occurring by overlapping with (G4).

However, embodiments of the present disclosure are not limited thereto. For example, the blocking layer 520 may overlap a portion of a gate line formed integrally with the gate electrode in some areas excluding the area where the gate electrodes of the transistor overlap the active layer.

Additionally, referring to FIG. 11, among the blocking layer 520 patterns disposed on the second transistor T2, the blocking layer 520 pattern disposed on the second source electrode S2 and the second source electrode ( The width (X1) between the patterns of the blocking layer 520 disposed between S2) and the second gate electrode (G2) is determined by It may be larger than the width (X2) between the blocking layer 520 pattern disposed on (S4) and the blocking layer 520 pattern disposed between the fourth source electrode (S4) and the fourth gate electrode (G4). .

In addition, among the blocking layer 520 patterns disposed on the second transistor T2, the blocking layer 520 pattern disposed on the second drain electrode D2, the second drain electrode D2, and the second gate The width It may be larger than the width (X4) between the blocking layer 520 pattern disposed between the fourth drain electrode D4 and the fourth gate electrode G4.

X1 shown in FIG. 11 is one of the plurality of blocking layer 520 patterns disposed on the second source electrode (S2) and the second source electrode (S2) and the second gate electrode (G2). It refers to the distance between one of the plurality of blocking layer 520 patterns, and may refer to the minimum distance between patterns arranged closest to each other.

X2 is one of the plurality of blocking layer 520 patterns disposed on the fourth source electrode (S4), and a plurality of blocking layers ( 520) It refers to the distance between one of the patterns, but may refer to the minimum distance between patterns arranged most adjacent to each other.

X3 is one of the plurality of blocking layer 520 patterns disposed on the second drain electrode D2, and a plurality of blocking layers disposed on the second drain electrode D2 and the second gate electrode G2 ( 520) It refers to the distance between one of the patterns, but may refer to the minimum distance between patterns arranged most adjacent to each other.

X4 represents one of the plurality of blocking layer 520 patterns disposed on the fourth drain electrode D4 and a plurality of blocking layers disposed on the fourth drain electrode D4 and the fourth gate electrode G4 ( 520) It refers to the distance between one of the patterns, but may refer to the minimum distance between patterns arranged most adjacent to each other.

As shown in FIG. 11, each of X1 and X3 is formed larger than X2 and 520) can block a larger amount of light and hydrogen.

Referring to FIG. 11, the blocking layer 520 disposed on the first transistor (T1) is connected to the first source electrode (S1) of the first transistor (T1) through a contact hole provided in the first passivation layer (PAS1). can be electrically connected to.

An overcoat layer (OC) may be disposed on the second passivation layer (PAS2).

The pixel electrode (PE) of the light emitting device may be disposed on the overcoat layer (OC). The pixel electrode PE may be electrically connected to the blocking layer 520, which is electrically connected to the first source electrode S1 through a contact hole provided in the second passivation layer PAS2 and the overcoat layer OC. Although FIG. 11 illustrates a structure in which the blocking layer 520 is in contact with the first source electrode (S1), embodiments of the present disclosure are not limited to this and may also be in contact with the first drain electrode (D1).

A bank BK exposing a portion of the top surface of the pixel electrode PE may be disposed on the pixel electrode PE.

Meanwhile, as shown in FIG. 11, by adjusting the width between the patterns of the blocking layer 520 disposed on the second and fourth transistors T2 and T4, the amount of light and hydrogen flowing into each transistor can be adjusted. It can be adjusted.

Additionally, the charge mobility of at least some of the plurality of active layers disposed on the display panel 110 may be improved due to hydrogen supplied by the second passivation layer PAS2. In this case, the charge mobility of the active layer is adjusted by adjusting the width between the patterns of the blocking layer 520 disposed on the second and fourth transistors (T2, T4) and the thickness of the second passivation layer (PAS2). can be adjusted.

Additionally, the structure of the display panel 110 according to embodiments of the present disclosure is not limited to this, and may further include auxiliary electrodes disposed on the active layers, as shown in FIG. 12 .

FIG. 12 is a diagram illustrating a cross-sectional structure of a display panel according to embodiments of the present disclosure.

Referring to FIG. 12 , the first transistor T1 may include a first auxiliary electrode (AUX1) and a second auxiliary electrode (AUX2) disposed on the first active layer (ACT1). The first auxiliary electrode (AUX1) may be in contact with the first source electrode (S1), and the second auxiliary electrode (AUX2) may be in contact with the first drain electrode (D1). That is, the first auxiliary electrode (AUX1) and the second auxiliary electrode (AUX2) may serve to electrically connect the first active layer (ACT1) to the first source electrode (S1) and the first drain electrode (D1). there is.

The second transistor T2 may include a third auxiliary electrode (AUX3) and a fourth auxiliary electrode (AUX4) disposed on the second active layer (ACT2). The third auxiliary electrode (AUX3) may be in contact with the second source electrode (S2), and the fourth auxiliary electrode (AUX4) may be in contact with the second drain electrode (D2). The third auxiliary electrode (AUX3) and the fourth auxiliary electrode (AUX4) may serve to electrically connect the second active layer (ACT2) to the second source electrode (S2) and the second drain electrode (D2).

The fourth transistor T4 may include a fifth auxiliary electrode (AUX5) and a sixth auxiliary electrode (AUX6) disposed on the fourth active layer (ACT4). The fifth auxiliary electrode (AUX5) may be in contact with the fourth source electrode (S4), and the sixth auxiliary electrode (AUX6) may be in contact with the fourth drain electrode (D4). The fifth auxiliary electrode (AUX5) and the sixth auxiliary electrode (AUX6) may serve to electrically connect the fourth active layer (ACT4) to the fourth source electrode (S4) and the fourth drain electrode (D4).

Each of the first to sixth auxiliary electrodes (AUX1, AUX2, AUX3, AUX4, AUX5, and AUX6) may include a conductive material.

For example, each of the first to sixth auxiliary electrodes (AUX1, AUX2, AUX3, AUX4, AUX5, and AUX6) is made of copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), or molybdenum/titanium. (MoTi), etc., but the embodiments of the present disclosure are not limited thereto.

Each of the first to sixth auxiliary electrodes (AUX1, AUX2, AUX3, AUX4, AUX5, and AUX6) may include a conductive oxide. For example, the conductive oxide may include at least one of transparent conductive oxide (TCO), nitrous oxide, and organic material. For example, transparent conductive oxides (TCOs) include Indium Zinc Oxide (IZO), Indium Tin Oxide (ITO), Indium-Gallium-Zinc Oxide (IGZO), Zinc Oxide (ZnO), Aluminum-doped Zinc Oxide (AZO), It may include one or more of Gallium-doped Zinc Oxide (GZO), Antimony Tin Oxide (ATO), and Flourine-doped Transparent Oxides (FTO). Nitric oxides may include ZnON (Zinc Oxynitride).

In addition, in Figure 12, each of the first to sixth auxiliary electrodes (AUX1, AUX2, AUX3, AUX4, AUX5, and AUX6) shows a single-layer structure, but the structure of the auxiliary electrodes according to embodiments of the present disclosure is not limited to this. No, it may be made of multiple layers.

As shown in FIG. 12, the electrical characteristics of the transistor can be improved by arranging auxiliary electrodes on the top surfaces of each of the first active layer (ACT1), second active layer (ACT2), and fourth active layer (ACT4). .

FIG. 13 is a diagram illustrating a cross-sectional structure of a display area of a display panel according to embodiments of the present disclosure.

Referring to FIG. 13 , the display panel 110 may include a transistor forming part, a light emitting element forming part, and an encapsulation part when viewed in a vertical structure. .

The transistor forming part includes a substrate SUB, a first buffer layer BUF1 on the substrate SUB, and various transistors T1 and T2 formed on the first buffer layer BUF1, and a storage capacitor ( Cst), and may include various electrodes or signal wires.

The substrate SUB may include a first substrate SUB1 and a second substrate SUB2, and may include an intermediate layer INTL between the first substrate SUB1 and the second substrate SUB2. Here, for example, the interlayer (INTL) may be an inorganic membrane and may block moisture penetration.

The first buffer layer (BUF1) may be a single layer or a multilayer. When the first buffer layer BUF1 is a multi-layer, the first buffer layer BUF1 may include a multi-buffer layer MBUF and an active buffer layer ABUF.

Various transistors (T1, T2), storage capacitor (Cst), and various electrodes or signal wires may be formed on the first buffer layer (BUF1).

Referring to FIG. 13, among the transistors T1 and T2, the first transistor T1 and the second transistor T2 are made of different materials and may be located in different layers.

The first transistor T1 may include a first active layer ACT1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1.

The second transistor T2 may include a second active layer ACT2, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2.

The first active layer (ACT1) of the first transistor (T1) may be located higher than the second active layer (ACT2) of the second transistor (T2).

A first buffer layer (BUF1) is disposed under the second active layer (ACT2) of the second transistor (T2), and a second buffer layer (BUF2) is disposed under the first active layer (ACT1) of the first transistor (T1). It can be.

In FIG. 13 , the first active layer ACT1 of the first transistor T1 may include an oxide semiconductor material. Additionally, the second active layer (ACT2) of the second transistor (T2) may be made of low-temperature polycrystalline silicon (LTPS). However, embodiments of the present disclosure are not limited to this, and the second active layer ACT2 may be made of amorphous silicon (a-si).

The second active layer (ACT2) of the second transistor (T2) is disposed on the first buffer layer (BUF1), and the first gate insulating film (GI1) is disposed on the second active layer (ACT2) of the second transistor (T2). can be placed. The second gate electrode G2 of the second transistor T1 may be disposed on the first gate insulating film GI1, and the first interlayer insulating film may be disposed on the second gate electrode G2 of the second transistor T2. ILD1) can be deployed.

Additionally, referring to FIG. 13 , the first storage capacitor electrode PLT1 may be disposed on the same layer as the first gate electrode G1.

Here, the second active layer ACT2 of the second transistor T2 includes a second channel region overlapping the second gate electrode G2, a second source connection region located on one side of the second channel region, and a second It may include a second drain connection region located on the other side of the channel region.

The second storage capacitor electrode PLT2 may be disposed on the first interlayer insulating layer ILD1.

The first storage capacitor electrode (PLT1) and the second storage capacitor (PLT2) may overlap each other to form one storage capacitor.

A second buffer layer (BUF2) may be disposed on the first interlayer insulating layer (ILD1) and the second storage capacitor electrode (PLT2).

The first active layer (ACT1) of the first transistor (T1) may be disposed on the second buffer layer (BUF2), and the second gate insulating layer (GI2) may be disposed on the first active layer (ACT1). The second gate electrode G2 of the second transistor T2 may be disposed on the second gate insulating layer GI2, and the second interlayer insulating layer ILD2 may be disposed on the second gate electrode G2. .

Here, the first active layer (ACT1) of the first transistor (T1) includes a first channel region overlapping the first gate electrode (G1), a first source connection region located on one side of the first channel region, and a first It may include a first drain connection region located on the other side of the channel region.

The first source electrode S1 and the first drain electrode D1 of the first transistor T1 may be disposed on the second interlayer insulating layer ILD2. Additionally, the second source electrode S2 and the second drain electrode D2 of the second transistor T2 may be disposed on the second interlayer insulating layer ILD2.

The first source electrode (S1) and the first drain electrode (D1) of the first transistor (T1) are connected to the first active layer ( It may be connected to the first source connection area and the first drain connection area of ACT1), respectively.

Additionally, referring to FIG. 13, the first source electrode (S1) of the first transistor (T1) may be extended to overlap the second storage capacitor electrode (PLT2), and this first source electrode (S1) may be extended to overlap the second storage capacitor electrode (PLT2). It may be electrically connected to the second storage capacitor electrode PLT2 through contact holes in the interlayer insulating layer ILD2, the second gate insulating layer GI2, and the second buffer layer BUF2.

The second source electrode S2 and the second drain electrode D2 of the second transistor T2 are connected to the second interlayer insulating film ILD2, the second gate insulating film GI2, the second buffer layer BUF2, and the first interlayer insulating film ILD2. It may be connected to the second source connection region and the second drain connection region of the second active layer ACT2 through contact holes in the insulating layer ILD1 and the first gate insulating layer GI1, respectively.

Referring to FIG. 13 , a third interlayer insulating film PAS3 may be disposed on the first transistor T1 and the second transistor T2. That is, the third interlayer insulating film PAS3 is connected to the first source electrode S1 and the first drain electrode D2 of the first transistor T1 and the second source electrode S2 and the second electrode of the second transistor T2. It may be disposed on the drain electrode (D2).

A blocking layer 520 may be disposed on the third interlayer insulating layer PAS3.

Referring to FIG. 13 , the blocking layer 520 may be disposed to overlap the first transistor T1 including the first active layer ACT1 including an oxide semiconductor material.

Here, the blocking layer 520 may overlap each of the first active layer (ACT1), the first gate electrode (G1), the first source electrode (S1), and the first drain electrode (D1).

In particular, the blocking layer 520 overlaps the entire first active layer (ACT1), thereby preventing light and hydrogen from flowing into the first active layer (ACT1) and changing the electrical characteristics of the first transistor (T1). there is.

Referring to FIG. 13 , the blocking layer 520 may not be disposed on the second transistor including the second active layer ACT2 made of low-temperature polycrystalline silicon.

In the case of the second active layer (ACT2) made of low-temperature polycrystalline silicon, sensitivity to hydrogen may be lower than that of the first active layer (ACT1) made of an oxide semiconductor material. Therefore, as shown in FIG. 13, even if the blocking layer 520 is not disposed on the second transistor T2, the electrical characteristics of the second transistor T2 can be maintained.

This blocking layer 520 may be electrically connected to the first source electrode S1 through a contact hole provided in the third interlayer insulating film PAS3.

Referring to FIG. 13, a first planarization layer (PLN1) may be disposed on the blocking layer 520.

A relay electrode (RE) may be disposed on the first planarization layer (PLN1). The relay electrode RE may be an electrode that relays the electrical connection between the first source electrode S1 of the first transistor T1 and the pixel electrode PE of the light emitting element ED.

The relay electrode RE may be electrically connected to the blocking layer 520, which is electrically connected to the first source electrode S1 of the first transistor T1 through a contact hole in the first planarization layer PLN1.

A second planarization layer (PLN2) may be disposed on the relay electrode (RE) and the first planarization layer (PLN1).

The pixel electrode (PE) of the light emitting device (ED) may be disposed on the second planarization layer (PLN2). The pixel electrode PE may be electrically connected to the relay electrode RE through a contact hole provided in the second planarization layer PLN2.

The bank BK may be disposed on a portion of the upper surface of the pixel electrode PE and the second planarization layer PLN2.

A spacer (SPCE) may be disposed on a portion of the upper surface of the bank (BK). The spacer (SPCE) may serve to prevent the mask used when depositing the light emitting layer (EL) from contacting the substrate (SUB) and causing damage to components disposed on the substrate (SUB).

The light emitting layer (EL) of the light emitting element (ED) may be disposed on the bank (BK) and the pixel electrode (PE).

The common electrode (CE) of the light emitting element (ED) may be disposed on the light emitting layer (EL).

An encapsulation layer (ENCAP) may be disposed on the light emitting element (ED) of the display panel 110. The encapsulation layer (ENCAP) may be disposed to cover the light emitting elements (ED).

The encapsulation layer (ENCAP) may be a layer that prevents moisture or oxygen from penetrating into the light emitting element (ED) disposed below the encapsulation layer (ENCAP). In particular, the encapsulation layer (ENCAP) can prevent moisture or oxygen from penetrating into the light emitting layer (EL), which may include an organic layer. Here, the encapsulation layer (ENCAP) may be composed of a single layer or a multilayer.

Referring to FIG. 13, the encapsulation layer (ENCAP) may include a first encapsulation layer (PAS1), a second encapsulation layer (PCL), and a third encapsulation layer (PAS2). The first encapsulation layer (PAS1) and the third encapsulation layer (PAS2) may be inorganic films, and the second encapsulation layer (PCL) may be an organic film.

Since the second encapsulation layer (PCL) is composed of an organic layer, the second encapsulation layer (PCL) may function as a planarization layer.

The structure of the display panel 110 according to embodiments of the present disclosure is not limited to this.

FIG. 14 is a diagram illustrating a cross-sectional structure of a display panel according to embodiments of the present disclosure.

Referring to FIG. 14, the first gate electrode G1 of the first transistor T1 may be disposed on the substrate SUB. The first gate electrode G1 may be disposed in the display area DA.

The non-display area NDA of the display panel 110 may include at least one first pad electrode PAD1 disposed on the same layer as the first gate electrode G1.

A gate insulating layer GI may be disposed on the first gate electrode G1 and the first pad electrode PAD1.

The first active layer ACT1 may be disposed on the gate insulating layer GI. The first active layer (ACT1) may be made of an oxide semiconductor material.

On the first active layer (ACT1), the first source electrode (S1) and the first drain electrode (D1) of the first transistor (T1) may be disposed to be spaced apart from each other. Each of the first source electrode S1 and the first drain electrode D1 may be in contact with a portion of the upper surface of the first active layer ACT1.

In the non-display area NDA of the display panel 110, a second pad electrode PAD2 and a third pad electrode disposed on the same layer as the first source electrode S1 and the first drain electrode D1 and spaced apart from each other ( PAD3) can be deployed.

The second pad electrode (PAD2) may be electrically connected to the first padden electrode (PAD2) through a contact hole provided in the gate insulating film (GI).

A first passivation layer (PAS1) may be disposed on the substrate on which the first source electrode (S1) and the first drain electrode (D1) are disposed.

A blocking layer 520 may be disposed on the first passivation layer (PAS1).

The blocking layer 520 may overlap the first gate electrode (G1), the first active layer (ACT1), the first source electrode (S1), and the first drain electrode (D1) of the first transistor (T1). In particular, the blocking layer 520 may overlap the entire first active layer ACT1.

This blocking layer 520 may be electrically connected to the first source electrode S1 through a contact hole provided in the first passivation layer PAS1.

Referring to FIG. 13, a second passivation layer (PAS2) may be disposed on the blocking layer 520.

A planarization layer (PLN) may be disposed on the second passivation layer (PAS2).

The first electrode E1 may be disposed on the planarization layer PLN. The first electrode (E1) may be a common electrode (Vcom).

A third passivation layer (PAS3) may be disposed on the first electrode (E1).

The second electrode E2 may be disposed on the third passivation layer PAS3. The second electrode E2 may be a pixel electrode.

The second electrode E2 may be electrically connected to the blocking layer 520 through contact holes provided in the second passivation layer (PAS2), the planarization layer (PLN), and the third passivation layer (PAS3).

Additionally, referring to FIG. 14 , the fourth pad electrode PAD4 and the fifth pad electrode PAD5 may be disposed on the third passivation layer PAS3 in the non-display area NDA.

The fourth pad electrode (PAD4) may be electrically connected to the second pad electrode (PAD2) through a contact hole provided in the first to third passivation layers (PAS1, PAS2, and PAS3). Additionally, the fifth pad electrode (PAD5) may be electrically connected to the third pad electrode (PAD3) through a contact hole provided in the first to third passivation layers (PAS1, PAS2, and PAS3).

According to embodiments of the present disclosure, a display panel and a display device having a structure in which a blocking layer overlapping a transistor is disposed so that the amount of light and hydrogen incident on the transistor can be adjusted depending on the type of transistor can be provided.

According to embodiments of the present disclosure, a display panel and display device having high efficiency and long lifespan are provided by improving the electrical characteristics of the driving transistor and improving the reliability of the scan transistor through a blocking layer disposed on at least some of the transistors. can do.

The above description is merely an illustrative explanation of the technical idea of the present disclosure, and those skilled in the art will be able to make various modifications and variations without departing from the essential characteristics of the present disclosure. In addition, the embodiments disclosed in the present disclosure are not intended to limit the technical idea of the present disclosure, but rather are for explanation, and therefore the scope of the technical idea of the present disclosure is not limited by these embodiments.

Claims (18)

Board;
a first active layer and a second active layer disposed on the substrate;
a gate insulating layer disposed on the first and second active layers;
a first gate electrode disposed on the gate insulating layer, a first gate electrode disposed on the first active layer, and a second gate electrode disposed on the second active layer;
an interlayer insulating film disposed on the first and second gate electrodes;
a first source electrode and a first drain electrode disposed on the interlayer insulating film and spaced apart from each other, but electrically connected to the first active layer, and a second source electrode and a second drain electrode electrically connected to the second active layer;
a first passivation layer disposed on the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode; and
Comprising a blocking layer disposed on the first passivation layer,
The blocking layer overlaps the entire first active layer and a portion of the second active layer. According to paragraph 1,
The first active layer and the second active layer include an oxide semiconductor material. According to paragraph 1,
The blocking layer is electrically connected to the first source electrode or the first drain electrode. According to paragraph 3,
Further comprising a pixel electrode disposed on the blocking layer,
The blocking layer electrically connects the first source electrode or the first drain electrode and the pixel electrode. According to paragraph 1,
The display panel wherein the blocking layer overlaps the first gate electrode and does not overlap the second gate electrode. According to paragraph 1,
The first active layer, the first gate electrode, the first source electrode, and the first drain electrode are included in the first transistor,
The second active layer, the second gate electrode, the second source electrode, and the second drain electrode are included in the second transistor,
The first transistor is a driving transistor,
A display panel in which the second transistor is one of the remaining transistors excluding the driving transistor. According to clause 6,
The blocking layer overlaps the first transistor and the second transistor,
The display panel wherein an area where the blocking layer overlaps with the first transistor is larger than an area where the blocking layer overlaps with the second transistor. According to clause 6,
A display panel wherein the second transistor is a scan transistor or a sense transistor. According to clause 6,
a third active layer disposed on the substrate;
a third gate electrode disposed on the third active layer and overlapping the third active layer; and
Further comprising a third transistor disposed on the third gate electrode and including a third source electrode and a third drain electrode electrically connected to the third active layer,
The display panel wherein the blocking layer overlaps a portion of the third active layer on the third source electrode and the third drain electrode. According to clause 9,
A display panel in which the blocking layer does not overlap the third gate electrode. According to clause 9,
The area where the blocking layer overlaps the third transistor is,
A display panel wherein the blocking layer is smaller than an area overlapping with the first transistor and larger than an area where the blocking layer overlaps with the second transistor. According to clause 9,
The third transistor is disposed in a non-display area of the display panel. According to clause 9,
The blocking layer is arranged in a plurality of patterns on the second transistor and the third transistor in cross-section,
A display panel wherein a width between patterns of the blocking layer disposed on the second transistor is greater than a width between patterns of the blocking layer disposed on the third transistor. According to clause 10,
A display panel wherein the first active layer, the second active layer, and the third active layer are made of an oxide semiconductor material. According to paragraph 1,
a fourth active layer disposed on the substrate;
a fourth gate electrode disposed on the fourth active layer; and
Further comprising a fourth transistor disposed on the fourth gate electrode and including a fourth source electrode and a fourth drain electrode electrically connected to the fourth active layer,
A display panel in which the blocking layer is not disposed on the fourth transistor. According to clause 15,
A display panel in which the fourth active layer is made of low-temperature polycrystalline silicon or amorphous silicon. Board;
A first transistor disposed on the substrate and including the first active layer, a first gate electrode disposed on the first active layer, a first source electrode and a first drain electrode disposed on the first gate electrode. ;
A second gate electrode disposed below the first active layer of the first transistor, a second active layer disposed below the second gate electrode, and a second gate electrode disposed on the same layer as the first source electrode and the first drain electrode. a second transistor including two source electrodes and a second drain electrode; and
A blocking layer overlapping the entire first active layer of the first transistor,
The blocking layer does not overlap the second transistor. According to clause 17,
The first active layer is made of an oxide semiconductor material,
The second active layer is a display device made of low-temperature polycrystalline silicon or amorphous silicon.

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