KR20240095848A - Display panel and display device including the same - Google Patents

Abstract

The present invention relates to a display panel and a display device including the same, wherein the display panel includes a plurality of data lines; a plurality of gate lines crossing the data lines; a plurality of pixel lines including a plurality of sub-pixels arranged in a line direction; A first demultiplexer connected to the top of the data lines; and a second demultiplexer connected to lower ends of the data lines. At least one of the gate lines includes a shared gate line that is commonly connected to adjacent odd-numbered pixel lines and even-numbered pixel lines to transmit a gate signal to subpixels of the odd-numbered pixel lines and even-numbered pixel lines. The present invention can drive a large-area, high-resolution display panel without deteriorating image quality and reduce cost increases, enable low-power operation of the drive IC, and reduce the cost of the display device by lowering the unit cost of the drive IC and COF.

Description

Display panel and display device including the same {DISPLAY PANEL AND DISPLAY DEVICE INCLUDING THE SAME}

The present invention relates to a display panel and a display device including the same.

Electroluminescence displays can be divided into inorganic light emitting displays and organic light emitting displays depending on the material of the light emitting layer. The active matrix type organic light emitting display device includes an organic light emitting diode (hereinafter referred to as “OLED”) that emits light on its own, has a fast response speed, and has high luminous efficiency, brightness, and viewing angle. There is an advantage. In organic light emitting display devices, OLEDs are formed in each pixel. Organic light emitting display devices not only have a fast response speed and excellent luminous efficiency, brightness, and viewing angle, but also have excellent contrast ratio and color gamut because they can express black gradations in complete black.

As the process technology and driving circuit technology of electroluminescence displays have improved, screens have become possible to have large areas and high resolution. However, as display panels become larger in area, the resistance of the display panel increases, increasing signal delay problems. This is causing a difference in the charge amount of pixels between pixel lines.

A method of applying a data signal using a double feeding method can be considered. However, to implement this method, the number of drive ICs (Integrated Circuits) and the number of input/output terminals of each drive IC are increased. In addition, the pitch between the terminals of the COF (Chip On Film) on which the drive IC is mounted becomes narrow, and a double metal layer COF is required. The manufacturing cost of display devices increases significantly.

The present invention aims to solve the above-described needs and/or problems.

The present invention provides a display panel that can operate a large-area, high-resolution display panel without deteriorating image quality and reduce cost increases, and a display device including the same.

The problem of the present invention is not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

A display panel according to an embodiment of the present invention includes a plurality of data lines; a plurality of gate lines crossing the data lines; a plurality of pixel lines including a plurality of sub-pixels arranged in a line direction; A first demultiplexer connected to the top of the data lines; and a second demultiplexer connected to lower ends of the data lines. At least one of the gate lines includes a shared gate line that is commonly connected to adjacent odd-numbered pixel lines and even-numbered pixel lines to transmit a gate signal to subpixels of the odd-numbered pixel lines and even-numbered pixel lines.

The first demultiplexer includes: a first transistor that supplies a 1-1 data voltage from a first output terminal of a first drive IC to an upper end of a first data line in response to a first selection signal during a first pixel driving period; and a second transistor that supplies the 2-1 data voltage from the first output terminal of the first drive IC to the upper end of the second data line in response to a second selection signal during the second pixel driving period. The second demultiplexer is a third transistor that supplies the 1-2 data voltage from the first output terminal of the second drive IC to the lower end of the first data line in response to the third selection signal during the second pixel driving period. ; and a fourth transistor that supplies the 1-2 data voltage from the first output terminal of the second drive IC to the lower end of the second data line in response to a fourth selection signal during the first pixel driving period. .

The first pixel driving period may be a scan period within the M-th frame period, and the second pixel driving period may be a scan period within the M+1-th frame period.

The first pixel driving period may be a first scan period divided within one horizontal period, and the second pixel driving period may be a second scan period after the first scan period within the one horizontal period.

The odd-numbered pixel line may include a first subpixel that charges the 1-1 data voltage in the first pixel driving period and charges the 1-2 data voltage in the second pixel driving period. . The even-th pixel line may include a second subpixel that charges the 2-2 data voltage in the first pixel driving period and charges the 2-1 data voltage in the second pixel driving period. . The first and second subpixels may be vertically adjacent to one column line that intersects the odd-numbered pixel line and the even-numbered pixel line.

Each of the subpixels includes a light emitting device; a driving element that supplies current to the light emitting element; and a switch element that is turned on in synchronization with the transistors of the first and second demultiplexers to supply the data voltage from the data line to the driving element.

The data lines may be separated in the middle of the display panel.

The pixel lines include adjacent first and second pixel lines disposed in the upper half of the display panel; It may be disposed in the lower half of the display panel and include adjacent n-1th (n is a positive integer of 4 or more) and nth pixel lines. The first demultiplexer may alternately supply the data voltage from the first drive IC to a first upper data line connected to the first pixel line and a second upper data line connected to the second pixel line. The second demultiplexer may alternately supply the data voltage from the second drive IC to a first lower data line connected to the n-1th pixel line and a second lower data line connected to the second pixel line.

The display device of the present invention includes the display panel; A display panel including a plurality of pixel lines where a plurality of data lines and a plurality of gate lines intersect and a plurality of subpixels arranged in a line direction; a first drive disposed on the top of the display panel to output a data voltage to be charged to the sub-pixels; a first demultiplexer disposed between the first drive IC and upper ends of the data lines; a second drive disposed at the bottom of the display panel to output a data voltage to be charged to the sub-pixels; a second demultiplexer disposed between the second drive IC and lower ends of the data lines; and a gate driver disposed on the display panel to sequentially output a gate signal to the gate lines.

The present invention can improve luminance uniformity and increase luminance by reducing the charge amount difference between subpixels by single feeding data voltage to data lines using demultiplexers disposed at the top and bottom of the display panel. As a result, the present invention can operate a large-area, high-resolution display panel without deteriorating image quality and reduce cost increases.

Furthermore, the present invention can increase the luminance of subpixels, enabling low-power operation of the drive IC and reducing the cost of the display device by lowering the unit cost of the drive IC and COF.

The effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims.

1 is a block diagram showing a display device according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view showing the cross-sectional structure of the display panel shown in FIG. 1.
Figure 3 is a diagram showing drive ICs arranged at the top and bottom of the display panel.
Figure 4 is a diagram showing in detail the connection relationship between demultiplexers and pixels in the structure of a display panel according to an embodiment of the present invention.
Figure 5 is a diagram showing one frame period and one horizontal period.
Figure 6 is a diagram showing the difference in slew rate of the data voltage charged to the subpixel due to signal delay.
Figure 7 is a waveform diagram showing a control method of demultiplexers according to the first embodiment of the present invention.
FIGS. 8A and 8B are diagrams showing an example in which paths of data voltages charged to subpixels are alternated on a frame basis.
Figure 9 is a waveform diagram showing a control method of demultiplexers according to a second embodiment of the present invention.
FIGS. 10A and 10B are diagrams showing an example in which paths of data voltages charged to subpixels alternate within one horizontal period.
FIG. 11 is a diagram showing in detail the connection relationship between demultiplexers and pixels in the structure of a display panel according to another embodiment of the present invention.
FIG. 12 is a waveform diagram showing a method of controlling demultiplexers disposed on the display panel shown in FIG. 11.
FIGS. 13A and 13B are diagrams showing an example in which paths of data voltages charged to subpixels alternate within one horizontal period.
14 and 15 are circuit diagrams showing a pixel circuit according to an embodiment of the present invention.
FIG. 16 is a waveform diagram showing a method of driving the pixel circuit shown in FIG. 15.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms. The embodiments only serve to ensure that the disclosure of the present invention is complete, and those skilled in the art will be able to understand the present invention. It is provided to completely inform the scope of the invention, and the invention is only defined by the scope of the claims.

The shape, size, ratio, angle, number, etc. shown in the drawings for explaining embodiments of the present invention are illustrative, and the present invention is not limited to the matters shown in the drawings. Like reference numerals refer to substantially like elements throughout the specification. Additionally, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

When “provides,” “includes,” “has,” “consists of,” etc. mentioned in this specification are used, other parts may be added unless ‘only’ is used. If a component is expressed in the singular, it may be interpreted as plural unless specifically stated.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

Position between two components, such as 'on', 'on top', 'on the bottom', 'next to', '~ connect, couple', crossing, intersecting, etc. When relationships and interconnections are described, one or more other components may be interposed between the components, unless reference is made to 'immediately' or 'directly'.

If a temporal relationship is described as 'after', 'successfully after', 'after', 'before', etc., it may not be continuous on the time axis unless 'immediately' or 'directly' is used. .

First, second, etc. may be used to distinguish components, but the function or structure of these components is not limited by the ordinal number or component name in front of the component.

The following embodiments can be partially or fully combined or combined with each other, and various technological interconnections and drives are possible. Each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

In the display device of the present invention, the pixel circuit and the gate driving circuit may include a plurality of transistors. The transistor may be an Oxide TFT (Thin Film Transistor) containing an oxide semiconductor or a LTPS TFT containing Low Temperature Poly Silicon (LTPS).

A transistor is a three-electrode device including a gate, source, and drain. The source is an electrode that supplies carriers to the transistor. Within the transistor, carriers begin to flow from the source. The drain is the electrode through which carriers exit the transistor. In a transistor, the flow of carriers flows from the source to the drain. In the case of an n-channel transistor, because the carriers are electrons, the source voltage has a lower voltage than the drain voltage so that electrons can flow from the source to the drain. In an n-channel transistor, the direction of current flows from the drain to the source. In the case of a p-channel transistor, since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-channel transistor, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain may change depending on the applied voltage. Therefore, the invention is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as first and second electrodes.

The gate signal can swing between Gate On Voltage and Gate Off Voltage. The gate-on voltage is set to a voltage higher than the threshold voltage of the transistor. The gate-off voltage is set to a voltage lower than the threshold voltage of the transistor.

The transistor is turned on in response to the gate on voltage, while the transistor is turned off in response to the gate off voltage. In the case of an n-channel transistor, the gate-on voltage may be the gate high voltage and the gate-off voltage may be the gate low voltage. In the case of a p-channel transistor, the gate-on voltage may be the gate low voltage and the gate-off voltage may be the gate high voltage.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings.

1 is a block diagram showing a display device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view showing the cross-sectional structure of the display panel shown in FIG. 1.

1 and 2, a display device according to an embodiment of the present invention includes a display panel 100, a display panel driving circuit for writing pixel data to pixels of the display panel 100, and pixels. and a power supply unit 600 that generates power necessary to drive the display panel driving circuit.

The display panel 100 may be a panel with a rectangular structure having a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. The display area AA of the display panel 100 includes a pixel array that displays an input image. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 that intersect the data lines 102, and pixels arranged in a matrix form. The display panel 100 may further include power lines commonly connected to pixels. Power lines are connected to constant voltage nodes of the pixel circuits to supply the pixels 101 with a constant voltage required to drive the pixels 101.

Each of the pixels 101 may be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel to implement color. Each of the pixels may further include a white subpixel. Each subpixel includes a pixel circuit. Each pixel circuit is connected to data lines, gate lines, and power lines. The pixel circuit may be implemented as a circuit such as that of FIGS. 14 and 15, but is not limited thereto.

The pixel array includes a plurality of pixel lines (L1 to Ln). Each of the pixel lines L1 to Ln includes one line of pixels arranged along the line direction or the longitudinal direction (X-axis direction) of the display panel in the pixel array of the display panel 100.

The display panel 100 may be implemented as a non-transmissive display panel or a transmissive display panel. A transmissive display panel can be applied to a transparent display device where an image is displayed on the screen and the actual object in the background is visible. The display panel 100 may be manufactured as a flexible display panel.

The cross-sectional structure of the display panel 100 may include a circuit layer (CIR), a light emitting element layer (EMIL), and an encapsulation layer (ENC) stacked on a substrate (SUBS) as shown in FIG. 2. there is.

The circuit layer (CIR) may include a TFT array including a pixel circuit connected to wires such as data lines, gate lines, and power lines, distribution units 210 and 310, and gate drivers 410 and 420. The circuit layer (CIR) includes a plurality of metal layers insulated with insulating layers interposed therebetween, and a semiconductor material layer. All transistors formed in the circuit layer (CIR) can be implemented as n-channel oxide TFTs.

The light emitting device layer (EMIL) may include a light emitting device (EL) driven by a pixel circuit. The light emitting device EL may include a red subpixel light emitting device, a green subpixel light emitting device, and a blue subpixel light emitting device. The light emitting device layer (EMIL) may further include a white subpixel light emitting device. The light emitting element layer (EMIL) in each subpixel may have a structure in which a light emitting element and a color filter are stacked. The light emitting elements EL of the light emitting element layer EMIL may be covered with multiple protective layers including an organic layer and an inorganic layer.

The encapsulation layer (ENC) covers the light emitting device layer (EMIL) to seal the circuit layer (CIR) and the light emitting device layer (EMIL). The encapsulation layer (ENC) may have a multi-insulating film structure in which organic and inorganic films are alternately stacked. The inorganic membrane blocks the penetration of moisture or oxygen. The organic film flattens the surface of the inorganic film. When an organic film and an inorganic film are stacked in multiple layers, the movement path of moisture or oxygen is longer compared to a single layer, so the penetration of moisture and oxygen that affects the light emitting device layer (EMIL) can be effectively blocked.

A touch sensor layer (omitted from the drawing) may be formed on the encapsulation layer (ENC), and a polarizing plate or color filter layer may be disposed thereon. The touch sensor layer may include capacitive touch sensors that sense touch input based on changes in capacitance before and after touch input. The touch sensor layer may include metal wiring patterns and insulating films that form the capacitance of the touch sensors. The insulating films can insulate the intersections of metal wiring patterns and flatten the surface of the touch sensor layer. The polarizer can improve visibility and contrast ratio by converting the polarization of external light reflected by the metal of the touch sensor layer and circuit layer. The polarizer may be implemented as a polarizer or circular polarizer in which a linear polarizer and a phase retardation film are bonded. A cover glass may be adhered onto the polarizer. The color filter layer may include red, green, and blue color filters. The color filter layer may further include a black matrix pattern. The color filter layer absorbs part of the wavelength of light reflected from the circuit layer and the touch sensor layer, taking the role of a polarizer and increasing the color purity of the image reproduced in the pixel array.

The power supply unit 600 uses a DC-DC converter to generate direct current (DC) voltage (or constant voltage) required to drive the pixel array of the display panel 100 and the display panel driving circuit. The DC-DC converter may include a charge pump, regulator, buck converter, boost converter, etc. The power supply unit 600 adjusts the level of the direct current input voltage applied from a host system (not shown) to the gamma reference voltage and gate-on voltage (VGH). Constant voltages such as gate-off voltage (VGL), pixel driving voltage (EVDD), low-potential pixel base voltage (EVSS), initialization voltage (VINIT), and reference voltage (VREF) can be generated. The gamma reference voltage is supplied to the data drivers 200 and 300. Gate-on voltage (VGH) and gate-off voltage (VGL) are supplied to the gate drivers 410 and 420. Constant voltages such as the pixel driving voltage (EVDD), pixel base voltage (EVSS), initialization voltage (VINIT), and reference voltage (VREF) are supplied to the pixels 101 through power lines commonly connected to the pixels 101. You can.

The display panel driving circuit writes pixel data of the input image to the pixels of the display panel 100 under the control of a timing controller 500.

The display panel driving circuit includes data driving units 200 and 300, distribution units 210 and 310, and gate driving units 410 and 420. The display panel driving circuit includes a timing controller 500 that controls data driving units 200 and 300, distribution units 210 and 310, and gate driving units 410 and 420.

The display panel driving circuit may further include a touch sensor driving unit for driving the touch sensors. The touch sensor driver is omitted in FIG. 1. The data drivers 200 and 300 and the touch sensor driver may be integrated into one drive IC (Integrated Circuit).

The data drivers 200 and 300 include a first data driver 200 disposed at the top of the display panel 100 and a second data driver 300 disposed at the bottom of the display panel 100 . Each of the first and second data drivers 200 and 300 may be implemented with one or more drive ICs DIC1 and DIC2 as shown in FIG. 3 .

Each of the first and second data drivers 200 and 300 receives pixel data of an input image received as a digital signal from the timing controller 500 and outputs a data voltage. Each of the first and second data drivers 200 and 300 converts pixel data of an input image into a gamma compensation voltage using a digital to analog converter (DAC) and outputs a data voltage. The gamma reference voltage is divided into a gamma compensation voltage for each gray level through a voltage dividing circuit. The gamma compensation voltage for each gray level is provided to the DAC of the data drivers 200 and 300. The data voltage is output from each channel of the data drivers 200 and 300 through an output buffer.

The distribution units 210 and 310 include a first distribution unit 210 disposed at the top of the display panel 100 and a second distribution unit 310 disposed at the bottom of the display panel 100. Each of the first and second distribution units 210 and 310 includes one or more de-multiplexers (DEMUX). The demultiplexer sequentially distributes the data voltage output from the channels of the data drivers 200 and 300 to the data lines 102 using a plurality of switch elements. Due to the demultiplexer, the number of data drivers 200 and 300 and channels can be reduced. The demultiplexer may be a 1:N (N is a positive integer greater than or equal to 2) demultiplexer. Although a 1:2 demultiplexer is illustrated in FIG. 3, it is not limited thereto.

The gate drivers 410 and 420 include a first gate driver 410 disposed on the left side of the display panel 100 and a second gate driver 420 disposed on the right side of the display panel 100 . The gate drivers 410 and 420 may be implemented as a gate in panel (GIP) circuit formed in the circuit layer (CIR) on the display panel 100 along with the TFT array and wires of the pixel array. The gate drivers 410 and 420 are disposed on the bezel area (BZ), which is a non-display area of the display panel 100, or at least some of the circuit elements constituting the gate drivers 410 and 420 are located in the display area (AA). ) can be placed in.

The gate drivers 410 and 420 may supply pulses of the gate signal from both sides of the gate lines 103 using a double feeding method. For example, the first gate driver 410 and the second gate driver 420 may simultaneously apply gate signal pulses on both sides of each gate line under the control of the timing controller 500. The gate drivers 410 and 420 may supply pulses of the gate signal from one side of the gate lines 103 using a single feeding method. For example, the first gate driver 410 applies a pulse of the gate signal to one side of the odd-numbered gate lines 103 under the control of the timing controller 500, and the second gate driver 420 applies the pulse of the gate signal to the timing controller ( A pulse of the gate signal may be applied to the other side of the even-numbered gate lines 103 under the control of 500).

The gate drivers 410 and 420 can sequentially supply the signals to the gate lines 103 by shifting the gate signals using a shift register. The gate drivers 410 and 420 may include a plurality of shift registers. For example, in the examples of FIGS. 15 and 16, the gate drivers 410 and 420 use a first shift register and a second gate signal S2N to sequentially output the first gate signal S1N. It may include a second shift register that sequentially outputs the signal, and a third shift register that sequentially outputs the third gate signal (EM).

The timing controller 500 receives digital video data of an input image and a timing signal synchronized therewith from the host system. The timing signal may include a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a clock (CLK), and a data enable signal (DE). Since the vertical period and horizontal period can be known by counting the data enable signal (DE), the vertical synchronization signal (Vsync) and horizontal synchronization signal (Hsync) can be omitted. The data enable signal (DE) has a period of 1 horizontal period (1H).

The host system may be any one of a television (TV) system, a tablet computer, a laptop computer, a personal computer (PC), a home theater system, and a vehicle system. The host system may scale the image signal from the video source to match the resolution of the display panel 100 and transmit it to the timing controller 500 along with the timing signal.

The timing controller 500 transmits pixel data of the input image to the data drivers 200 and 300. The timing controller 500 provides a data timing control signal for controlling the operation timing of the data drivers 200 and 300 based on timing signals (Vsync, Hsync, DE) received from the host system, and a data timing control signal of the distribution units 210 and 310. A control signal for controlling the operation timing and a gate timing control signal for controlling the operation timing of the gate drivers 410 and 420 may be output. The timing controller 500 can synchronize the data drivers 200 and 300, the distribution units 210 and 310, and the gate drivers 410 and 420 by controlling the operation timing of the display panel driving circuit.

The gate timing control signal output from the timing controller 500 may be supplied to the gate drivers 410 and 420 through a level shifter (not shown). The level shifter can receive a gate timing control signal, generate a start pulse and a shift clock, and supply them to the shift registers of the gate drivers 410 and 420.

Figure 3 is a diagram showing drive ICs arranged at the top and bottom of the display panel.

Referring to FIG. 3, the first data driver 200 may include a plurality of first COFs (COF1) on which the first drive IC (DIC1) is mounted. As shown in FIG. 4 , the first distribution unit 210 includes a plurality of first demultiplexers DEMUX1 disposed between the first COFs COF1 and the display area AA. The output pads of the first COFs (COF1) are attached to the top of the display panel through an anisotropic conductive film (ACF).

Output terminals of the first drive IC (DIC1) may be electrically connected to input terminals of the first demultiplexer (DEMUX1). The first demultiplexer DEMUX1 may be connected to the first COF COF1 and the upper ends of the data lines DL1 to DL6 of the display area AA.

The second data driver 300 may include a plurality of second COFs (COF2) on which a second drive IC (DIC2) is mounted. As shown in FIG. 4 , the second distribution unit 310 includes a plurality of second demultiplexers DEMUX2 disposed between the second COFs COF2 and the display area AA. The output pads of the second COFs (COF2) are attached to the bottom of the display panel through the ACF.

Output terminals of the second drive IC (DIC2) may be electrically connected to input terminals of the second demultiplexer (DEMUX2). The second demultiplexer DEMUX2 may be connected to the second COF COF2 and the lower ends of the data lines DL1 to DL6 of the display area AA.

In FIG. 3, “SCAN SHIFT” indicates a scan shift direction in which the pulses of the gate signal are sequentially shifted and pixel lines on which pixel data is written are sequentially selected line by line.

Figure 4 is a diagram showing in detail the connection relationship between demultiplexers and pixels. In FIG. 4, 'R1, R2' are red subpixels arranged in the same column line in neighboring pixel lines (OPL, EPL). 'G1, G2' are green subpixels arranged on the same column line in neighboring pixel lines (OPL, EPL). 'B1, B2' are blue subpixels arranged on the same column line in neighboring pixel lines (OPL, EPL).

Referring to FIG. 4 , the first drive IC (DIC1) may be placed at the top of the display panel 100, and the second drive IC (DIC2) may be placed at the bottom of the display panel 100.

The first drive IC (DIC1) may include a first output terminal (UOUT1), a second output terminal (UOUT2), and a third output terminal (UOUT3). The data voltage UD1 output from the first output terminal UOUT1 is the 1-1 R data voltage output during the first pixel driving period and charged in the first red subpixel R1, and the 1-1 R data voltage output during the first pixel driving period and charged to the first red subpixel R1 during the second pixel driving period. It may include a 2-1 R data voltage that is output and charged to the second red subpixel (R2). The data voltage UD2 output from the second output terminal UOUT2 is the 1-1 G data voltage output during the first pixel driving period and charged in the first green sub-pixel G1, and the It may include a 2-1 G data voltage that is output and charged to the second green subpixel (G2). The data voltage UD3 output from the third output terminal UOUT3 is the 1-1 B data voltage output during the first pixel driving period and charged in the first blue subpixel B1, and the data voltage UD3 output during the first pixel driving period and charged to the first blue subpixel B1 during the second pixel driving period. It may include a 2-1 B data voltage that is output and charged to the second blue subpixel (B2).

The second drive IC (DIC2) may include a first output terminal (BOUT1), a second output terminal (BOUT2), and a third output terminal (BOUT3). The data voltage BD1 output from the first output terminal BOUT1 is the 2-2 R data voltage output during the first pixel driving period and charged in the second red subpixel R2, and the 2-2 R data voltage output during the first pixel driving period and charged to the second red subpixel R2 during the second pixel driving period It may include 1-2 1 data voltages that are output and charged to the first red subpixel (R1). The data voltage BD2 output from the second output terminal BOUT2 is the 2-2G data voltage output during the first pixel driving period and charged in the second green subpixel G2, and It may include a 1-2 G data voltage that is output and charged to the first green subpixel (G1). The data voltage BD3 output from the third output terminal BOUT3 is the 2-2 B data voltage output during the first pixel driving period and charged in the second blue subpixel B2, and the 2-2 B data voltage output during the first pixel driving period and charged in the second blue subpixel B2 during the second pixel driving period. It may include a 1-2 B data voltage that is output and charged to the first blue subpixel (B1).

The first demultiplexer (DEMUX1) is disposed between the first drive IC (DIC1) and the top of the data lines (DL1 to DL6). The first demultiplexer (DEMUX1) may include one input terminal and at least two output terminals. The first demultiplexer (DEMUX1) is turned on in response to the pulse of the first selection signal (UMUX1) to supply the data voltages (UD1, UD2, UD3) to the top of the odd-numbered data lines (DL1, DL3, and DL5). there is. The first demultiplexer (DEMUX1) is turned on in response to the pulse of the second selection signal (UMUX2) to supply the data voltages (UD1, UD2, UD3) to the upper ends of the even-th data lines (DL2, DL4, and DL6). there is.

The first demultiplexer (DEMUX1) includes at least first and second transistors (UT1 and UT2). The first transistor (UT1) is turned on according to the pulse of the first selection signal (UMUX1) and transmits the data voltages (UD1, UD2, UD3) from the first drive IC (DIC1) to the odd-numbered data lines (DL1, DL3, It is supplied to DL5). The first transistor UT1 has a first electrode to which the data voltages UD1, UD2, and UD3 of the pixel data are applied, a gate electrode to which the first selection signal UMUX1 is applied, and odd-numbered data lines DL1, DL3, and DL5. ) and a second electrode connected to the electrode. The second transistor (UT2) is turned on according to the pulse of the second selection signal (UMUX2) and transmits the data voltages (UD1, UD2, UD3) from the first drive IC (DIC1) to the even-th data lines (DL2, DL4, It is supplied to DL6). The second transistor UT2 has a first electrode to which the data voltages UD1, UD2, and UD3 of the pixel data are applied, a gate electrode to which the second selection signal UMUX2 is applied, and even-th data lines DL2, DL4, and DL6. ) and a second electrode connected to the

The second demultiplexer (DEMUX2) is disposed between the second drive IC (DIC2) and the lower ends of the data lines (DL1 to DL6). The second demultiplexer (DEMUX2) may include one input terminal and at least two output terminals. The second demultiplexer (DEMUX2) is turned on in response to the pulse of the third selection signal (BMUX1) to supply the data voltages (BD1, BD2, BD3) to the lower ends of the odd-numbered data lines (DL1, DL3, and DL5). there is. The second demultiplexer (DEMUX2) is turned on in response to the pulse of the fourth selection signal (BMUX2) to supply the data voltages (BD1, BD2, BD3) to the lower ends of the even-th data lines (DL2, DL4, and DL6). there is.

The second demultiplexer DEMUX2 includes at least third and fourth transistors BT1 and BT2. The third transistor (BT1) is turned on according to the pulse of the third selection signal (BMUX1) and transmits the data voltages (BD1, BD2, BD3) from the second drive IC (DIC2) to the odd-numbered data lines (DL1, DL3, It is supplied to DL5). The third transistor BT1 has a first electrode to which the data voltages BD1, BD2, and BD3 of the pixel data are applied, a gate electrode to which the third selection signal BMUX1 is applied, and odd-numbered data lines DL1, DL3, and DL5. ) and a second electrode connected to the electrode. The fourth transistor (BT2) is turned on according to the pulse of the fourth selection signal (BMUX2) and transmits the data voltages (BD1, BD2, BD3) from the second drive IC (DIC2) to the upper and lower data lines (DL2, DL4, It is supplied to DL6). The fourth transistor BT2 has a first electrode to which the data voltages BD1, BD2, and BD3 of the pixel data are applied, a gate electrode to which the fourth selection signal BMUX2 is applied, and the even-th data lines DL2, DL4, and DL6. ) and a second electrode connected to the electrode.

The transistors UT1 and UT2 of the first demultiplexer DEMUX1 are alternately driven in units of predetermined pixel driving periods to supply data voltages UD1, UD2, and UD3 to the upper ends of the data lines DL1 to DL2. For example, the first transistor UT1 transmits the 1-1 data voltage from the first output terminal of the first drive IC DIC1 in response to the first selection signal UMUX1 during the first pixel driving period. It is supplied to the top of the data line (DL1). Subsequently, the second transistor UT2 transmits the 2-1 data voltage from the first output terminal of the first drive IC (DIC2) to the second data line in response to the second selection signal UMUX2 during the second pixel driving period. supplied to the top of.

The transistors BT1 and BT2 of the second demultiplexer DEMUX2 are alternately driven in units of pixel driving periods to supply data voltages BD1, BD2, and BD3 to the lower ends of the data lines DL1 to DL2. For example, the third transistor BT1 is synchronized with the second transistor UT2 and outputs the signal from the first output terminal of the second drive IC DIC1 in response to the third selection signal BMUX1 during the second pixel driving period. A 1-2 data voltage is supplied to the lower end of the first data line. The fourth transistor BT2 is synchronized with the first transistor UT1 and generates the 2-2 data voltage from the first output terminal of the second drive IC in response to the fourth selection signal BMUX2 during the first pixel driving period. It is supplied to the lower end of the second data line.

The demultiplexers (DEMUX1, DEMUX2) and the switch element of the pixel circuit, that is, the transistor, may be turned on according to the gate-on voltage, while they may be turned off according to the gate-off voltage. The switch element of the pixel circuit may apply the data voltage to the gate electrode or first electrode of the driving element DT as shown in FIGS. 14 and 15, but is not limited thereto.

Pixel lines (OPL, EPL) and column lines (COL1, COL2) intersect. The pixel lines OPL and EPL include subpixels arranged along the gate line direction (X), and the column lines COL1 and COL2 include subpixels arranged along the data line direction (Y).

The subpixels R1, G1, and B1 arranged on the odd-numbered pixel line OPL may be connected to the odd-numbered data lines DL1, DL3, and DL5. The subpixels R2, G2, and B2 arranged on the even-numbered pixel line EPL may be connected to the even-numbered data lines DL2, DL4, and DL6.

At least one of the gate lines of the display panel 100 is commonly connected to adjacent odd-numbered pixel lines and even-numbered pixel lines to transmit a gate signal to sub-pixels of the odd-numbered pixel line and even-numbered pixel lines through a shared gate line. It can be included. For example, in FIG. 4, the subpixels R1 to B2 arranged on two neighboring pixel lines OPL and EPL share one gate line GL1 so that the pulses of the gate signal GATE1 are transmitted simultaneously. It may be applied to the subpixels R1 to B2 simultaneously. Subpixels arranged above and below one column line may be connected to different data lines. For example, in the first column line COL1, the first red subpixel R1 is connected to the first data line DL1, and the second red subpixel disposed below the first red subpixel R1 ( R2) may be connected to the second data line DL2. The first and second red subpixels R1 and R2 share one gate line GL1. In the second column line COL2, the first green subpixel G1 is connected to the third data line DL3, and the second green subpixel G2 disposed below the first green subpixel G1 is connected to the third data line DL3. 4 can be connected to the data line (DL4). The first and second green subpixels G1 and G2 share one gate line GL1.

The timing controller 500 controls the first and second distribution units 210 and 310 to reduce the difference in charging amounts of sub-pixels, thereby reducing the difference in luminance between pixel lines and increasing the luminance of pixels. The switch elements UT1 to BT2 of the first and second distribution units 210 and 310 are alternately driven in units of frames or one horizontal period under the control of the timing controller 500 to reduce the difference in charge amount between pixel lines. there is.

Figure 5 is a diagram showing one frame period and one horizontal period.

Referring to FIG. 5, the vertical synchronization signal (Vsync), horizontal synchronization signal (Vsync), and data enable signal (DE) are timing signals that are synchronized with pixel data of the input image.

The vertical synchronization signal (Vsync) defines one frame period. The horizontal synchronization signal (Hsync) defines one horizontal period (1H). The data enable signal DE defines a valid data section including pixel data to be written to pixels. Pulses of the data enable signal DE are synchronized with pixel data to be written in pixels of the display panel 100. One pulse period of the data enable signal (DE) is one horizontal period (1H).

One frame period (1 Frame) is divided into an active period (AT) in which pixel data of the input image is written to pixels, and a vertical blank period (VB) in which there is no pixel data. The vertical blank period (VB) is a blank period in which pixel data is not received by the timing controller 130 between the active period (AT) of the M-1 (M is a natural number) frame period and the active period (AT) of the M frame period. It's a period. The active period (AT) includes pixel data to be written in subpixels of all pixel lines (L1 to Ln) of the display panel.

As shown in FIGS. 3 and 4, when the first and second subpixels R1 and R2 are disposed on the upper side of the display panel 100, the subpixels ( The data voltage (UD1) applied to R1 and R2) has a small RC delay because the resistance and capacitor in the transmission path are small. On the other hand, the data voltage UD1 applied from the second drive IC DIC2 to the subpixels R1 and R2 has a large resistance and capacitor in the transmission path, so the RC delay is relatively large. Accordingly, the first and second red subpixels (R1, R2) have a large charge amount when charging the data voltage (UD1) output from the first drive IC (DIC1), while the charge amount is large when the data voltage (UD1) output from the first drive IC (DIC1) is charged. When charging the data voltage BD1, the charging amount may be relatively small. When the voltages (UD1, BD1) output from the first and second drive ICs (DIC1, DIC2) have the same voltage level, the data voltage charge of the first red subpixel (R1) is the second due to the difference in RC delay. It becomes larger than the data voltage charge amount of the red subpixel (R2).

Differences in RC delay result in differences in slew rates of data voltages charged to subpixels. For example, when a data voltage is applied to a subpixel through a data voltage transmission path with a small RC delay amount in the first period, the slew rate PIX(S) charged to the subpixel is large, as shown in FIG. 6. Then, in the second period, when the data voltage is applied to the subpixel through a data voltage transmission path with a large RC delay amount, the slew rate (PIX(W)) charged to the subpixel is large, as shown in FIG. 6. In FIG. 6, 'PIX(A)' represents the slew rate (PIX(S)) of the data voltage charged in the subpixel during the first period and the slew rate (PIX(S)) of the data voltage charged in the subpixel during the second period. W)) is the average. The display device of the present invention can alternate the data voltage transmission path in each sub-pixel for a predetermined period of time, for example, a frame period or a horizontal period, in order to reduce the difference in charging amount between pixels and increase luminance across the screen.

Figure 7 is a waveform diagram showing a control method of demultiplexers according to the first embodiment of the present invention. FIGS. 8A and 8B are diagrams showing an example in which paths of data voltages charged to subpixels are alternated on a frame basis. 7 to 8B, 'S' in parentheses is a subpixel with a large data voltage charge, and 'W' in parentheses is a subpixel with a relatively small data voltage charge. In FIGS. 8A and 8B , the red subpixels R1 and R2 that are adjacent to each other above and below are illustrated, but they can be charged in the same way as the green, red and green subpixels omitted from the drawings.

Referring to FIGS. 3 to 8B, a pulse of the gate signal (GATE1) is generated as the gate-on voltage (VGL) in the first pixel driving period (P10), and the gate signal (GATE1) is generated in the second pixel driving period (P20). A pulse is generated as the gate-on voltage (VGL). The pulses of the selection signals (UMUX1 to BMUX2) are generated as the gate-on voltage (VGL) and overlap with the pulses of the gate signal (GATE1). The pulse width of the selection signals (UMUX1 to BMUX2) can be set wider than the pulse width of the gate-on voltage (VGL).

During the first pixel driving period P10, a pulse of the gate signal GATE1 synchronized with the data voltages UD1 and BD1 is generated as the gate-on voltage VGL. At the same time, the first and fourth selection signals (UMUX1, BMUX2) are generated as pulses of the gate-on voltage (VGL), and the voltage of the second and third selection signals (UMUX2, BMUX1) is the gate-off voltage (VGH). . The first pixel driving period P10 is a pulse of the gate signal GATE1 to neighboring pixel lines where the first and second red subpixels R1 and R2 are arranged in the M frame period FR(M). may be an authorized scan period.

During the first pixel driving period (P10), the switch elements of the red sub-pixels (R1, R2) arranged on the neighboring odd-numbered pixel line (OPL) and even-numbered pixel line (EPL) turn on the gate signal (GATE1). It turns on simultaneously depending on the voltage (VGL). At the same time, as shown in FIG. 8A, the first and fourth transistors UT1 and BT2 of the demultiplexers DEMUX1 and DEMUX2 are turned on.

During the first pixel driving period (P10), the data voltage (UD1) output from the first drive IC (DIC1) is transmitted to the first red sub-pixel (R1) through the first transistor (UT1) and the switch element of the first red sub-pixel (R1). It is charged to the pixel (R1). At the same time, the data voltage BD1 output from the second drive IC DIC2 is charged to the second red subpixel R2 through the fourth transistor BT2 and the switch element of the second red subpixel R2. . When the voltages UD1 and BD1 output from the first and second drive ICs DIC1 and DIC2 have the same voltage level, the first red subpixel in the first pixel driving period P10 due to the difference in RC delay. The data voltage charge amount of (R1) may be greater than the data voltage charge amount of the second red subpixel (R2).

Subsequently, during the second pixel driving period P20, the pulse of the gate signal GATE1 synchronized with the data voltages UD1 and BD1 is generated again as the gate-on voltage VGL. At the same time, the second and third selection signals (UMUX2, BMUX1) are generated as pulses of the gate-on voltage (VGL), and the voltages of the first and fourth selection signals (UMUX1, BMUX2) are generated as the gate-off voltage (VGH). It is reversed. The second pixel driving period P20 is a gate signal ( This may be a scan period in which the pulse of GATE1) is applied.

During the second pixel driving period (P20), the switch elements of the red sub-pixels (R1, R2) arranged on the neighboring odd-numbered pixel line (OPL) and even-numbered pixel line (EPL) turn on the gate signal (GATE1). It turns on simultaneously depending on the voltage (VGL). At the same time, as shown in FIG. 8B, the second and third transistors UT2 and BT1 of the demultiplexers DEMUX1 and DEMUX2 are turned on.

During the second pixel driving period P20, the data voltage UD1 output from the first drive IC DIC1 is transmitted to the second red subpixel through the second transistor UT2 and the switch element of the second subpixel R2. (R2) is charged. At the same time, the data voltage BD1 output from the second drive IC DIC2 is charged to the first red subpixel R1 through the third transistor BT1 and the switch element of the first red subpixel R1. . When the voltages UD1 and BD1 output from the first and second drive ICs DIC1 and DIC2 have the same voltage level, the second red subpixel in the second pixel driving period P20 due to the difference in RC delay. The data voltage charge amount of (R2) may be greater than the data voltage charge amount of the first red subpixel (R1).

As can be seen in FIGS. 6 to 8B, the data voltage charge amount of each of the first and second subpixels (R1, R2) changes alternately with a period of 1 frame period, and the subpixels (R1, R2) are charged for 2 frame periods. ) The charge amount of data voltage in each is averaged. As a result, the variation in charge amount of each subpixel can be reduced and the luminance and uniformity of pixels across the screen can be increased.

Figure 9 is a waveform diagram showing a control method of demultiplexers according to a second embodiment of the present invention. FIGS. 10A and 10B are diagrams showing an example in which paths of data voltages charged to subpixels alternate within one horizontal period. 9 to 10B, 'S' in parentheses is a subpixel with a large data voltage charge, and 'W' in parentheses is a subpixel with a relatively small data voltage charge. In FIGS. 10A and 10B , the red subpixels R1 and R2 that are adjacent to each other above and below are illustrated, but they can be charged in the same way as the green and red subpixels omitted from the drawings.

Referring to FIGS. 9 to 10B, the transistors UT1 to BT2 of the demultiplexers DEMUX1 and DEMUX2 may be alternately driven within one horizontal period (1H). 1 Horizontal period (1H) can be divided into a first pixel driving period (P1) and a second pixel driving period (P2). In this case, the first pixel driving period (P1) is a first scan period divided within one horizontal period (1H), and the second pixel driving period (P2) is a second scan period set after the first scan period (1H). It can be.

During the first and second pixel driving periods P1 and P2, a pulse of the gate signal GATE1 may be generated as the gate-on voltage VGL. The pulses of the selection signals (UMUX1 to BMUX2) are generated as the gate-on voltage (VGL) and overlap with the pulses of the gate signal (GATE1). The pulse width of the selection signals (UMUX1 to BMUX2) may be set to a pulse width of approximately 1/2 or less than the pulse width of the gate-on voltage (VGL). When the pulse width of the gate signal (GATE1) is 1 horizontal period, switch elements of subpixels to which the gate signal (GATE1) is applied may be turned on for 1 horizontal period (1H).

During the first pixel driving period (P1), the first and fourth selection signals (UMUX1, BMUX2) are generated as pulses of the gate-on voltage (VGL), and the voltages of the second and third selection signals (UMUX2, BMUX1) are It is the gate-off voltage (VGH). During the first pixel driving period (P1), the switch elements of the red sub-pixels (R1, R2) arranged in the neighboring odd-numbered pixel line (OPL) and even-numbered pixel line (EPL) turn on the gate signal (GATE1). It turns on simultaneously depending on the voltage (VGL). At the same time, as shown in FIG. 10A, the first and fourth transistors UT1 and BT2 of the demultiplexers DEMUX1 and DEMUX2 are turned on.

During the first pixel driving period P1, as shown in FIG. 10A, the data voltage UD1 output from the first drive IC DIC1 is connected to the switch of the first transistor UT1 and the first red subpixel R1. The first red subpixel (R1) is charged through the device. At the same time, the data voltage BD1 output from the second drive IC DIC2 is charged to the second red subpixel R2 through the fourth transistor BT2 and the switch element of the second red subpixel R2. . During the first pixel driving period P1, the data voltage charge of the first red subpixel (R1) may be greater than the data voltage charge of the second red subpixel (R2).

Subsequently, during the second pixel driving period P2, the pulse of the gate signal GATE1 synchronized with the data voltages UD1 and BD1 is generated again as the gate-on voltage VGL. At the same time, the second and third selection signals (UMUX2, BMUX1) are generated as pulses of the gate-on voltage (VGL), and the voltages of the first and fourth selection signals (UMUX1, BMUX2) are generated as the gate-off voltage (VGH). It is reversed.

During the second pixel driving period (P2), the switch elements of the red sub-pixels (R1, R2) arranged on the neighboring odd-numbered pixel line (OPL) and even-numbered pixel line (EPL) turn on the gate signal (GATE1). It turns on simultaneously depending on the voltage (VGL). At the same time, as shown in FIG. 10B, the second and third transistors UT2 and BT1 of the demultiplexers DEMUX1 and DEMUX2 are turned on.

During the second pixel driving period P2, as shown in FIG. 10B, the data voltage UD1 output from the first drive IC DIC1 is applied to the second transistor UT2 and the switch element of the second subpixel R2. is charged to the second red subpixel (R2). At the same time, the data voltage BD1 output from the second drive IC DIC2 is charged to the first red subpixel R1 through the third transistor BT1 and the switch element of the first red subpixel R1. . During the second pixel driving period P2, the data voltage charge of the second red subpixel (R2) may be greater than the data voltage charge of the first red subpixel (R1).

9 to 10B, the data voltage charge amount of each of the first and second subpixels R1 and R2 changes alternately within one horizontal period (1H), thereby altering the first and second subpixels R1 and R2. R2) The charge amount of data voltage in each is averaged. As a result, the charge amount deviation between subpixels can be reduced and the luminance and uniformity of pixels across the screen can be increased.

FIG. 11 is a diagram showing in detail the connection relationship between demultiplexers and pixels in the structure of a display panel according to another embodiment of the present invention.

Referring to FIG. 11, the data lines of the display panel 100 may be separated from the middle line OP of the display panel 100.

The upper data lines UDL1 to UDL6 disposed in the upper half of the display panel 100 are connected to the first demultiplexers DEMUX1. The odd-numbered upper data lines UDL1, UDL3, and UDL5 are connected to the subpixels R1, G1, and B1 of the odd-numbered pixel line, for example, the first pixel line PL1. The data voltages (UD1, UD2, UD3) output from the first drive IC (DIC1) are transmitted to the first pixel line (PL1) through the first demultiplexers (DEMUX1) and the odd-numbered upper data lines (UDL1, UDL3, and UDL5). is supplied to the subpixels (R1, G1, B1).

The even-th upper data lines UDL2, UDL4, and UDL6 are connected to the sub-pixels R2, G2, and B2 of the even-th pixel line, for example, the second pixel line PL2. The data voltages (UD1, UD2, and UD3) output from the first drive IC (DIC1) are transmitted to the second pixel line (PL2) through the first demultiplexers (DEMUX1) and the even upper data lines (UDL2, UDL4, and UDL6). is supplied to the subpixels (R2, G2, B2).

The lower data lines BDL1 to BDL6 disposed in the lower half of the display panel 100 are connected to the second demultiplexers DEMUX2. The odd-numbered lower data lines (BDL1, BDL3, BDL5) are the odd-numbered pixel lines, for example, the subpixels (Rn-1, Gn-1, Bn-1) of the n-1th pixel line (PLn-1). connected to The data voltages (BD1, BD2, BD3) output from the second drive IC (DIC2) are transmitted to the n-1th pixel line ( It is supplied to the subpixels (Rn-1, Gn-1, Bn-1) of PLn-1).

The even-th lower data lines BDL2, BDL4, and BDL6 are connected to the sub-pixels Rn, Gn, and Bn of the even-th pixel line, for example, the n-th pixel line PLn. The data voltages (BD1, BD2, BD3) output from the second drive IC (DIC2) are connected to the n-th pixel line (PLn) through the second demultiplexers (DEMUX2) and the even-th lower data lines (BDL2, BDL4, BDL6). is supplied to the subpixels (Rn, Gn, Bn).

The first demultiplexer (DEMUX1) includes at least first and second transistors (UT1 and UT2). The first transistor (UT1) is turned on according to the pulse of the first selection signal (UMUX1) and transmits the data voltages (UD1, UD2, UD3) from the first drive IC (DIC1) to the odd-numbered upper data lines (UDL1, UDL3). , UDL5). The first transistor (UT1) is connected to the first electrode to which the data voltages (UD1, UD2, and UD3) are applied, the gate electrode to which the first selection signal (UMUX1) is applied, and the odd-numbered upper data lines (UDL1, UDL3, and UDL5). It includes a connected second electrode. The second transistor (UT2) is turned on according to the pulse of the second selection signal (UMUX2) and transmits the data voltages (UD1, UD2, UD3) from the first drive IC (DIC1) to the upper data lines (UDL2, UDL4). , supplied to UDL6). The second transistor UT2 includes a first electrode to which the data voltages UD1, UD2, and UD3 of the pixel data are applied, a gate electrode to which the second selection signal UMUX2 is applied, and even-th upper data lines UDL2, UDL4, It includes a second electrode connected to UDL6).

The second demultiplexer DEMUX2 includes at least third and fourth transistors BT1 and BT2. The third transistor (BT1) is turned on according to the pulse of the third selection signal (BMUX1) and transmits the data voltages (BD1, BD2, BD3) from the second drive IC (DIC2) to the odd-numbered lower data lines (BDL1, BDL3). , BDL5). The third transistor BT1 has a first electrode to which the data voltages BD1, BD2, and BD3 of the pixel data are applied, a gate electrode to which the third selection signal BMUX1 is applied, and odd-numbered lower data lines BDL1, BDL3, It includes a second electrode connected to BDL5). The fourth transistor (BT2) is turned on according to the pulse of the fourth selection signal (BMUX2) and transmits the data voltages (BD1, BD2, BD3) from the second drive IC (DIC2) to the upper and lower data lines (BDL2, BDL4). , BDL6). The fourth transistor BT2 has a first electrode to which the data voltages BD1, BD2, and BD3 of the pixel data are applied, a gate electrode to which the fourth selection signal BMUX2 is applied, and even-th lower data lines BDL2, BDL4, It includes a second electrode connected to BDL6).

The demultiplexers (DEMUX1, DEMUX2) and the switch element of the pixel circuit, that is, the transistor, may be turned on according to the gate-on voltage, while they may be turned off according to the gate-off voltage.

FIG. 12 is a waveform diagram showing a method of controlling demultiplexers disposed on the display panel shown in FIG. 11. FIGS. 13A and 13B are diagrams showing an example in which paths of data voltages charged to subpixels alternate within one horizontal period.

Referring to FIGS. 11 to 13B, the transistors UT1 to BT2 of the demultiplexers DEMUX1 and DEMUX2 may be alternately driven within one horizontal period (1H). 1 Horizontal period (1H) can be divided into a first pixel driving period (P1) and a second pixel driving period (P2).

During the first and second pixel driving periods (P1, P2), pulses of the gate signals (UGATE1, BGATE1) synchronized with the data voltages (UD1, BD1) are generated as the gate-on voltage (VGL). Since the pulse width of the gate signals (UGATE1, BGATE1) is 1 horizontal period, the switch elements of the subpixels to which the gate signals (UGATE1, BGATE1) are applied are turned on for one horizontal period (1H).

During the first pixel driving period (P1), the first and fourth selection signals (UMUX1, BMUX2) are generated as pulses of the gate-on voltage (VGL), and the voltages of the second and third selection signals (UMUX2, BMUX1) are It is the gate-off voltage (VGH). Hereinafter, 'UGATE1' will be referred to as the first gate signal, and 'BGATE1' will be referred to as the second gate signal.

During the first pixel driving period (P1), the switch element of the first red subpixel (R1) is turned on according to the gate-on voltage (VGL) of the first gate signal (UGATE1), and at the same time, the n-th red subpixel (Rn) The switch element of is turned on according to the gate-on voltage (VGL) of the second gate signal (BGATE1). At the same time, as shown in FIG. 13A, the first and fourth transistors UT1 and BT2 of the demultiplexers DEMUX1 and DEMUX2 are turned on.

During the first pixel driving period P1, as shown in FIG. 13A, the data voltage UD1 output from the first drive IC DIC1 is connected to the switch of the first transistor UT1 and the first red subpixel R1. The first red subpixel (R1) is charged through the device. At the same time, the data voltage BD1 output from the second drive IC DIC2 is charged to the nth red subpixel Rn through the fourth transistor BT2 and the switch element of the nth red subpixel Rn. . In the first pixel driving period (P1), since the transmission path of the data voltage is short, there is almost no difference in the data voltage charge amount of the first and n-th red subpixels (R1, Rn), and the charge amount increases, so that the luminance increases uniformly. You can.

Subsequently, during the second pixel driving period (P2), the second and third selection signals (UMUX2, BMUX1) are generated as pulses of the gate-on voltage (VGL), and the voltages of the first and fourth selection signals (UMUX1, BMUX2) This is the gate-off voltage (VGH).

During the second pixel driving period P2, the switch element of the second red subpixel R2 is turned on according to the gate-on voltage VGL of the first gate signal UGATE1, and at the same time, the n-1th red subpixel ( The switch element (Rn-1) is turned on according to the gate-on voltage (VGL) of the second gate signal (BGATE1). At the same time, as shown in FIG. 13A, the second and third transistors UT2 and BT1 of the demultiplexers DEMUX1 and DEMUX2 are turned on.

During the second pixel driving period P2, as shown in FIG. 13B, the data voltage UD1 output from the first drive IC DIC1 is connected to the switch of the second transistor UT2 and the second red subpixel R2. The second red subpixel R2 is charged through the device. At the same time, the data voltage BD1 output from the second drive IC DIC2 is transmitted through the third transistor BT1 and the switch element of the n-1 red subpixel Rn-1. (Rn-1) is charged. In the second pixel driving period (P2), since the transmission path of the data voltage is short, there is almost no difference in the data voltage charge amount of the second and n-1th red subpixels (R2, Rn-1), and the charge amount increases, reducing the luminance. It can be raised evenly.

FIG. 14 is a circuit diagram showing an example of a pixel circuit of sub-pixels adjacent above and below the odd-numbered pixel line and the even-numbered pixel line. In FIG. 14 , the first pixel circuit PXL1 may be a pixel circuit for driving the light emitting element EL of the first red subpixel R1 in the above-described embodiment. The second pixel circuit PXL2 may be a pixel circuit for driving the light emitting element EL of the second red subpixel R2 in the above-described embodiment. In Figure 14, the demultiplexers (DEMUX1, DEMUX2) and drive ICs (DIC1, DIC2) are omitted.

Referring to FIG. 14, each of the first and second pixel circuits (PXL1 and PXL2) includes a light emitting element (EL), a driving element (DT) that supplies current to the light emitting element (EL), and a pulse of the gate signal (GATE1). In response to a switch element (M01) connecting the data lines (DL1, DL1) to the gate electrode of the driving element (DT), and a capacitor (Cst) connected between the gate electrode of the driving element (DT) and the second electrode. do. The driving element (DT) and the switch element (M01) may be implemented with n-channel transistors, but are not limited thereto.

In the first pixel circuit PXL1, the driving element DT drives the light emitting element EL by supplying current to the light emitting element EL according to the gate-source voltage Vgs. The driving element DT is connected to the first electrode to which the pixel driving voltage EVDD is applied, the gate electrode to which the data voltages UD1 and BD1 are applied through the first switch element MO1, and the anode electrode of the light emitting element EL. It includes a connected second electrode. The switch element M01 includes a first electrode connected to the first data line DL1, a gate electrode to which a pulse of the gate signal GATE1 is applied, and a second electrode connected to the gate electrode of the driving element DT. The switch element (M01) is turned on according to the gate-on voltage of the gate signal (GATE1). The capacitor Cst is connected between the gate electrode and the source electrode of the driving element DT to maintain the gate-source voltage Vgs of the driving element DT.

In the second pixel circuit PXL2, the driving element DT drives the light emitting element EL by supplying current to the light emitting element EL according to the gate-source voltage Vgs. The driving element DT is connected to the first electrode to which the pixel driving voltage EVDD is applied, the gate electrode to which the data voltages UD1 and BD1 are applied through the first switch element MO1, and the anode electrode of the light emitting element EL. It includes a connected second electrode. A pixel base voltage (EVSS) is applied to the cathode electrode of the light emitting element (EL). The switch element M01 includes a first electrode connected to the second data line DL2, a gate electrode to which a pulse of the gate signal GATE1 is applied, and a second electrode connected to the gate electrode of the driving element DT. The switch element (M01) is turned on according to the gate-on voltage of the gate signal (GATE1). The capacitor Cst is connected between the gate electrode and the source electrode of the driving element DT to maintain the gate-source voltage Vgs of the driving element DT.

The light-emitting device may be implemented as an Organic Light Emitting Diode (OLED). OLED includes an organic compound layer formed between an anode electrode and a cathode electrode. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer. EIL) may be included, but is not limited thereto. When voltage is applied to the anode and cathode electrodes of the OLED, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) are moved to the emitting layer (EML), forming excitons, and visible light is emitted from the emitting layer (EML). It is released. OLED may have a tandem structure in which multiple light emitting layers are stacked. OLED with a tandem structure can improve pixel brightness and lifespan.

There may be differences in the electrical characteristics of driving elements between pixels due to process deviations and device characteristic deviations resulting from the manufacturing process of the display panel 100, and these differences may become larger as the driving time of the pixels elapses. To compensate for differences in electrical characteristics of driving elements between pixels, internal compensation technology or external compensation technology may be applied to the organic light emitting display device. Internal compensation technology uses an internal compensation circuit implemented in each pixel circuit to sample the threshold voltage (Vth) of the driving element (DT) for each sub-pixel and compensates the gate-source voltage (Vgs) of the driving element by the threshold voltage. do. External compensation technology uses an external compensation circuit to sense the current or voltage of driving elements that change according to the electrical characteristics of the driving elements in real time. External compensation technology compensates in real time for the deviation (or change) in the electrical characteristics of the driving element in each pixel by modulating the pixel data (digital data) of the input image by the deviation (or change) in the electrical characteristics of the driving element sensed for each pixel.

15 is a circuit diagram showing an example of a pixel circuit including an internal compensation circuit. FIG. 16 is a waveform diagram showing the internal compensation method of the pixel circuit shown in FIG. 15. In Figure 16, 'Vdata' is the data voltage (UD1, BD1) in the above-described embodiment, and 'Vth' is the threshold voltage of the driving element (DT).

Referring to FIG. 15, each of the first and second pixel circuits (PXL1 and PXL2) includes a light emitting element (EL), a driving element (DT), a plurality of switch elements (M1 to M9), a capacitor (Cst), etc. Includes. The driving element (DT) and the switch elements (M1 to M9, DT) can be implemented as p-channel transistors.

The first pixel circuit PXL1 is connected to the first data line DL1 to which the data voltages UD1 and BD1 are applied and to gate lines to which the gate signals S1N, S2N, and EM are applied. The pixel circuit has a first constant voltage node to which a pixel driving voltage (EVDD) is applied, a second constant voltage node to which a pixel base voltage (EVSS) is applied, a third constant voltage node to which an initialization voltage (Vini) is applied, and a reference voltage (Vref). It is connected to power nodes to which direct current voltage (or constant voltage) is applied, such as the fourth constant voltage node. Power lines to which constant voltage nodes are connected on the display panel may be commonly connected to all pixels.

The pixel driving voltage EVDD is higher than the maximum voltage of the data voltage VDATA and is set to a voltage that allows the driving element DT to operate in the saturation region. The initialization voltage (Vini) and the reference voltage (Vref) may be set to a voltage that is lower than the pixel driving voltage (EVDD) and higher than the pixel base voltage (EVSS). The gate-on voltage (VGH) may be set to a voltage higher than the pixel driving voltage (EVDD), and the gate-off voltage (VGL) may be set to a voltage lower than the pixel base voltage (EVSS). For example, the driving voltage applied to the pixels is EVDD=2.8[V], EVSS=-10[V], VGH=7[V], VGL=-13[V], Vini=-5[V], Vref=-3[V] may be set, but is not limited to this.

The gate signals (S1N, S2N, EM) include pulses that swing between the gate-on voltage (VGH) and the gate-off voltage (VGL). The gate signals S1N, S2N, and EM include a first gate signal S1N, a second gate signal S2N, and a third gate signal EM. In FIG. 16, “and S2N-1” are first and second gate signals applied to previous pixel lines scanned prior to pixel lines on which the first and second pixel circuits PXL1 and PXL2 are arranged.

The driving period of the pixel circuit may be determined by the waveforms of the gate signals S1N, S2N, and EM. The driving period of the pixel circuit can be divided into an initialization period (Ti), a sampling period (Ts), and a light emission period (Tem), as shown in FIG. 16. All switch elements (M1 to M9) are turned off between the sampling period (Ts) and the emission period (Tem), and a holding period (Th) is set to secure more threshold voltage sensing time for the driving element (DT). It can be.

The voltage of the first gate signal S1N is generated as a pulse of the gate-on voltage (VGL) prior to the initialization period (Ti) and is the gate-on voltage (VGL) during the initialization period (Ti). The initialization period (Ti) is one horizontal period (1H). The pulse of the first gate signal S1N may be generated with a pulse width of 2 horizontal periods (2H). The voltage of the first gate signal (S1N) is the gate-off voltage during the remaining frame period excluding the two horizontal periods (2H) including the initialization period (Ti). The fifth and ninth switch elements M5 and M9 are turned on in response to the pulse of the first gate signal S1N.

The voltage of the second gate signal S2N is generated as a pulse of the gate-on voltage VGL during the sampling period Ts. The pulse of the second gate signal S2N may be generated with a pulse width of 2 horizontal periods (2H). In this case, the sampling period (Ts) is 2 horizontal periods (2H). The voltage of the second gate signal S2N is the gate-off voltage during the remaining frame period excluding the sampling period Ti. The first, second, sixth, and eighth switch elements M1, M2, M6, and M8 are turned on in response to the pulse of the second gate signal S2N.

The voltage of the third gate signal EM is generated as a pulse of the gate-off voltage VGH for 4 horizontal periods from the start of the sampling period Tin to immediately before the emission period Tem. The voltage of the third gate signal (EM) is the gate-on voltage (VGH) during the remaining frame periods excluding the four horizontal periods. During the emission period (EM), the third gate signal (EM) may be generated as a pulse width modulation (PWM) pulse. The duty ratio of the PWM pulse may change depending on the digital brightness value (hereinafter referred to as 'DBV'). During the emission period (EM), the PWM pulse adjusts the lighting and turning off ratio of the light emitting element (EL), that is, the emission duty, to minimize afterimages when expressing low gray levels and improve the luminance uniformity of low gray levels to improve the low gray level expression of pixels. can be improved and the leakage current of pixels can be reduced. The third, fourth, and seventh switch elements M3, M4, and M7 are turned on in response to the gate-on voltage VGL of the third gate signal EM.

The driving element DT drives the light emitting element EL by generating a current flowing through the light emitting element EL according to the gate-source voltage Vgs. The driving element DT includes a first electrode connected to the first node DRS, a gate electrode connected to the second node DRG, and a second electrode connected to the third node DRD.

The anode electrode of the light emitting element EL is connected to the fourth node n4, and the cathode electrode is connected to the second constant voltage node to which the pixel base voltage EVSS is applied. The capacitor Cst is connected between the second node DRG and the fifth node n5.

In each of the first and second pixel circuits (PXL1 and PXL2), the first switch element (M1) is turned on according to the gate-on voltage (VGL) of the second gate signal (S2N) to connect to the second node (DRG) and connect the third node (DRD). The first switch element M1 includes a first electrode connected to the second node DRG, a gate electrode connected to the second gate line to which the second gate signal S2N is applied, and a second electrode connected to the third node DRD. Contains electrodes.

The second switch element M2 of the first pixel circuit PXL1 is turned on according to the gate-on voltage VGL of the second gate signal S2N to connect the first data line DL1 to the first node DRS. Connect to The second switch element M2 of the first pixel circuit PXL1 includes a first electrode connected to the first data line DL1, a gate electrode connected to the second gate line to which the second gate signal S2N is applied, and a second switch element M2. 1 includes a second electrode connected to the node (DRS).

The second switch element M2 of the second pixel circuit PXL2 is turned on according to the gate-on voltage VGL of the second gate signal S2N to connect the second data line DL2 to the first node DRS. Connect to The second switch element M2 of the second pixel circuit PXL2 includes a first electrode connected to the second data line DL2, a gate electrode connected to the second gate line to which the second gate signal S2N is applied, and a second switch element M2. 1 includes a second electrode connected to the node (DRS).

In each of the first and second pixel circuits (PXL1 and PXL2), the third switch element (M3) is turned on according to the gate-on voltage (VGL) of the third gate signal (EM) to generate the pixel driving voltage (EVDD). is supplied to the first node (DRS). The third gate signal EM is supplied to the pixel circuits PXL1 and PXL2 through the third gate line. The third switch element M3 includes a first electrode connected to a first constant voltage node to which the pixel driving voltage EVDD is applied, a gate electrode connected to a third gate line to which the third gate signal EM is applied, and a first node. and a second electrode connected to (DRS).

In each of the first and second pixel circuits (PXL1 and PXL2), the fourth switch element (M4) is turned on according to the gate-on voltage (VGL) of the third gate signal (EM) to connect to the third node (DRD). Connect to the fourth node (n4). The fourth switch element M4 includes a first electrode connected to the third node DRD, a gate electrode connected to the third gate line to which the third gate signal EM is applied, and a second electrode connected to the fourth node n4. Contains electrodes.

In each of the first and second pixel circuits (PXL1, PXL2), the fifth switch element (M5) is turned on according to the gate-on voltage (VGL) of the first gate signal (S1N) to set the initialization voltage (Vini). Applies to the second node (DRG). The fifth switch element M5 includes a first electrode connected to the second node DRG, a gate electrode connected to the first gate line to which the first gate signal S1N is applied, and a third electrode to which the initialization voltage Vini is applied. and a second electrode connected to the constant voltage node.

In each of the first and second pixel circuits (PXL1 and PXL2), the sixth switch element (M6) is turned on according to the gate-on voltage (VGL) of the second gate signal (S2N) to set the initialization voltage (Vini). It is applied to the fourth node (n4). The sixth switch element M6 includes a first electrode connected to a third constant voltage node to which an initialization voltage (Vini) is applied, a gate electrode connected to a second gate line to which a second gate signal (S2N) is applied, and an initialization voltage (Vini). It includes a second electrode connected to the applied third constant voltage node.

In each of the first and second pixel circuits (PXL1 and PXL2), the seventh switch element (M7) is turned on according to the gate-on voltage (VGL) of the third gate signal (EM) to generate the pixel driving voltage (EVDD). is supplied to the fifth node (n5). The seventh switch element M7 includes a first electrode connected to the first constant voltage node to which the pixel driving voltage EVDD is applied, a gate electrode connected to the third gate line to which the third gate signal EM is applied, and a fifth node. It includes a second electrode connected to (n5).

In each of the first and second pixel circuits PXL1 and PXL2, the eighth switch element M8 is turned on according to the gate-on voltage VGL of the second gate signal S2N to set the reference voltage Vref. It is supplied to the fifth node (n5). The eighth switch element M8 includes a first electrode connected to the fourth constant voltage node to which the reference voltage Vref is applied, a gate electrode connected to the second gate line to which the second gate signal S2N is applied, and a fifth node ( It includes a second electrode connected to n5).

The ninth switch element M9 is turned on according to the gate-on voltage (VGL) of the first gate signal (S1N) and supplies the reference voltage (Vref) to the fifth node (n5). The ninth switch element M9 includes a first electrode connected to the fourth constant voltage node to which the reference voltage Vref is applied, a gate electrode connected to the first gate line to which the first gate signal S1N is applied, and a fifth node ( It includes a second electrode connected to n5).

Referring to FIG. 13, during the initialization period Ti, the voltage of the first gate signal S1N is the gate-on voltage VGL, and the voltages of the second gate signal S2N and the N-th third gate signal EM are It is the gate-off voltage (VGH). Accordingly, during the initialization period Ti, the fifth and ninth switch elements M5 and M9 are turned on, while the other switch elements M1 to M4 and M6 to M8 are turned off.

In the initialization period Ti, the voltage of the first node DRS, that is, the first electrode voltage of the driving element DT, is floating because the second and third switch elements M2 and M3 are in the off state. It is a state. The voltage of the second node DRG is initialized to the first initialization voltage Vini1 because the fifth switch element M5 is turned on during the initialization period Ti. The voltage of the fifth node n5 is the reference voltage Vref because the ninth switch element M9 is turned on during the initialization period Ti.

During the sampling period Ts, the voltage of the second gate signal S2N is the gate-on voltage VGL, and the voltages of the first and third gate signals S1N and EM are the gate-off voltage VGH. During the sampling period Ts, the data voltage Vdata of the pixel data is output from the first and second drive ICs DIC1 and DIC2 to the data lines DL1 and DL2 through the demultiplexers DEMUX1 and DEMUX2. supplied. In the sampling period Ts, the first, second, sixth, and eighth switch elements (M1, M2, M6, M8) are turned on, while the other switch elements (M3, M4, M5, M7, M9) are turned off.

In the sampling period (Ts), since the second node (DRG) and the third node (DRD) are connected through the first switch element (M1) in the sampling period (Ts), the third node (DRD) is connected through the driving element (DT). When the voltage of DRD increases to the data voltage Vdata, the voltage of the second node DRG increases. During the sampling period Ts, when the gate voltage of the driving element DT increases and reaches Vdata-lVthl, the driving element DT is turned off. When the holding period (Th) ends, Vref - (Vdata - lVthl) is stored in the capacitor (Cst) and the threshold voltage (Vth) of the driving element (DT) is sampled in the capacitor (Cst).

During the holding period (Th), the first to third gate signals (S1N, S2N, EM) maintain the gate-off voltage (VGH) so that all switch elements (M1 to M9) remain in an off state. During the holding period Th, the rising threshold voltage sensing operation of the driving element DT is maintained until the voltage of the second node DRG reaches Vdata-lVthl.

During the light emission period Tem, the voltage of the third gate signal EM is the gate-on voltage VGL, and the voltages of the first and second gate signals S1N and S2N are the gate-off voltage VGH. During the light emission period (Tem), the third, fourth, and seventh switch elements (M3, M4, M7) are turned on, while the remaining switch elements (M1, M2, M5, M6, M8, M9) is turned off.

During the light emission period Tem, the pixel driving voltage EVDD is supplied to the first and fifth nodes DRD and n5 through the third and seventh switch elements M2 and M7. During the light emission period Tem, the voltage of the second node DRG, that is, the gate voltage of the driving element DT, changes to EVDD - Vref + Vdata - lVthl. During the light emission period (Tem), the light emitting element (EL) is driven by the current (I _OLED ) generated according to the gate-source voltage (Vgs) of the driving element (DT) and emits light with a luminance corresponding to the grayscale value of the pixel data. It can be. As can be seen from the equation below, the current (I _OLED ) flowing to the light emitting element (EL) through the driving element (DT) is not affected by the threshold voltage (Vth) of the driving element (DT) and drives the pixel. It is not affected by changes in pixel driving voltage (EVDD) due to IR drop in voltage (EVDD).

Here, K is a proportionality constant determined by the charge mobility of the driving element DT, parasitic capacitance, and channel capacitance. Vgs is the voltage between the gate and source of the driving element (DT).

Since the contents of the specification described in the problem to be solved, the means to solve the problem, and the effect described above do not specify the essential features of the claim, the scope of the claim is not limited by the matters described in the content of the specification.

Although embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be made without departing from the technical spirit of the present invention. . Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but are for illustrative purposes, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive. The scope of protection of the present invention should be interpreted in accordance with the claims, and all technical ideas within the equivalent scope should be interpreted as being included in the scope of rights of the present invention.

100: display panel 200, 300: data driver
210, 310: distribution unit 410, 420: gate driver
500: Timing controller 600: Power unit
OPL: Odd pixel line EPL: Even pixel line
DEMUX1: first demultiplexer DEMUX2: second demultiplexer
UMUX1: first selection signal UMUX2: second selection signal
BMUX1: Third selection signal BMUX2: Fourth selection signal
UT1: first transistor UT2: second transistor
BT1: Third transistor BT2: Fourth transistor
DIC1: 1st drive IC DIC2: 2nd drive IC
DL1, DL2: data line GL1: gate line
GATE1, S1N, S2N, EM: Gate signal EL: Light emitting element
DT: driving element Cst: first capacitor
M01, M1~M9: Switch element of pixel circuit

Claims (16)

a plurality of data lines;
a plurality of gate lines crossing the data lines;
a plurality of pixel lines including a plurality of sub-pixels arranged in a line direction;
A first demultiplexer connected to the top of the data lines; and
Includes a second demultiplexer connected to the lower end of the data lines,
At least one of the gate lines is
A display panel including a gate line commonly connected to adjacent odd-numbered pixel lines and even-numbered pixel lines to transmit a gate signal to sub-pixels of the odd-numbered pixel lines and even-numbered pixel lines. According to claim 1,
The first demultiplexer,
a first transistor that supplies a 1-1 data voltage from a first output terminal of the first drive IC to the top of the first data line in response to a first selection signal during the first pixel driving period; and
A second transistor for supplying a 2-1 data voltage from a first output terminal of the first drive IC to an upper end of a second data line in response to a second selection signal during a second pixel driving period,
The second demultiplexer,
a third transistor for supplying a 1-2 data voltage from a first output terminal of a second drive IC to a lower end of the first data line in response to a third selection signal during the second pixel driving period; and
A display including a fourth transistor for supplying the 1-2 data voltage from the first output terminal of the second drive IC to the lower end of the second data line in response to a fourth selection signal during the first pixel driving period. panel. According to claim 2,
The first pixel driving period is a scan period within the M (M is a natural number) frame period,
The display panel wherein the second pixel driving period is a scan period within the M+1th frame period. According to claim 2,
The first pixel driving period is a first scan period divided within one horizontal period,
The display panel wherein the second pixel driving period is a second scan period after the first scan period within the one horizontal period. According to claim 2,
The odd pixel line is,
A first sub-pixel configured to charge the 1-1 data voltage during the first pixel driving period and to charge the 1-2 data voltage during the second pixel driving period,
The superior pixel line is,
a second sub-pixel charging the 2-2 data voltage during the first pixel driving period and charging the 2-1 data voltage during the second pixel driving period;
The first and second subpixels are vertically adjacent to each other in one column line where the odd-numbered pixel line intersects the even-numbered pixel line. The method according to any one of claims 1 to 5,
Each of the subpixels is,
light emitting device;
a driving element that supplies current to the light emitting element;
A display panel including a switch element that is turned on in synchronization with the transistors of the first and second demultiplexers and supplies a data voltage from the data line to the driving element. According to claim 1,
A display panel in which the data lines are separated in the middle of the display panel. According to claim 7,
The pixel lines are,
first and second pixel lines disposed in the upper half of the display panel and adjacent to each other;
disposed in the lower half of the display panel and including adjacent n-1th (n is a positive integer of 4 or more) and nth pixel lines,
The first demultiplexer alternately supplies the data voltage from the first drive IC to a first upper data line connected to the first pixel line and a second upper data line connected to the second pixel line,
The display panel wherein the second demultiplexer alternately supplies data voltage from the second drive IC to a first lower data line connected to the n-1th pixel line and a second lower data line connected to the second pixel line. A display panel including a plurality of pixel lines where a plurality of data lines and a plurality of gate lines intersect and a plurality of subpixels arranged in a line direction;
a first drive IC disposed on the top of the display panel to output a data voltage to be charged to the sub-pixels;
a first demultiplexer disposed between the first drive IC and upper ends of the data lines;
a second drive IC disposed at the bottom of the display panel to output a data voltage to be charged to the sub-pixels;
a second demultiplexer disposed between the second drive IC and lower ends of the data lines; and
A gate driver disposed on the display panel and sequentially outputting a gate signal to the gate lines,
At least one of the gate lines is
A display device comprising a gate line commonly connected to adjacent odd-numbered pixel lines and even-numbered pixel lines to transmit the gate signal to sub-pixels of the odd-numbered pixel line and even-numbered pixel lines. According to clause 9,
The first demultiplexer,
a first transistor that supplies a 1-1 data voltage from a first output terminal of the first drive IC to an upper end of a first data line in response to a first selection signal during a first pixel driving period; and
A second transistor for supplying a 2-1 data voltage from a first output terminal of the first drive IC to an upper end of a second data line in response to a second selection signal during a second pixel driving period,
The second demultiplexer,
a third transistor supplying a 1-2 data voltage from a first output terminal of the second drive IC to a lower end of the first data line in response to a third selection signal during the second pixel driving period; and
A display including a fourth transistor for supplying the 1-2 data voltage from the first output terminal of the second drive IC to the lower end of the second data line in response to a fourth selection signal during the first pixel driving period. Device. According to claim 10,
The first pixel driving period is a scan period within the M (M is a natural number) frame period,
The second pixel driving period is a scan period within the M+1th frame period. According to claim 10,
The first pixel driving period is a first scan period divided within one horizontal period,
The second pixel driving period is a second scan period after the first scan period within the one horizontal period. According to claim 10,
The odd pixel line is,
A first sub-pixel configured to charge the 1-1 data voltage during the first pixel driving period and to charge the 1-2 data voltage during the second pixel driving period,
The superior pixel line is,
a second sub-pixel charging the 2-2 data voltage during the first pixel driving period and charging the 2-1 data voltage during the second pixel driving period;
The first and second subpixels are vertically adjacent to one column line where the odd-numbered pixel line intersects the even-numbered pixel line. The method according to any one of claims 9 to 13,
Each of the subpixels is,
light emitting device;
a driving element that supplies current to the light emitting element;
A display device including a switch element that is turned on in synchronization with the transistors of the first and second demultiplexers and supplies a data voltage from the data line to the driving element. According to clause 9,
A display device in which the data lines are separated in the middle of the display panel. According to claim 15,
The pixel lines are,
first and second pixel lines disposed in the upper half of the display panel and adjacent to each other;
disposed in the lower half of the display panel and including adjacent n-1th (n is a positive integer of 4 or more) and nth pixel lines,
The first demultiplexer alternately supplies the data voltage from the first drive IC to a first upper data line connected to the first pixel line and a second upper data line connected to the second pixel line,
The second demultiplexer alternately supplies the data voltage from the second drive IC to a first lower data line connected to the n-1th pixel line and a second lower data line connected to the second pixel line. .