KR20230034824A - Pixel circuit and display device including the same - Google Patents

Abstract

According to an embodiment, a pixel circuit, for improving data charging capacity, and a display device including the same are disclosed. The pixel circuit according to the embodiment comprises: a driving element including a first electrode connected to a first power line to which a pixel driving voltage is applied, a gate electrode connected to a first node, and a second electrode connected to a second node; a first switch element including a first electrode connected to a second power line to which a data voltage is applied, a gate electrode to which a first scan pulse is applied, and a second electrode connected to the first node; a second switch element including a first electrode connected to the second power line, a gate electrode to which a second scan pulse is applied, and a second electrode connected to the first node; a light-emitting element including an anode electrode connected to the second node and a cathode electrode connected to a third power line to which a low-potential power supply voltage is applied; and a capacitor connected between the first node and the second node.

Description

Pixel circuit and display device including the same {PIXEL CIRCUIT AND DISPLAY DEVICE INCLUDING THE SAME}

The present invention relates to a pixel circuit and a display device including the same.

Electroluminescence displays can be divided into inorganic light emitting displays and organic light emitting displays according to the material of the light emitting layer. An active matrix type organic light emitting display includes an organic light emitting diode (OLED) that emits light by itself, and has a fast response speed, high luminous efficiency, luminance, and viewing angle. There are advantages. Organic Light Emitting Diode (OLED) is formed in each pixel of the organic light emitting display device. The organic light emitting display device has a fast response speed, excellent luminous efficiency, luminance, viewing angle, etc., as well as black gradation. Since it can be expressed in complete black, the contrast ratio and color gamut are excellent.

A pixel circuit of a field emission display device includes an OLED used as a light emitting element and a driving element for driving the OLED.

A driving frequency applied to such a field emission display device tends to gradually increase. For example, when the driving frequency increases from 120HZ to 240HZ, one horizontal period (1H) becomes shorter. When one horizontal period is shortened, a data filling rate in a pixel circuit decreases, and thus luminance may decrease. Therefore, methods capable of improving data charging capability even when the driving frequency applied to the field emission display device is increased are required.

The present invention aims to address the aforementioned needs and/or problems.

The present invention provides a pixel circuit capable of improving data charging capability and a display device including the same.

The objects of the present invention are not limited to the tasks mentioned above, and other tasks not mentioned will be clearly understood by those skilled in the art from the following description.

A pixel circuit according to an embodiment of the present invention includes a driving element including a first electrode connected to a first power supply line to which a pixel driving voltage is applied, a gate electrode connected to a first node, and a second electrode connected to a second node; a first switch element including a first electrode connected to a second power supply line to which a data voltage is applied, a gate electrode to which a first scan pulse is applied, and a second electrode connected to the first node; a second switch element including a first electrode connected to the second power line, a gate electrode to which a second scan pulse is applied, and a second electrode connected to the first node; a light emitting element including an anode electrode connected to the second node and a cathode electrode connected to a third power supply line to which a low potential power supply voltage is applied; and a capacitor connected between the first node and the second node.

According to the present invention, two switch elements turned on according to the gate-on voltage of a scan pulse are connected in parallel between a data voltage line and a gate node of a driving element, thereby improving data charging capability even when the driving frequency increases. there is.

According to the present invention, double data charging control is possible by adjusting polling times of scan pulses applied to two switch elements, and thus, a data charging rate can be improved.

The effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims.

1 is a block diagram illustrating a display device according to an exemplary embodiment of the present invention.
FIG. 2 is a view showing a cross-sectional structure of the display panel shown in FIG. 1 .
3 is a circuit diagram showing a pixel circuit according to a first embodiment of the present invention.
4 is a circuit diagram showing a pixel circuit according to a second embodiment of the present invention.
5A and 5B are waveform diagrams illustrating gate signals applied to the pixel circuit shown in FIG. 4 .
6A to 6E are circuit diagrams showing the operation of the pixel circuit shown in FIG. 4 step by step.
7A to 7G are diagrams for explaining the polling time of the second scan pulse.
8A to 8C are waveform diagrams illustrating gate signals applied to the pixel circuit shown in FIG. 4 .
9 is a circuit diagram showing a pixel circuit according to a fourth embodiment of the present invention.
10 is a circuit diagram showing a pixel circuit according to a fifth embodiment of the present invention.
11A and 11B are waveform diagrams illustrating gate signals applied to the pixel circuit shown in FIG. 10 .

Advantages and features of the present invention, and methods of achieving them, will become clear with reference to the detailed description of the following embodiments taken in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and will be implemented in various forms different from each other, only these embodiments make the disclosure of the present invention complete, and common knowledge in the art to which the present invention pertains. It is provided to completely inform the person who has the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative, so the present invention is not limited to the details shown. Like reference numbers designate like elements throughout the specification. In addition, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted.

When 'includes', 'has', 'consists of', etc. mentioned in this specification is used, other parts may be added unless 'only' is used. In the case where a component is expressed in the singular, the case including the plural is included unless otherwise explicitly stated.

In interpreting the components, even if there is no separate explicit description, it is interpreted as including the error range.

In the case of a description of a positional relationship, for example, when the positional relationship of two parts is described as 'on ~', 'upon ~', '~ below', 'next to', etc., 'right' Or, unless 'directly' is used, one or more other parts may be located between the two parts.

In the description of the embodiment, first, second, etc. are used to describe various constituent elements, but these constituent elements are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below may also be the second component within the technical spirit of the present invention.

Like reference numbers designate like elements throughout the specification.

Features of various embodiments can be partially or entirely combined or combined with each other, technically various interlocking and driving are possible, and each embodiment can be implemented independently of each other or together in an association relationship.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Each of the pixels is divided into a plurality of sub-pixels having different colors for color implementation, and each of the sub-pixels includes a transistor used as a switch element or a driving element. Such a transistor may be implemented as a TFT (Thin Film Transistor).

A driving circuit of the display device writes pixel data of an input image into pixels. A driving circuit of a flat panel display device includes a data driver for supplying data signals to data lines and a gate driver for supplying gate signals to gate lines.

In the display device of the present invention, a pixel circuit may include a plurality of transistors. The transistor may be implemented as a TFT of a Metal-Oxide-Semiconductor FET (MOSFET) structure, and may be an oxide TFT including an oxide semiconductor or an LTPS TFT including low temperature poly silicon (LTPS). Hereinafter, transistors constituting the pixel circuit will be described based on an example implemented with an n-channel oxide TFT implemented with an oxide TFT, but the present invention is not limited thereto.

A transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. Within a transistor, carriers start flowing from the source. The drain is an electrode through which carriers exit the transistor. The flow of carriers in a transistor flows from the source to the drain. In the case of an n-channel transistor, since carriers are electrons, the source voltage has a voltage lower than the drain voltage so that electrons can flow from the source to the drain. The direction of current in an n-channel transistor is from drain to source. In the case of a p-channel transistor, since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-channel transistor, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain may change depending on the applied voltage. Therefore, the invention is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as first and second electrodes.

The gate signal can swing between a Gate On Voltage and a Gate Off Voltage. The gate-on voltage is set to a voltage higher than the threshold voltage of the transistor. The gate-off voltage is set to a voltage lower than the threshold voltage of the transistor.

A transistor is turned on in response to a gate-on voltage, while it is turned off in response to a gate-off voltage. In the case of an n-channel transistor, the gate-on voltage may be a gate high voltage (VGH and VEH), and the gate-off voltage may be a gate low voltage (VGL and VEH).

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following embodiments, the display device will be described mainly with an organic light emitting display device, but the present invention is not limited thereto.

FIG. 1 is a block diagram showing a display device according to an exemplary embodiment of the present invention, and FIG. 2 is a view showing a cross-sectional structure of the display panel shown in FIG. 1 .

Referring to FIGS. 1 and 2 , a display device according to an exemplary embodiment of the present invention includes a display panel 100, a display panel driver for writing pixel data to pixels of the display panel 100, and pixels and a power supply unit 140 generating power necessary for driving the display panel driving unit.

The display panel 100 may have a rectangular structure having a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. The display panel 100 includes a pixel array displaying an input image on a screen. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 crossing the data lines 102, and pixels arranged in a matrix form. The display panel 100 may further include power lines commonly connected to pixels. The power lines include a power line to which the pixel driving voltage ELVDD is applied, a power line to which the initialization voltage Vinit is applied, a power line to which the reference voltage Vref is applied, and a power line to which the low potential power voltage ELVSS is applied. can include These power lines are commonly connected to the pixels.

The pixel array includes a plurality of pixel lines L1 to Ln. Each of the pixel lines L1 to Ln includes one line of pixels disposed along the line direction X in the pixel array of the display panel 100 . Pixels arranged on one pixel line share gate lines 103 . Sub-pixels arranged in the column direction (Y) along the data line direction share the same data line 102 . One horizontal period (1H) is a time obtained by dividing one frame period by the total number of pixel lines (L1 to Ln).

The display panel 100 may be implemented as a non-transmissive display panel or a transmissive display panel. The transmissive display panel may be applied to a transparent display device in which an image is displayed on a screen and a real object in the background is visible.

The display panel may be made of a flexible display panel. The flexible display panel may be implemented as an OLED panel using a plastic substrate. The pixel array and light emitting elements of the plastic OLED panel may be disposed on an organic thin film adhered to a back plate.

Each of the pixels 101 may be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel for color implementation. Each of the pixels may further include a white sub-pixel. Each of the sub-pixels includes a pixel circuit. Hereinafter, a pixel may be interpreted as having the same meaning as a sub-pixel. Each of the pixel circuits is connected to data lines, gate lines, and power lines.

Pixels can be arranged as real color pixels and pentile pixels. A pentile pixel can implement a higher resolution than a real color pixel by driving two sub-pixels of different colors as one pixel 101 using a preset pixel rendering algorithm. The pixel rendering algorithm may compensate for insufficient color expression in each pixel with the color of light emitted from an adjacent pixel.

Touch sensors may be disposed on the screen of the display panel 100 . The touch sensors are on-cell type or add-on type, and are arranged on the screen of the display panel or in-cell type touch sensors embedded in the pixel array (AA). can be implemented as

As shown in FIG. 2 , the display panel 100 includes a circuit layer 12, a light emitting element layer 14, and an encapsulation layer 16 stacked on a substrate 10 when viewed in a cross-sectional structure. can include

The circuit layer 12 may include a pixel circuit connected to wires such as data lines, gate lines, and power lines, and a gate driver GIP connected to gate lines. The wiring and circuit elements of the circuit layer 12 may include a plurality of insulating layers, two or more metal layers separated with an insulating layer interposed therebetween, and an active layer including a semiconductor material.

The light emitting element layer 14 may include a light emitting element EL driven by a pixel circuit. The light emitting element EL may include a red (R) light emitting element, a green (G) light emitting element, and a blue (B) light emitting element. The light emitting element layer 14 may include a white light emitting element and a color filter. The light emitting elements EL of the light emitting element layer 14 may be covered by a protective layer including an organic layer and a protective layer.

An encapsulation layer 16 covers the light emitting element layer 14 so as to seal the circuit layer 12 and the light emitting element layer 14 . The encapsulation layer 16 may have a multi-insulation layer structure in which organic layers and inorganic layers are alternately stacked. The inorganic film blocks the penetration of moisture or oxygen. The organic layer flattens the surface of the inorganic layer. When the organic layer and the inorganic layer are stacked in multiple layers, the movement path of moisture or oxygen is longer than that of a single layer, so that penetration of moisture and oxygen affecting the light emitting element layer 14 can be effectively blocked.

A touch sensor layer formed on the encapsulation layer 16 may be disposed. The touch sensor layer may include capacitive touch sensors that sense a touch input based on a change in capacitance before and after the touch input. The touch sensor layer may include metal wiring patterns and insulating layers forming capacitance of the touch sensors. Capacitance of the touch sensor may be formed between the metal wiring patterns. A polarizer may be disposed on the touch sensor layer. The polarizer may improve visibility and contrast ratio by converting polarization of external light reflected by the touch sensor layer and the metal of the circuit layer 12 . The polarizing plate may be implemented as a polarizing plate in which a linear polarizing plate and a phase retardation film are bonded together or a circular polarizing plate. A cover glass may be adhered on the polarizing plate.

The display panel 100 may further include a touch sensor layer and a color filter layer stacked on the encapsulation layer 16 . The color filter layer may include red, green, and blue color filters and a black matrix pattern. The color filter layer may absorb some wavelengths of light reflected from the circuit layer and the touch sensor layer to serve as a polarizer and increase color purity. In this embodiment, the light transmittance of the display panel PNL can be improved and the thickness and flexibility of the display panel PNL can be improved by applying the color filter layer 20 having higher light transmittance than that of the polarizer to the display panel. A cover glass may be adhered on the color filter layer.

The power supply unit 140 uses a DC-DC converter to generate DC power necessary for driving the pixel array of the display panel 100 and the display panel driver. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, and the like. The power supply unit 140 adjusts the level of a DC input voltage applied from a host system (not shown) to generate a gamma reference voltage (VGMA) and gate-on voltages (VGH, VEH). Constant voltages (or DC voltages) such as gate-off voltages (VGL, VEL), pixel driving voltages (ELVDD), low-potential power supply voltages (ELVSS), reference voltages (Vref), initialization voltages (Vinit), and anode voltages (Vano) can happen The gamma reference voltage VGMA is supplied to the data driver 110 . Gate-on voltages VGH and VEH and gate-off voltages VGL and VEL are supplied to the gate driver 120 . Constant voltages such as the pixel driving voltage ELVDD, the low potential power supply voltage ELVSS, the reference voltage Vref, the initialization voltage Vinit, and the anode voltage Vano are commonly supplied to the pixels.

The display panel driver writes pixel data of an input image into pixels of the display panel 100 under the control of a timing controller (TCON) 130 .

The display panel driver includes a data driver 110 and a gate driver 120 . The display panel driver may further include a demultiplexer array 112 disposed between the data driver 110 and the data lines 102 .

The demultiplexer array 112 sequentially supplies data voltages output from channels of the data driver 110 to the data lines 102 using a plurality of demultiplexers (DEMUX). The demultiplexer may include a plurality of switch elements disposed on the display panel 100 . When the demultiplexer is disposed between the output terminals of the data driver 110 and the data lines 102 , the number of channels of the data driver 110 may be reduced. The demultiplexer array 112 may be omitted.

The display panel driver may further include a touch sensor driver for driving touch sensors. The touch sensor driver is omitted in FIG. 1 . The data driving unit and the touch sensor driving unit may be integrated into one drive IC (Integrated Circuit). In a mobile device or a wearable device, the timing controller 130, the power supply unit 140, the data driver 110, the touch sensor driver, and the like may be integrated into one drive IC.

The display panel driver may operate in a low speed driving mode under the control of the timing controller 130 . The low-speed driving mode may be set to reduce power consumption of the display device when there is no change in the input image for a preset time by analyzing the input image. The low-speed driving mode can reduce power consumption of the display panel driver and the display panel 100 by lowering the refresh rate of pixels when a still image is input for a predetermined period of time or longer. The low-speed drive mode is not limited when a still image is input. For example, when the display device operates in a standby mode or when a user command or an input image is not input to the display panel driving circuit for a predetermined period of time or more, the display panel driving circuit may operate in a low speed driving mode.

The data driver 110 generates a data voltage by converting pixel data of an input image received as a digital signal from the timing controller 130 into a gamma compensation voltage for each frame period using a digital to analog converter (DAC). The gamma reference voltage (VGMA) is divided into gamma compensation voltages for each gray level through a voltage divider circuit and supplied to the DAC. The data voltage is output from each of the channels of the data driver 110 through an output buffer.

The gate driver 120 may be implemented as a gate in panel (GIP) circuit formed directly on the circuit layer 12 of the display panel 100 together with the TFT array and wires of the pixel array. The GIP circuit may be disposed on the bezel area (BZ), which is a non-display area of the display panel 100, or distributedly disposed within a pixel array where an input image is reproduced. The gate driver 120 sequentially outputs gate signals to the gate lines 103 under the control of the timing controller 130 . The gate driver 120 may sequentially supply the gate signals to the gate lines 103 by shifting the gate signals using a shift register. The gate signal may include a scan pulse, an emission control pulse (hereinafter referred to as “EM pulse”), an initialization pulse, and a sensing pulse.

The shift register of the gate driver 120 outputs a gate signal pulse in response to a start pulse and a shift clock from the timing controller 130 and shifts the pulse according to the shift clock timing. .

The timing controller 130 receives digital video data (DATA) of an input image and a timing signal synchronized therewith from the host system. The timing signal may include a vertical sync signal (Vsync), a horizontal sync signal (Hsync), a clock (CLK), and a data enable signal (DE). Since the vertical period and the horizontal period can be known by counting the data enable signal DE, the vertical sync signal Vsync and the horizontal sync signal Hsync can be omitted. The data enable signal DE has a period of one horizontal period (1H).

The host system may be any one of a television (TV) system, a tablet computer, a notebook computer, a navigation system, a personal computer (PC), a home theater system, a mobile device, a wearable device, and a vehicle system. The host system may scale an image signal from a video source according to the resolution of the display panel 100 and transmit it to the timing controller 13 together with a timing signal.

The timing controller 130 may control the operation timing of the display panel driver with the frame frequency of the input frame frequency Хi (i is a natural number) Hz by multiplying the input frame frequency by i in the normal driving mode. The input frame frequency is 60 Hz in the National Television Standards Committee (NTSC) method and 50 Hz in the Phase-Alternating Line (PAL) method. The timing controller 130 may lower the driving frequency of the display panel driving unit by lowering the frame frequency to a frequency between 1 Hz and 30 Hz in order to lower the refresh rate of pixels in the low-speed driving mode.

The timing controller 130 controls the data timing control signal for controlling the operation timing of the data driver 110 and the operation timing of the demultiplexer array 112 based on the timing signals Vsync, Hsync, and DE received from the host system. A gate timing control signal for controlling the operation timing of the gate driving unit 120 is generated. The timing controller 130 controls the operation timing of the display panel driver to synchronize the data driver 110 , the demultiplexer array 112 , the touch sensor driver, and the gate driver 120 .

The voltage level of the gate timing control signal output from the timing controller 130 is converted into gate-on voltages (VGH and VEH) and gate-off voltages (VGL and VEL) through a level shifter (not shown) to form a gate driver ( 120) can be supplied. The level shifter converts the low level voltage of the gate timing control signal into the gate off voltage (VGL, VEL) and converts the high level voltage of the gate timing control signal into the gate on voltage (VGH, VEH). ) is converted to The gate timing signal includes a start pulse and a shift clock.

3 is a circuit diagram showing a pixel circuit according to a first embodiment of the present invention.

Referring to FIG. 3 , the pixel circuit according to the first embodiment of the present invention includes a light emitting element EL, a driving element DT driving the light emitting element EL, a plurality of switch elements M01 and M02, and a capacitor. (Cst) may be included.

The light emitting element EL may be implemented as an OLED. An OLED includes an organic compound layer formed between an anode electrode and a cathode electrode. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer, EIL), but is not limited thereto. The anode electrode of the light emitting element EL is connected to the second node n2, and the cathode electrode is connected to the third power line PL3 to which the low-potential power supply voltage EVSS is applied. When a voltage is applied to the anode electrode and the cathode electrode of the light emitting element EL, holes passing through the hole transport layer HTL and electrons passing through the electron transport layer ETL are moved to the light emitting layer EML, and excitons are formed to form the light emitting layer EML. ), visible light is emitted.

The driving element DT drives the light emitting element EL by generating a current according to the gate-source voltage Vgs. The driving element DT includes a gate electrode connected to a first node n1, a first electrode connected to a first power line to which a pixel driving voltage is applied, and a second electrode connected to a second node n2.

The first switch element M01 is turned on according to the gate-on voltage VEH of the first scan pulse SCAN1 and applies the data voltage to the first node n1. The first switch element M1 includes a gate electrode to which the first scan pulse SCAN1 is applied, a first electrode connected to the second power line DL to which the data voltage is applied, and a second electrode connected to the first node n1. contains electrodes.

The second switch element M02 is turned on according to the gate-on voltage VEH of the second scan pulse SCAN2 and applies the data voltage to the first node n1. The second switch element M02 includes a gate electrode to which the second scan pulse SCAN2 is applied, a first electrode connected to the second power line DL to which the data voltage is applied, and a second electrode connected to the first node n1. contains electrodes.

When both the first switch element M01 and the second switch element M02 are turned on while the data voltage is applied, the first switch element M01 and the second switch element are connected in parallel to the second power line. Therefore, the total resistance on the equivalent circuit is reduced, and the data charging capability can be improved.

The first capacitor Cst is connected between the first node n1 and the second node n2 to store a threshold voltage. One side of the first capacitor Cst is connected to the first node n1 and the other side is connected to the second node n2.

4 is a circuit diagram showing a pixel circuit according to a second embodiment of the present invention, and FIGS. 5A and 5B are waveform diagrams showing gate signals applied to the pixel circuit shown in FIG. 4 .

Referring to FIG. 4 , the pixel circuit according to the second embodiment of the present invention includes a light emitting element EL, a driving element DT for driving the light emitting element EL, and a plurality of switch elements M01, M02, M03, M04), and a capacitor Cst. The driving element DT and the switch elements M01, M02, M03, M04, and M05 may be implemented as n-channel oxide TFTs.

The pixel circuit includes a first power line PL1 to which the pixel driving voltage EVDD is applied, a second power line DL to which the data voltage Vdata is applied, and a third power source to which the low-potential power supply voltage EVSS is applied. The line PL3, the fourth power line PL4 to which the initialization voltage Vinit is applied, the fifth power line RL to which the reference voltage Vref is applied, and the gate signals INIT, SENSE, SCAN1, and SCAN2 are It is connected to the applied gate lines.

The driving element DT drives the light emitting element EL by generating a current according to the gate-source voltage Vgs. The driving element DT includes a gate electrode connected to the first node n1, a first electrode connected to the first power line PL1 to which the pixel driving voltage EVDD is applied, and a second electrode connected to the second node n2. contains electrodes.

The first switch element M01 is turned on according to the gate-on voltage VEH of the first scan pulse SCAN1 and applies the data voltage to the first node n1. The first switch element M1 includes a gate electrode to which the first scan pulse SCAN1 is applied, a first electrode connected to the second power line DL to which the data voltage is applied, and a second electrode connected to the first node n1. contains electrodes.

The second switch element M02 is turned on according to the gate-on voltage VEH of the second scan pulse SCAN2 and applies the data voltage to the first node n1. The second switch element M02 includes a gate electrode to which the second scan pulse SCAN2 is applied, a first electrode connected to the second power line DL to which the data voltage is applied, and a second electrode connected to the first node n1. contains electrodes.

The third switch element M03 is turned on according to the gate-on voltage VGH of the initialization pulse INIT to apply the initialization voltage Vinit to the first node n1. The third switch element M03 includes a first electrode connected to the fourth power line PL4 to which the initialization voltage Vinit is applied, a gate electrode to which the initialization pulse INIT is applied, and a second electrode connected to the first node n1. contains electrodes.

The fourth switch element M04 is turned on according to the gate-on voltage VGH of the sensing pulse SENSE and supplies the reference voltage Vref to the second node n2. The fourth switch element M04 includes a first electrode connected to the second node n2, a gate electrode to which the sensing pulse SENSE is applied, and a second electrode connected to the fifth power line RL to which a reference voltage is applied. do.

The pixel circuit may be driven in the order of an initialization step (Ti), a sensing step (Ts), a data writing step (Tw), and a light emitting step (Tem), as shown in FIGS. 5A and 5B. In the initialization step Ti, the pixel circuit is initialized. In the sensing step Ts, the threshold voltage Vth of the driving element DT is sensed and stored in the first capacitor Cst. In the data writing step Tw, the data voltage Vdata of the pixel data is applied to the first node n1. After the voltage of the first and second nodes n1 and n2 increases in the boosting step Tboost, the light emitting element EL may emit light with a luminance corresponding to the grayscale value of the pixel data in the light emitting step Tem. .

The pixel circuit may equally apply the first scan pulse and the second scan pulse as shown in FIG. 5A, or may separately apply the first scan pulse and the second scan pulse differently as shown in FIG. 5B.

6A to 6E are circuit diagrams showing the operation of the pixel circuit shown in FIG. 4 step by step. Here, an operation according to driving timing as shown in FIG. 5B will be described.

As shown in FIG. 6A , in the initialization step Ti, the third and fourth switch elements M03 and M04 are turned on, and the first and second switch elements M01 and M02 are turned off. The initialization voltage Vinit is applied to the first node n1, and the reference voltage Vref is applied to the second node n2. At this time, the driving element DT is turned on, and the light emitting element EL is not turned on.

In the sensing step Ts, as shown in FIG. 6B, the third switch element MO3 maintains an on state so that the voltage of the second node n2 rises and the gate-source voltage of the driving element DT ( When Vgs reaches the threshold voltage Vth, the driving element DT is turned off and the threshold voltage Vth is stored in the first capacitor Cst. During the sensing step Ts, the sensing pulse SENSE applied to the third switch element MO3 may be generated in approximately 1.5 horizontal periods (1.5H).

During the hold period Th, the third switch element MO3 is turned off and the second node n2 and the third node n3 are floated to maintain the previous voltage. The hold period Th may be generated by approximately one horizontal period (1H).

In the data writing step Tw, the first and second switch elements M01 and M02 are turned on as shown in FIG. 6C. The data voltage Vdata of the pixel data is applied to the second node n2 so that the voltage of the second node n2 is changed by the data voltage Vdata. At this time, the data voltage Vdata of the pixel data is not applied through one switch element, but applied through the first and second switch elements M01 and M02 connected in parallel, so that charging characteristics may be improved. Both the first and second switch elements M01 and M02 maintain a turned-on state during the data writing step Tw. During the data writing step Tw, the scan pulse SCAN applied to the first and second switch elements M01 and M02 may be generated with approximately 0.7 horizontal period (0.7H). In the data writing step Tw, the first and second switch elements M01 and M02 are turned on. The data voltage Vdata of the pixel data is applied to the second node n2 so that the voltage of the second node n2 is changed by the data voltage Vdata. At this time, the data voltage Vdata of the pixel data is not applied through one switch element, but applied through the first and second switch elements M01 and M02 connected in parallel, so that charging characteristics may be improved. The first and second switch elements M01 and M02 are both turned on when the data writing step Tw starts, while the first and second switch elements M01 and M02 are turned off at different times. there is. That is, the first switch element M01 is turned off before the data writing step (Tw) ends, and the second switch element M02 is turned off when the data writing step (Tw) is finished. The reason why the turn-off timing is different is to prevent data mixing. At this time, the time point at which the first switch element M01 is turned off is fixed, and the time point at which the second switch element M02 is turned off may be variable.

In addition, the second scan pulse can reduce not only the polling time but also the polling time, and the polling time can be reduced through downward application of under driving.

7A to 7G are diagrams for explaining the polling time of the second scan pulse.

Referring to FIGS. 7A and 7B , it can be seen that when the falling time of the second scan pulse is different, the turn-off time of the second switch element is also different. As the polling time of the second scan pulse decreases, the turn-off time of the second switch device decreases.

Due to the reduction in the turn-off time of the second switch element, it is possible to turn off the second switch element before the next line is opened, thereby preventing data mixing, so that more effective charging time can be secured.

The second switch element is an auxiliary TFT for improving a charging rate, and polling time can be minimized through a size and load reduction compared to the first switch element and downward application of under-driving.

Referring to FIG. 7C , since the voltage level of the first scan pulse SACN1 and the second scan pulse SACN2 can be separated, the gate voltage of the second scan pulse SACN2 is lower than the gate low voltage of the first scan pulse SACN1. The low voltage may be low. That is, the voltage of the first scan pulse SACN1 swings between the first gate-on voltage VGH1 and the first gate-off voltage VGL1, and the voltage of the second scan pulse SACN2 swings between the first gate-on voltage (VGH1) and the first gate-off voltage (VGL1). VGH1) and a second gate-off voltage VGL2 lower than the first gate-off voltage VGL1.

When the difference between the gate high voltage VGH1 and the gate low voltage VGL2 of the second scan pulse SACN2 increases, the polling period of the second scan pulse SACN2 becomes short, so the polling time can be reduced.

Referring to FIG. 7D , since the voltage level of the first scan pulse SACN1 and the second scan pulse SACN2 can be separated, the gate voltage of the second scan pulse SACN2 is higher than the gate high voltage of the first scan pulse SACN1. High voltage can be high. That is, the voltage of the first scan pulse SACN1 swings between the first gate-on voltage VGH1 and the first gate-off voltage VGL, and the voltage of the second scan pulse SACN2 swings between the first gate-on voltage VGH1 and the first gate-off voltage VGL. It swings between the second gate-on voltage VGH2 higher than VGH1 and the first gate-off voltage VGL.

When the difference between the gate high voltage VGH2 and the gate low voltage VGL of the second scan pulse SACN2 increases, the polling period of the second scan pulse SACN2 becomes short, so the polling time can be reduced.

Referring to FIG. 7E , the voltage level of the first scan pulse SACN1 and the second scan pulse SACN2 can be separated, so that the gate low voltage of the second scan pulse is lower than the gate low voltage of the first scan pulse SACN1. , the gate high voltage of the second scan pulse SACN2 may be higher than the gate high voltage of the first scan pulse SACN1. That is, the voltage of the first scan pulse SACN1 swings between the first gate-on voltage VGH1 and the first gate-off voltage VGL1, and the voltage of the second scan pulse SACN2 swings between the first gate-on voltage (VGH1) and the first gate-off voltage (VGL1). It swings between a second gate-on voltage VGH2 higher than VGH1 and a second gate-off voltage VGL2 lower than first gate-off voltage VGL1.

When the difference between the gate high voltage VGH2 and the gate low voltage VGL2 of the second scan pulse SACN2 increases, the polling period of the second scan pulse SACN2 becomes short, so the polling time can be reduced.

Referring to FIG. 7F, since the polling time of the scan pulse of the (n−1)th line is shortened and the turn-off time of the switch element is shortened, the effective charging time in the nth row is increased and the data charging rate is improved. can

Referring to FIG. 7G, as the gate low voltage (VGL) of the second scan pulse is lowered, the difference between the gate high voltage (VGH) of the second scan pulse and the gate high voltage (VGH) of the second scan pulse is increased. This reduction may improve the data charging rate.

For example, when the gate low voltage (VGL) of the second scan pulse is -6V, the data filling rate is 12.7%, and when the gate low voltage (VGL) is -12V, the data filling rate is 53.7%, and the gate low voltage (VGL ) is -15V, the data charge rate is 66.1V, and when the gate low voltage (VGL) is -18V, the data charge rate is 74.3, showing that the charge rate is improved.

During the boosting period Tboost, the first, second, third, and fourth switch elements M01, M02, M03, and M04 are turned off. At this time, the voltages of the first and second nodes n1 and n2 are increased.

In the light emitting step Tem, as shown in FIG. 6D , the first, second, third, and fourth switch elements M01, M02, M03, and M04 maintain an off state. At this time, a current generated according to the voltage Vgs between the gate and source of the driving element DT, that is, the voltage between the first and second nodes n1 and n2 is supplied to the light emitting element EL so that the light emitting element EL may emit light.

In the embodiment, a case in which the same polling time of the scan pulse is applied to all pixels is described as an example, but is not necessarily limited thereto. That is, in the embodiment, the polling time of the scan pulse is applied differently for each gate line or each gate line group in consideration of the RC delay in the data line or the IR drop in the power supply lines (EVDD, EVSS). .

8A to 8C are waveform diagrams illustrating gate signals applied to the pixel circuit shown in FIG. 4 .

Referring to FIG. 8A , a second scan pulse may be applied with a different polling time for each gate line in consideration of an RC delay in a data line or an IR drop in power lines (EVDD and EVSS).

Referring to FIG. 8B , the second scan pulse may be applied with a different polling time for each gate line group in consideration of the RC delay in the data line or the IR drop in the power lines (EVDD and EVSS).

Referring to FIG. 8C, in consideration of the RC delay in the data line or the IR drop in the power lines (EVDD, EVSS), different rising times of the second scan pulse are applied for each gate line group, and the first scan pulse and the second scan pulse are applied. The overlapping section of scan pulses can be adjusted.

As shown in FIGS. 8A to 8C , the polling time or gate low voltage of the second scan pulse according to embodiments may vary in proportion to the RC delay or IR drop.

Here, a case of differently applying the gate low voltage of the second scan pulse is described, but is not necessarily limited thereto. That is, in the embodiment, at least one of the gate high voltage and the gate low voltage of the second scan pulse may be applied differently.

9 is a circuit diagram showing a pixel circuit according to a fourth embodiment of the present invention.

Referring to FIG. 9 , a pixel circuit according to a fourth embodiment of the present invention includes a light emitting element EL, a driving element DT for driving the light emitting element EL, a switch element M01, and a capacitor Cst. can do.

The light emitting element EL may be implemented as an OLED. An OLED includes an organic compound layer formed between an anode electrode and a cathode electrode. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer, EIL), but is not limited thereto. The anode electrode of the light emitting element EL is connected to the second node n2, and the cathode electrode is connected to the third power line PL3 to which the low-potential power supply voltage EVSS is applied. When a voltage is applied to the anode electrode and the cathode electrode of the light emitting element EL, holes passing through the hole transport layer HTL and electrons passing through the electron transport layer ETL are moved to the light emitting layer EML, and excitons are formed to form the light emitting layer EML. ), visible light is emitted.

The driving element DT drives the light emitting element EL by generating a current according to the gate-source voltage Vgs. The driving element DT includes a gate electrode connected to a first node n1, a first electrode connected to a first power line to which a pixel driving voltage is applied, and a second electrode connected to a second node n2.

The first switch element M01 is formed as a double gate and can be separately driven by the first scan pulse SCAN1 and the second scan pulse SCAN2. When formed as a double gate, the application of a gate voltage to the upper and lower surfaces of the active layer can bring about an effect of increasing carriers and increasing mobility, thereby improving current capability. Accordingly, when the first switch element M01 is turned on while the data voltage is applied, the data charging capacity may be improved due to the current capability characteristic of the first switch element M01 having a double gate structure.

The first capacitor Cst is connected between the first node n1 and the second node n2 to store a threshold voltage. One side of the first capacitor Cst is connected to the first node n1 and the other side is connected to the second node n2.

10 is a circuit diagram showing a pixel circuit according to a fifth embodiment of the present invention, and FIGS. 11A and 11B are waveform diagrams showing gate signals applied to the pixel circuit shown in FIG. 10 .

Referring to FIG. 10 , a pixel circuit according to a fifth embodiment of the present invention includes a light emitting element EL, a driving element DT for driving the light emitting element EL, and a plurality of switch elements M01, M02, and M03. , may include a capacitor Cst. The driving element DT and the switch elements M01, M02, and M03 may be implemented as n-channel oxide TFTs.

The pixel circuit includes a first power line PL1 to which the pixel driving voltage EVDD is applied, a second power line DL to which the data voltage Vdata is applied, and a third power source to which the low-potential power supply voltage EVSS is applied. The line PL3, the fourth power line PL4 to which the initialization voltage Vinit is applied, the fifth power line RL to which the reference voltage Vref is applied, and the gate signals INIT, SENSE, SCAN1, and SCAN2 are It is connected to the applied gate lines.

The driving element DT drives the light emitting element EL by generating a current according to the gate-source voltage Vgs. The driving element DT includes a gate electrode connected to the first node n1, a first electrode connected to the first power line PL1 to which the pixel driving voltage EVDD is applied, and a second electrode connected to the second node n2. contains electrodes.

The first switch element M01 is turned on according to the gate-on voltage VEH of the first scan pulse SCAN1 and the second scan pulse SCAN2 to apply the data voltage to the first node n1. The first switch element M1 includes a first gate electrode to which the first scan pulse SCAN1 is applied, a second gate electrode to which the second scan pulse SCAN1 is applied, and a second power line DL to which the data voltage is applied. It includes a first electrode connected to and a second electrode connected to the first node n1.

The second switch element M02 is turned on according to the gate-on voltage VGH of the initialization pulse INIT to apply the initialization voltage Vinit to the first node n1. The second switch element M02 includes a first electrode connected to the fourth power line PL4 to which the initialization voltage Vinit is applied, a gate electrode to which the initialization pulse INIT is applied, and a second electrode connected to the first node n1. contains electrodes.

The third switch element M03 is turned on according to the gate-on voltage VGH of the sensing pulse SENSE and supplies the reference voltage Vref to the second node n2. The third switch element M03 includes a first electrode connected to the second node n2, a gate electrode to which the sensing pulse SENSE is applied, and a second electrode connected to the fifth power line RL to which a reference voltage is applied. do.

The first capacitor Cst is connected between the first node n1 and the second node n2 to store a threshold voltage. One side of the first capacitor Cst is connected to the first node n1 and the other side is connected to the second node n2.

As shown in FIGS. 11A and 11B , the pixel circuit may be driven in the order of an initialization step (Ti), a sensing step (Ts), a data writing step (Tw), and a light emitting step (Tem). In the initialization step Ti, the pixel circuit is initialized. In the sensing step Ts, the threshold voltage Vth of the driving element DT is sensed and stored in the first capacitor Cst. In the data writing step Tw, the data voltage Vdata of the pixel data is applied to the first node n1. After the voltage of the first and second nodes n1 and n2 increases in the boosting step Tboost, the light emitting element EL may emit light with a luminance corresponding to the grayscale value of the pixel data in the light emitting step Tem. .

The pixel circuit may equally apply the first scan pulse and the second scan pulse as shown in FIG. 11A, or may separately apply the first scan pulse and the second scan pulse differently as shown in FIG. 11B.

11B , in the initialization step Ti, the second and third switch elements M02 and M03 are turned on, and the first switch element M01 is turned off. The initialization voltage Vinit is applied to the first node n1, and the reference voltage Vref is applied to the second node n2. At this time, the driving element DT is turned on, and the light emitting element EL is not turned on.

In the sensing step Ts, the second switch element MO3 maintains an on state and the voltage of the second node n2 rises, so that the gate-source voltage Vgs of the driving element DT becomes the threshold voltage Vth. ), the driving element DT is turned off and the threshold voltage Vth is stored in the first capacitor Cst.

During the hold period Th, the second switch element MO2 is turned off and the second node n2 and the third node n3 are floated to maintain the previous voltage.

In the data writing step Tw, the first switch element M01 is turned on. The data voltage Vdata of the pixel data is applied to the second node n2 so that the voltage of the second node n2 is changed by the data voltage Vdata. During the data writing step Tw, the scan pulse SCAN applied to the first switch element M01 may be generated with approximately 0.7 horizontal period (0.7H). At this time, the data voltage Vdata of the pixel data is not applied through one switch element, but applied through the first switch element M01 formed in a double gate structure, so that charging characteristics may be improved.

During the boosting period Tboost, the first, second, and third switch elements M01, M02, and M03 are turned off. At this time, the voltages of the first and second nodes n1 and n2 are increased.

In the light emitting step Tem, the first, second, and third switch elements M01, M02, and M03 maintain an off state. At this time, a current generated according to the voltage Vgs between the gate and source of the driving element DT, that is, the voltage between the first and second nodes n1 and n2 is supplied to the light emitting element EL so that the light emitting element EL may emit light.

Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and may be variously modified and implemented without departing from the technical spirit of the present invention. . Therefore, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but to explain, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The protection scope of the present invention should be construed according to the claims, and all technical ideas within the equivalent range should be construed as being included in the scope of the present invention.

100: display panel
101: pixel
102: data line
103: gate line
110: data driving unit
120: gate driver
130: timing controller
140: power supply

Claims (21)

a driving element including a first electrode connected to a first power supply line to which a pixel driving voltage is applied, a gate electrode connected to a first node, and a second electrode connected to a second node;
a first switch element including a first electrode connected to a second power supply line to which a data voltage is applied, a gate electrode to which a first scan pulse is applied, and a second electrode connected to the first node;
a second switch element including a first electrode connected to the second power line, a gate electrode to which a second scan pulse is applied, and a second electrode connected to the first node;
a light emitting element including an anode electrode connected to the second node and a cathode electrode connected to a third power supply line to which a low potential power supply voltage is applied; and
and a capacitor coupled between the first node and the second node. According to claim 1,
a third switch element including a first electrode connected to a fourth power supply line to which an initialization voltage is applied, a gate electrode to which an initialization pulse is applied, and a second electrode connected to the first node; and
and a fourth switch element including a first electrode connected to the second node, a gate electrode to which a sensing pulse is applied, and a second electrode connected to a fifth power line to which a reference voltage is applied. According to claim 1,
wherein the first switch element and the second switch element turn off at different times during a period in which the data voltage is applied. According to claim 3,
A time point at which the second switch element is turned off varies depending on RC delay or IR drop of the first power line, the second power line, and the third power line. According to claim 3,
The voltage of the first scan pulse swings between a first gate-on voltage and a first gate-off voltage;
wherein the voltage of the second scan pulse swings between the first gate-on voltage and a second gate-off voltage lower than the first gate-off voltage. According to claim 3,
The voltage of the first scan pulse swings between a first gate-on voltage and a first gate-off voltage;
wherein the voltage of the second scan pulse swings between a second gate-on voltage higher than the first gate-on voltage and the first gate-off voltage. According to claim 3,
The voltage of the first scan pulse swings between a first gate-on voltage and a first gate-off voltage;
wherein the voltage of the second scan pulse swings between a second gate-on voltage higher than the first gate-on voltage and a second gate-off voltage lower than the first gate-off voltage. According to claim 1,
The pixel circuit of claim 1 , wherein timings at which the first switch element and the second switch element are turned on are different during a period in which the data voltage is applied. a driving element including a first electrode connected to a first power supply line to which a pixel driving voltage is applied, a gate electrode connected to a first node, and a second electrode connected to a second node;
A first electrode connected to a second power line to which a data voltage is applied, a first gate electrode to which a first scan pulse is applied, a second gate electrode to which a second scan pulse is applied, and a second electrode connected to the first node A first switch element comprising;
a light emitting element including an anode electrode connected to the second node and a cathode electrode connected to a third power supply line to which a low potential power supply voltage is applied; and
and a capacitor coupled between the first node and the second node. According to claim 9,
a second switch element including a first electrode connected to a fourth power line to which an initialization voltage is applied, a gate electrode to which an initialization pulse is applied, and a second electrode connected to the first node; and
and a third switch element including a first electrode connected to the second node, a gate electrode to which a sensing pulse is applied, and a second electrode connected to a fifth power line to which a reference voltage is applied. a display panel on which a plurality of data lines, a plurality of gate lines crossing the data lines, a plurality of power lines to which different constant voltages are applied, and a plurality of subpixels are disposed;
a data driver supplying data voltages of pixel data to the data lines; and
a gate driver supplying a first light emission control pulse and a light emission control pulse to the gate lines;
Each of the sub-pixels,
a driving element including a first electrode connected to a first power supply line to which a pixel driving voltage is applied, a gate electrode connected to a first node, and a second electrode connected to a second node;
a first switch element including a first electrode connected to a second power supply line to which a data voltage is applied, a gate electrode to which a first scan pulse is applied, and a second electrode connected to the first node;
a second switch element including a first electrode connected to the second power line, a gate electrode to which a second scan pulse is applied, and a second electrode connected to the first node;
a light emitting element including an anode electrode connected to the second node and a cathode electrode connected to a third power supply line to which a low potential power supply voltage is applied; and
and a capacitor connected between the first node and the second node. According to claim 11,
a third switch element including a first electrode connected to a fourth power supply line to which an initialization voltage is applied, a gate electrode to which an initialization pulse is applied, and a second electrode connected to the first node; and
and a fourth switch element including a first electrode connected to the second node, a gate electrode to which a sensing pulse is applied, and a second electrode connected to a fifth power line to which a reference voltage is applied. According to claim 11,
wherein the first switch element and the second switch element turn off at different times during a period in which the data voltage is applied. According to claim 13,
A time point at which the second switch element is turned off varies according to RC delay or IR drop of the first power line, the second power line, and the third power line. According to claim 13,
The voltage of the first scan pulse swings between a first gate-on voltage and a first gate-off voltage;
wherein the voltage of the second scan pulse swings between the first gate-on voltage and a second gate-off voltage lower than the first gate-off voltage. According to claim 13,
The voltage of the first scan pulse swings between a first gate-on voltage and a first gate-off voltage;
A voltage of the second scan pulse swings between a second gate-on voltage higher than the first gate-on voltage and the first gate-off. According to claim 13,
The voltage of the first scan pulse swings between a first gate-on voltage and a first gate-off voltage;
wherein the voltage of the second scan pulse swings between a second gate-on voltage higher than the first gate-on voltage and a second gate-off voltage lower than the first gate-off voltage. According to claim 11,
Turn-on times of the first switch element and the second switch element are different during a period in which the data voltage is applied. a display panel on which a plurality of data lines, a plurality of gate lines crossing the data lines, a plurality of power lines to which different constant voltages are applied, and a plurality of subpixels are disposed;
a data driver supplying data voltages of pixel data to the data lines; and
a gate driver supplying a first light emission control pulse and a light emission control pulse to the gate lines;
Each of the sub-pixels,
a driving element including a first electrode connected to a first power supply line to which a pixel driving voltage is applied, a gate electrode connected to a first node, and a second electrode connected to a second node;
A first electrode connected to a second power line to which a data voltage is applied, a first gate electrode to which a first scan pulse is applied, a second gate electrode to which a second scan pulse is applied, and a second electrode connected to the first node A first switch element comprising;
a light emitting element including an anode electrode connected to the second node and a cathode electrode connected to a third power line to which a low potential power supply voltage is applied; and
and a capacitor connected between the first node and the second node. According to claim 19,
a second switch element including a first electrode connected to a fourth power line to which an initialization voltage is applied, a gate electrode to which an initialization pulse is applied, and a second electrode connected to the first node; and
and a third switch element including a first electrode connected to the second node, a gate electrode to which a sensing pulse is applied, and a second electrode connected to a fifth power line to which a reference voltage is applied. The method of claim 11 or 19,
All transistors in a panel including the data driver, the gate driver, and the sub-pixels are implemented as oxide TFTs including an n-channel type oxide semiconductor.

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