KR20230029112A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

The present invention relates to a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a channel layer formed on a substrate and including a two-dimensional electron gas channel therein; an intermediate layer formed on the channel layer to form a two-dimensional electron gas channel and forming a bottom surface of the recess region; a recess structure including a peripheral layer forming a side surface of the recess region; a gate electrode formed on the intermediate layer in the recess region; and a source electrode and a drain electrode formed on the peripheral layer. Therefore, it is possible to provide a semiconductor device with improved ohmic characteristics.

Description

Semiconductor device and its manufacturing method {SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF}

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device capable of forming a recess structure using a selective regrowth process and improving ohmic characteristics, and a method for manufacturing the same.

In general, a recess etching process is used to improve the performance of power devices, such as controlling threshold voltage, reducing gate leakage current, or preventing short channel effects. this applies

In particular, a gallium nitride (GaN)-based High Electron Mobility Transistor (HEMT) can be applied to a power semiconductor device by manufacturing it as a normally-off device by applying a recess etching process. . In addition, a recess etching process may be applied to improve a cut-off frequency of an RF device.

FIG. 1A is a diagram for explaining the structure of a general HEMT device, and FIG. 1B is a diagram for explaining the structure of a HEMT device to which a recess etching process is applied.

Referring to FIG. 1A, a general HEMT device 10 includes a substrate 11, a GaN buffer layer 13, a GaN channel layer 15, an AlGaN barrier layer 17, a gate electrode 19, a source electrode 21, and A drain electrode 23 may be included. Here, the GaN buffer layer 13 is formed on the substrate 11, and the GaN channel layer 15 is formed on the GaN buffer layer 13. In addition, the AlGaN barrier layer 17 is formed on the GaN channel layer 15, and each of the gate electrode 19, the source electrode 21 and the drain electrode 23 is formed on the AlGaN barrier layer 17.

Since the AlGaN barrier layer 17 has a larger band gap and a smaller lattice constant than the GaN channel layer 15, a discontinuity in the band gap exists at the interface between the GaN channel layer 15 and the AlGaN barrier layer 17. Here, the piezoelectric polarization charge due to the difference in lattice constant between the GaN channel layer 15 and the AlGaN barrier layer 17 and the naturally generated polarization charge are limited, so that the 2-Dimensional Electron Gas (hereinafter referred to as 2DEG) is formed. is formed

2DEG is used as a channel between the source electrode 21 and the drain electrode 23, and the current flowing through the channel may vary depending on the voltage applied to the source electrode 21 and the drain electrode 23. The distance between the 2DEG channel and the gate electrode 19 has a significant effect on performance of the HEMT device 10 .

Accordingly, as shown in FIG. 1B , a recess etching process may be used to adjust the distance between the 2DEG channel and the gate electrode 19 . That is, the distance between the 2DEG channel and the gate electrode 19 may be adjusted by forming the recess 25 in a partial region of the AlGaN barrier layer 17 .

This recess etching process is applied as a method of reducing a partial thickness of the AlGaN barrier layer 17 using a dry or wet etching process. Since the recess etching process mainly uses a high-density plasma etching apparatus, the GaN channel layer 15 may be damaged by plasma.

In addition, the surface of the recess 25 may be unevenly etched or damaged depending on the etched position, so that gate leakage current may increase and performance or reliability of the HEMT device 10 may deteriorate. In order to solve this problem, various methods are applied, such as optimizing etching conditions or minimizing etching damage by performing surface treatment after the etching process, but damage due to the etching process eventually occurs.

One embodiment of the present invention is to provide a semiconductor device capable of forming a recess structure using a selective regrowth process and improving ohmic characteristics, and a manufacturing method thereof.

Among embodiments, a semiconductor device may include a channel layer formed on a substrate and including a two-dimensional electron gas channel therein; a recess structure formed on the channel layer to form the two-dimensional electron gas channel and including an intermediate layer forming a bottom surface of the recess region and a peripheral layer forming a side surface of the recess region; a gate electrode formed on the intermediate layer in the recess region; and a source electrode and a drain electrode formed on the peripheral layer.

Here, the intermediate layer includes a barrier layer formed on the entire surface of the channel layer.

Here, the barrier layer is formed of In _x Al _y Ga _1-xy N (here, 0≤x≤1, 0≤y≤1, 0≤(x+y)≤1) layer.

Here, the peripheral layer includes a regrowth barrier layer formed on the barrier layer in regions other than the recess region.

Here, the regrowth barrier layer is formed of In _x Al _y Ga _1-xy N (where 0≤x≤1, 0≤y≤1, 0≤(x+y)≤1) layer.

Here, the peripheral layer further includes an ohmic contact layer formed on the regrowth barrier layer.

Here, the ohmic contact layer is formed of at least one of AlGaN and GaN doped with an n-type impurity, and a stacked structure thereof.

Here, the n-type impurity includes Si.

Here, the n-type impurity is doped at a concentration of 10 ¹⁹ /cm ³ or higher.

Here, the intermediate layer includes a regrowth barrier layer formed on the channel layer corresponding to the recess region.

Here, the regrowth barrier layer is formed of In _x Al _y Ga _1-xy N (where 0≤x≤1, 0≤y≤1, 0≤(x+y)≤1) layer.

Here, the peripheral layer includes an ohmic contact layer formed on the channel layer in a region other than the recess region.

Here, the ohmic contact layer is formed of GaN doped with n-type impurities at a concentration of 10 ¹⁹ /cm ³ or more.

Here, the channel layer is formed of GaN.

Among the embodiments, a method of manufacturing a semiconductor device includes forming a channel layer including a two-dimensional electron gas channel on a substrate; forming a recess structure on the channel layer including an intermediate layer forming a bottom surface of a recess area and a peripheral layer forming a side surface of the recess area; forming a gate electrode on the intermediate layer in the recess region; and forming a source electrode and a drain electrode on the peripheral layer.

Here, the step of forming the intermediate layer includes forming a barrier layer for forming the two-dimensional electron gas channel on the entire surface of the channel layer.

Here, the barrier layer is formed of In _x Al _y Ga _1-xy N (here, 0≤x≤1, 0≤y≤1, 0≤(x+y)≤1) layer.

Here, the forming of the peripheral layer may include forming a mask pattern on the barrier layer to cover a recessed area; forming a re-growth layer on the barrier layer exposed by the mask pattern; and removing the mask pattern.

Here, the regrowth layer is formed of at least one of a regrowth barrier layer, an ohmic contact layer, and a stacked structure thereof.

Here, the regrowth barrier layer is formed of In _x Al _y Ga _1-xy N (here, here, 0≤x≤1, 0≤y≤1, 0≤(x+y)≤1) layer .

Here, the ohmic contact layer is formed of at least one of AlGaN and GaN doped with an n-type impurity, and a stacked structure thereof.

Here, the n-type impurity includes Si.

Here, the n-type impurity is doped at a concentration of 10 ¹⁹ /cm ³ or higher.

Here, forming the peripheral layer may include forming an ohmic contact layer on the entire surface of the channel layer; forming a mask pattern exposing the recess region on the ohmic contact layer; and exposing the channel layer by etching the ohmic contact layer using the mask pattern as an etch mask.

Here, the ohmic contact layer is formed of GaN doped with an n-type impurity at a concentration of 10 ¹⁹ /cm ³ or more.

Here, the forming of the intermediate layer may include forming a regrowth barrier layer for forming the two-dimensional electron gas channel on the channel layer exposed by the mask pattern; and removing the mask pattern.

Here, the regrowth barrier layer is formed of In _x Al _y Ga _1-xy N (where 0≤x≤1, 0≤y≤1, 0≤(x+y)≤1) layer.

The disclosed technology may have the following effects. However, it does not mean that a specific embodiment must include all of the following effects or only the following effects, so it should not be understood that the scope of rights of the disclosed technology is limited thereby.

A semiconductor device and a manufacturing method thereof according to an exemplary embodiment of the present invention may form a recess structure and improve ohmic characteristics by using a selective regrowth process.

1A is a diagram for explaining the structure of a general HEMT device.
1B is a diagram for explaining the structure of a HEMT device to which a recess etching process is applied.
2 is a diagram illustrating a semiconductor device according to an exemplary embodiment of the present invention.
3A to 3E are diagrams illustrating an embodiment of a method of manufacturing the semiconductor device shown in FIG. 2 .
4A to 4D are diagrams illustrating another embodiment of a method of manufacturing the semiconductor device shown in FIG. 2 .
5A to 5D are diagrams illustrating another embodiment of a method of manufacturing the semiconductor device shown in FIG. 2 .
6 is a diagram illustrating a semiconductor device according to another exemplary embodiment of the present invention.
7A to 7E are diagrams illustrating an embodiment of a method of manufacturing the semiconductor device shown in FIG. 6 .
8 is a diagram for explaining ohmic characteristics when an n+ type GaN layer is applied.
9 is a diagram for explaining ohmic resistance measured using a TLM (Transfer Length Method) pattern.

Since the description of the present invention is only an embodiment for structural or functional description, the scope of the present invention should not be construed as being limited by the embodiments described in the text. That is, since the embodiment can be changed in various ways and can have various forms, it should be understood that the scope of the present invention includes equivalents capable of realizing the technical idea. In addition, since the object or effect presented in the present invention does not mean that a specific embodiment should include all of them or only such effects, the scope of the present invention should not be construed as being limited thereto.

Meanwhile, the meaning of terms described in this application should be understood as follows. It should be understood that when an element is referred to as being “connected” to another element, it may be directly connected to the other element, but other elements may exist in the middle. On the other hand, when an element is referred to as being "directly connected" to another element, it should be understood that no intervening elements exist. Meanwhile, other expressions describing the relationship between components, such as “between” and “immediately between” or “adjacent to” and “directly adjacent to” should be interpreted similarly.

Expressions in the singular number should be understood to include plural expressions unless the context clearly dictates otherwise, and terms such as “comprise” or “have” refer to an embodied feature, number, step, operation, component, part, or these. It should be understood that it is intended to indicate that a combination exists, and does not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

All terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs, unless defined otherwise. Terms defined in commonly used dictionaries should be interpreted as consistent with meanings in the context of the related art, and cannot be interpreted as having ideal or excessively formal meanings unless explicitly defined in the present application.

2 is a diagram illustrating a semiconductor device according to an exemplary embodiment of the present invention.

Referring to FIG. 2 , a semiconductor device 100 according to an embodiment of the present invention includes a substrate 110, a buffer layer 120, a channel layer 130, a recess structure RS, a gate electrode 170, a source An electrode 180 and a drain electrode 190 may be included. Here, a case in which the semiconductor device 100 is a gallium nitride (GaN)-based compound semiconductor device, that is, a HEMT device will be described as an example, but the semiconductor device 100 may include other compound semiconductor devices, power semiconductor devices, communication devices, It may be implemented with other elements such as sensor elements.

The substrate 110 may be formed of at least one of sapphire, AlN, BN, SiC, and GaN, but is not limited thereto. The buffer layer 120 is formed on the substrate 110 and may be formed of GaN. The channel layer 130 is formed on the buffer layer 120 and may be formed of GaN. An embodiment of the present invention is not limited thereto, and the channel layer 130 may be formed of any other material as long as the 2DEG channel 132 can be formed.

The recess structure RS may be formed on the channel layer 130 and may include an intermediate layer and a peripheral layer defining the recess region 160 . Here, the recess region 160 is a region corresponding to a planned gate region where the gate electrode 170 is to be formed, and the recess structure RS is formed by molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), or the like. It can be formed using an epitaxial growth process of.

The middle layer according to an embodiment of the present invention may be formed of the barrier layer 140 forming the bottom surface of the recess region 160 and forming the 2DEG channel 132 . The barrier layer 140 may be formed on the entire surface of the channel layer 130 and may be formed of a material having a larger band gap and a smaller lattice constant than the channel layer 130 .

For example, the barrier layer 140 may be formed of In _x Al _y Ga _1-xy N (where 0≤x≤1, 0≤y≤1, 0≤(x+y)≤1) layer. there is. That is, the barrier layer 140 may be formed of at least one of AlN, InAlN, InGaN, AlGaN, and InAlGaN.

The thickness of the barrier layer 140 may be adjusted according to a preset target distance between the 2DEG channel 132 and the gate electrode 170 . That is, the performance of the semiconductor device 100 may be controlled by adjusting the thickness of the barrier layer 140 .

The peripheral layer forms a side surface of the recessed region 160 . The peripheral layer according to an embodiment of the present invention may be formed of the regrowth layer 150 . The re-growth layer 150 is an epitaxial thin film layer re-grown on the barrier layer 140 excluding the recess region 160, and may be formed of the same material as the barrier layer 140 or a material for ohmic junction. . Here, the material for the ohmic junction may include AlGaN or GaN doped with an n-type impurity. The n-type impurity may include Si and may be doped at a concentration of 10 ¹⁹ /cm ³ or higher.

The gate electrode 170 may be formed in the recess region 160 , and the source electrode 180 and the drain electrode 190 may be formed on the regrowth layer 150 . That is, the semiconductor device 100 according to an embodiment of the present invention includes the recess region 160 by forming the bottom and side surfaces of the recess region 160 with the barrier layer 140 and the regrowth layer 150. A recess structure RS may be formed.

Accordingly, since a recess etching process is unnecessary, a phenomenon in which performance or reliability of the semiconductor device 100 is deteriorated due to damage caused by the recess etching process may be prevented. In addition, the effect of the recess etching process can be obtained by adjusting the thickness of the barrier layer 140, and reproducibility and reliability of the process can be secured by forming the barrier layer 140 with a uniform thickness.

3A to 3E are diagrams illustrating an embodiment of a method of manufacturing the semiconductor device shown in FIG. 2 .

Referring to FIG. 3A , first, a substrate 110 is prepared. Here, the substrate 110 may be formed of at least one of sapphire, AlN, BN, SiC, and GaN, but is not limited thereto. Next, a multilayer epitaxial thin film for fabricating the structure of a HEMT device is grown on the substrate 110 . Here, an epitaxial growth process such as molecular beam epitaxy (MBE) or metal organic chemical vapor deposition (MOCVD) may be used for the growth process of the epitaxial thin film.

Specifically, the buffer layer 120 and the channel layer 130 may be sequentially stacked on the substrate 110 . Here, each of the buffer layer 120 and the channel layer 130 may be formed of a GaN layer. An embodiment of the present invention is not limited thereto, and the channel layer 130 may be formed of another material in which the 2DEG channel 132 may be formed.

Then, a barrier layer 140 is formed on the channel layer 130 . The barrier layer 140 is an intermediate layer forming the bottom surface of the recess region 160 and forms the 2DEG channel 132 in the channel layer 130 . The barrier layer 140 may be formed on the entire surface of the channel layer 130 and may have a thickness corresponding to a preset target distance between the 2DEG channel 132 and the gate electrode 170 .

The barrier layer 140 may be formed of a material having a larger band gap and a smaller lattice constant than the channel layer 130 . For example, the barrier layer 140 may be formed of In _x Al _y Ga _1-xy N (where 0≤x≤1, 0≤y≤1, 0≤(x+y)≤1) layer. there is. That is, the barrier layer 140 may be formed of at least one of AlN, InAlN, InGaN, AlGaN, and InAlGaN.

Referring to FIG. 3B , a mask pattern 142 covering a target gate region is formed on the barrier layer 140 . Here, the mask pattern 142 may be formed of an amorphous material in which re-growth of the semiconductor thin film is impossible. For example, the mask pattern 142 may be formed of at least one of SiO ₂ and SiN. The mask pattern 142 may be patterned by a photolithography process using a photoresist film and an etching process. The mask pattern 142 may be formed to a thickness of about 10 nm to 1 μm.

Referring to FIG. 3C , a re-growth layer 150 is formed on the barrier layer 140 exposed by the mask pattern 142 . The regrowth layer 150 is a peripheral layer forming a side surface of the recess region 160 and may be formed of the same material as the barrier layer 140 . That is, the regrowth layer 150 may be formed of the regrowth barrier layer 150a. Here, the regrowth barrier layer 150a may be formed of In _x Al _y Ga _1-xy N (where 0≤x≤1, 0≤y≤1, 0≤(x+y)≤1) layer. there is. For example, the regrowth barrier layer 150a may be formed of at least one of AlN, InAlN, InGaN, AlGaN, and InAlGaN.

Referring to FIG. 3D , the mask pattern 142 is removed. Accordingly, a recess structure RS1 including the recess region 160 is formed.

Referring to FIG. 3E , a source electrode 180 and a drain electrode 190 are formed on the regrowth barrier layer 150a. Then, a heat treatment process is performed to complete the ohmic junction. Here, the heat treatment may be performed at a temperature of about 600 to 1200° C., and may be performed by a rapid thermal process (RTP) to reduce process time. Next, a gate electrode 170 is formed in the recess region 160 . Thus, the semiconductor element 100a is completed.

That is, in the method of manufacturing a semiconductor device according to an embodiment of the present invention, the barrier layer 140 is primarily formed on the channel layer 130 according to the target distance between the 2DEG channel 132 and the gate electrode 170, , secondarily forming the re-growth barrier layer 150a on the region other than the planned gate region.

Accordingly, the recess structure RS1 including the recess region 160 may be formed by a bottom-up method instead of a top-down method of etching the recess. Accordingly, deterioration in device performance due to etching damage occurring during the recess etching process can be prevented, and reproducibility and reliability in the process can be secured because the barrier layer 140 can be formed with a uniform thickness.

4A to 4D are diagrams illustrating another embodiment of a method of manufacturing the semiconductor device shown in FIG. 2 .

Referring to FIG. 4A , first, a substrate 110 is prepared, and a buffer layer 120, a channel layer 130, and a barrier layer 140 are formed on the substrate 110. Next, a mask pattern 142 is formed on the barrier layer 140 to cover the planned gate region. Here, since the process of forming the substrate 110, the buffer layer 120, the channel layer 130, the barrier layer 140, and the mask pattern 142 is the same as the process of FIGS. 3A and 3B, a detailed description thereof will be omitted.

Referring to FIG. 4B , a re-growth layer 150 is formed on the barrier layer 140 exposed by the mask pattern 142 . Here, the re-growth layer 150 is a peripheral layer forming the side surface of the recess region 160 and includes an ohmic contact layer 150b forming an ohmic junction with the source and drain electrodes 180 and 190 to be formed later. can be formed as The present invention is not limited thereto, and the regrowth layer 150 may be formed in a stacked structure of the regrowth barrier layer 150a formed by re-growth from the barrier layer 140 and the ohmic contact layer 150b.

The ohmic contact layer 150b may be formed of an AlGaN layer doped with n-type impurities. Here, the n-type impurity may include Si. That is, in another embodiment of the present invention, the regrowth layer 150 is formed of an epitaxial thin film doped with Si rather than the same material as the barrier layer 140 .

In general, since the conductivity of the epitaxial thin film doped with Si is improved, the ohmic resistance of the source and drain electrodes 180 and 190 to be formed later can be lower than that of the undoped epitaxial thin film. Accordingly, the amount of current flowing through the 2DEG channel 132 can be increased.

Referring to FIG. 4C , the mask pattern 142 is removed. Accordingly, the recess structure RS2 including the recess region 160 is formed.

Referring to FIG. 4D , a source electrode 180 and a drain electrode 190 are formed on the ohmic contact layer 150b. Then, a heat treatment process is performed to complete the ohmic junction.

Then, the gate electrode 170 is formed in the recess region 160 to complete the semiconductor device 100b. Here, since the gate electrode 170 has a relatively narrow width compared to the source electrode 180 and the drain electrode 190, the source electrode 180 and the drain electrode 190 are used as an align key, or the substrate It can be formed through an electron-beam lithography process using an align key separately formed on the dummy region of (100).

However, during the heat treatment process for the ohmic junction, the surface of the source and drain electrodes 180 and 190 may become rough. Similarly, the surface of the align key formed in the dummy area may also become rough. If the e-beam lithography process is performed in this state, the gate electrode 170 may be misaligned. Also, the ohmic resistance of the source and drain electrodes 180 and 190 may increase. Therefore, a manufacturing method according to another embodiment of the present invention capable of forming an ohmic junction without a heat treatment process will be described in detail below.

5A to 5D are diagrams illustrating another embodiment of a method of manufacturing the semiconductor device shown in FIG. 2 .

Referring to FIG. 5A , first, a substrate 110 is prepared, and a buffer layer 120 , a channel layer 130 , and a barrier layer 140 are formed on the substrate 110 . Next, a mask pattern 142 is formed on the barrier layer 140 to cover the planned gate region. Here, since the process of forming the substrate 110, the buffer layer 120, the channel layer 130, the barrier layer 140, and the mask pattern 142 is the same as the process of FIGS. 3A and 3B, a detailed description thereof will be omitted.

Referring to FIG. 5B , a re-growth layer 150 is formed on the barrier layer 140 exposed by the mask pattern 142 . Here, the regrowth layer 150 is a peripheral layer forming the side surface of the recess region 160, and includes the regrowth barrier layer 150a formed of the same material as the barrier layer 140 and the source electrode and drain to be formed later. It may be formed in a laminated structure of the electrodes 180 and 190 and the ohmic contact layer 150c forming an ohmic junction. In another embodiment of the present invention, the regrowth layer 150 is not limited thereto, and may be formed as a single layer of the ohmic contact layer 150c.

The ohmic contact layer 150c may be formed of a GaN layer doped with n-type impurities. Here, the n-type impurity may include Si and may be doped at a concentration of 10 ¹⁹ /cm ³ or higher. When Si is doped at a high concentration, the ohmic resistance is lowered compared to a low concentration, so an ohmic junction can be formed without a heat treatment process, and the amount of current flowing through the 2DEG channel 132 can be increased. A detailed description of this will be described with reference to FIGS. 8 and 9 .

Referring to FIG. 5C , the mask pattern 142 is removed. Accordingly, the recess structure RS3 including the recess region 160 is formed.

Referring to FIG. 5D , a source electrode 180 and a drain electrode 190 are formed on the ohmic contact layer 150c. Then, the gate electrode 170 is formed in the recess region 160 to complete the semiconductor device 100c.

In the semiconductor device 100c having the above structure, the recess structure RS3 is formed by forming the regrowth barrier layer 150a and the ohmic contact layer 150c as the regrowth layer 150 on the barrier layer 140. can In addition, by forming the ohmic contact layer 150c as a heavily doped n+ type GaN layer, the ohmic resistance can be reduced without a separate heat treatment process. Accordingly, it is possible to prevent a phenomenon in which the surfaces of the source electrode 180 and the gate electrode 190 are roughened by the heat treatment process, thereby preventing a phenomenon in which the gate 170 is misaligned during the forming process of the gate 170 .

6 is a diagram illustrating a semiconductor device according to another exemplary embodiment of the present invention.

Referring to FIG. 6 , a semiconductor device 200 according to another embodiment of the present invention includes a substrate 210, a buffer layer 220, a channel layer 230, a recess structure RS′, a gate electrode 270, A source electrode 280 and a drain electrode 290 may be included. The substrate 210 may be formed of at least one of sapphire, AlN, BN, SiC, and GaN, but is not limited thereto.

The buffer layer 220 is formed on the substrate 210 and may be formed of GaN. The channel layer 230 is formed on the buffer layer 220 and may be formed of GaN. An embodiment of the present invention is not limited thereto, and the channel layer 230 may be formed of any other material as long as the material in which the 2DEG channel 232 can be formed.

The recess structure RS′ may be formed on the channel layer 230 and may include a peripheral layer and an intermediate layer defining the recess region 260 . Here, the recess structure RS' may be formed using an epitaxial growth process such as molecular beam epitaxy (MBE) or metal organic chemical vapor deposition (MOCVD).

The peripheral layer according to another embodiment of the present invention may be formed of an ohmic contact layer 240 forming a side surface of the recess region 260 and forming an ohmic junction with the source and drain electrodes 280 and 290. . Here, the ohmic contact layer 240 may be formed not only on the side surface of the recess region 260 but also on the side surface of the barrier layer 250 . That is, the ohmic contact layer 240 may be formed on the channel layer 230 except for the recess region 260 .

The ohmic contact layer 240 may be formed of AlGaN or GaN doped with an n-type impurity. Preferably, the ohmic contact layer 240 may be formed of n+ type GaN doped with Si at a concentration of 10 ¹⁹ /cm ³ or higher.

In addition, the intermediate layer according to another embodiment of the present invention may be formed of the regrowth barrier layer 250 forming the bottom surface of the recess region 260 and forming the 2DEG channel 232 . The re-growth barrier layer 250 is an epitaxial thin film layer re-grown on a portion of the channel layer 230, that is, a region corresponding to the recess region 260, and has a larger band gap and a lattice constant than the channel layer 230. It can be made of small materials.

For example, the regrowth barrier layer 250 may be formed of In _x Al _y Ga _1-xy N (where 0≤x≤1, 0≤y≤1, 0≤(x+y)≤1). can That is, the regrowth barrier layer 250 may be formed of at least one of AlN, InAlN, InGaN, AlGaN, and InAlGaN. The thickness of the regrowth barrier layer 250 may be adjusted according to a preset target distance between the 2DEG channel 232 and the gate electrode 270 . That is, the performance of the semiconductor device 200 can be controlled by adjusting the thickness of the regrowth barrier layer 250 .

The gate electrode 270 may be formed on the recess region 260 , and the source electrode 280 and the drain electrode 290 may be formed on the ohmic contact layer 240 . That is, in the semiconductor device 200 according to another embodiment of the present invention, the regrowth barrier layer 250 is formed only on the bottom surface of the recess region 260, and the side surface of the regrowth barrier layer 250 and the recess region 260 The recess structure RS' may be formed by forming the ohmic contact layer 240 on the side surface of the ).

7A to 7E are diagrams illustrating an embodiment of a method of manufacturing the semiconductor device shown in FIG. 6 .

Referring to FIG. 7A , first, a substrate 210 is prepared. Here, the substrate 210 may be formed of at least one of sapphire, AlN, BN, SiC, and GaN, but is not limited thereto. Next, a multilayer epitaxial thin film for fabricating the structure of a HEMT device is grown on the substrate 210 . Here, an epitaxial growth process such as molecular beam epitaxy (MBE) or metal organic chemical vapor deposition (MOCVD) may be used for the growth process of the epitaxial thin film.

Specifically, the buffer layer 220 and the channel layer 230 may be sequentially stacked on the substrate 210 . Here, each of the buffer layer 220 and the channel layer 230 may be formed of a GaN layer. The embodiment of the present invention is not limited thereto, and the channel layer 230 may be formed of other materials in which the 2DEG channel 232 may be formed.

Then, an ohmic contact layer 240 is formed on the channel layer 230 . Here, the ohmic contact layer 240 is a peripheral layer forming a side surface of the recess region 260 and may be formed of GaN doped with an n-type impurity. Preferably, the ohmic contact layer 240 may be formed of n+ type GaN doped with Si at a concentration of 10 ¹⁹ /cm ³ or higher.

Referring to FIG. 7B , a mask pattern 242 exposing a planned gate region is formed on the ohmic contact layer 240 . Here, the mask pattern 242 may be formed of an amorphous material in which re-growth of the semiconductor thin film is impossible.

For example, the mask pattern 242 may be formed of at least one of SiO ₂ and SiN. The mask pattern 242 may be patterned by a photolithography process using a photoresist film and an etching process.

Referring to FIG. 7C , the channel layer 230 is exposed by etching the ohmic contact layer 240 using the mask pattern 242 as an etch mask.

Referring to FIG. 7D , a regrowth barrier layer 250 is formed on the channel layer 230 exposed by the mask pattern 242 . The regrowth barrier layer 250 is an intermediate layer forming the bottom surface of the recess region 260 and forms the 2DEG channel 232 in the channel layer 230 .

The regrowth barrier layer 250 may be formed to a thickness corresponding to a preset target distance between the 2DEG channel 232 and the gate electrode 270 . Here, the regrowth barrier layer 250 may be formed of In _x Al _y Ga _1-xy N (where 0≤x≤1, 0≤y≤1, 0≤(x+y)≤1) layer. there is. That is, the regrowth barrier layer 250 may be formed of at least one of AlN, InAlN, InGaN, AlGaN, and InAlGaN.

Then, the mask pattern 242 is removed. Accordingly, a recess structure RS′ including the recess region 260 is formed.

Referring to FIG. 7E , a source electrode 280 and a drain electrode 290 are formed on the ohmic contact layer 240 . Then, the gate electrode 270 is formed in the recess region 260 to complete the semiconductor device 200 .

That is, in another embodiment of the present invention, the ohmic contact layer 240 exposing the planned gate region is firstly formed on the channel layer 230, and the ohmic contact layer 240 is secondarily re-grown on the channel layer 230 in the planned gate region. A barrier layer 250 is formed. Accordingly, the recess structure RS′ including the recess region 260 may be formed by a bottom-up method instead of a top-down method of etching the recess.

As a result, device performance degradation due to etching damage occurring during the recess etching process can be prevented, the barrier layer 250 can be uniformly formed by the selective regrowth process, and reproducibility and reliability in the process can be secured. .

In addition, by completing the ohmic junction without a heat treatment process, it is possible to prevent a phenomenon in which the surfaces of the source and drain electrodes 280 and 290 become rough due to the heat treatment process, thereby preventing misalignment during the forming process of the gate electrode 270. there is.

8 is a diagram for explaining ohmic characteristics when an n+ type GaN layer is applied, and FIG. 9 is a diagram for explaining ohmic resistance measured using a TLM (Transfer Length Method) pattern.

In FIG. 8, when the heat treatment process is performed at 650° C. or 850° C. to complete the ohmic junction after forming the source and drain electrodes 180 and 190, (a) and (b) show As shown, it can be seen that the surfaces of the source and drain electrodes 180 and 190 are rough. On the other hand, as in one embodiment of the present invention, in the case of applying an n+ type GaN layer doped with Si at a high concentration of 10 ¹⁹ /cm ³ or more without a heat treatment process, as shown in (c), the source and drain electrodes 180, 190) It can be seen that the roughness of the surface is relatively small and it is in a smooth state. Therefore, when forming the gate electrode 170 through an electron-beam lithography process, a phenomenon in which misalignment occurs due to surface roughness of the source and drain electrodes 180 and 190 can be minimized.

In addition, as shown in FIG. 9, when the heat treatment process is performed at 850° C. after forming the source and drain electrodes 180 and 190, as shown in (a), the ohmic resistance is about 0.69 Ω mm However, as shown in (b), when an n+ type GaN layer doped with Si at a high concentration is applied, as in one embodiment of the present invention, it can be seen that the ohmic resistance is lowered to about 0.25Ω·mm.

That is, when the epitaxial thin film layer in contact with the source and drain electrodes 180 and 190 is formed of an n+ type GaN layer doped with a high concentration of Si, ohmic characteristics can be secured without a heat treatment process.

100, 200: semiconductor element
110, 210: substrate 120, 220: buffer layer
130, 230: channel layer 140: barrier layer
150: regrowth layer 160, 260: recess area
170, 270: gate electrode 180, 280: source electrode
190, 290: drain electrode 240: ohmic contact layer
250: regrowth barrier layer

Claims (27)

a channel layer formed on the substrate and including a two-dimensional electron gas channel therein;
a recess structure formed on the channel layer to form the two-dimensional electron gas channel and including an intermediate layer forming a bottom surface of the recess region and a peripheral layer forming a side surface of the recess region;
a gate electrode formed on the intermediate layer in the recess region; and
A semiconductor device including a source electrode and a drain electrode formed on the peripheral layer. The method of claim 1, wherein the intermediate layer
A semiconductor device comprising a barrier layer formed on an entire surface of the channel layer. The method of claim 2, wherein the barrier layer
A semiconductor device formed of In _x Al _y Ga _1-xy N (here, 0≤x≤1, 0≤y≤1, 0≤(x+y)≤1) layers. The method of claim 2, wherein the peripheral layer
A semiconductor device comprising a regrowth barrier layer formed on the barrier layer in a region other than the recess region. 5. The method of claim 4, wherein the regrowth barrier layer
A semiconductor device formed of In _x Al _y Ga _1-xy N (here, 0≤x≤1, 0≤y≤1, 0≤(x+y)≤1) layers. 5. The method of claim 4, wherein the peripheral layer is
The semiconductor device further comprises an ohmic contact layer formed on the regrowth barrier layer. The method of claim 6 , wherein the ohmic contact layer
A semiconductor device formed of at least one of AlGaN and GaN doped with n-type impurities, and a stacked structure thereof. The method of claim 7, wherein the n-type impurity
A semiconductor device containing Si. The method of claim 7, wherein the n-type impurity
A semiconductor device doped at a concentration of 10 ¹⁹ /cm ³ or more. The method of claim 1, wherein the intermediate layer
and a regrowth barrier layer formed on the channel layer corresponding to the recess region. 11. The method of claim 10, wherein the regrowth barrier layer
A semiconductor device formed of In _x Al _y Ga _1-xy N (here, 0≤x≤1, 0≤y≤1, 0≤(x+y)≤1) layers. 11. The method of claim 10, wherein the peripheral layer
A semiconductor device comprising an ohmic contact layer formed on the channel layer in a region other than the recess region. 13. The method of claim 12, wherein the ohmic contact layer
A semiconductor device formed of GaN doped with an n-type impurity at a concentration of 10 ¹⁹ /cm ³ or higher. The method of claim 1, wherein the channel layer
A semiconductor device made of GaN. Forming a channel layer including a two-dimensional electron gas channel on a substrate;
forming a recess structure on the channel layer including an intermediate layer forming a bottom surface of a recess area and a peripheral layer forming a side surface of the recess area;
forming a gate electrode on the intermediate layer in the recess region; and
A method of manufacturing a semiconductor device comprising forming a source electrode and a drain electrode on the peripheral layer. 16. The method of claim 15, wherein forming the intermediate layer
and forming a barrier layer for forming the two-dimensional electron gas channel on the entire surface of the channel layer. 17. The method of claim 16, wherein the barrier layer
A method of manufacturing a semiconductor device formed of In _x Al _y Ga _1-xy N (where 0≤x≤1, 0≤y≤1, 0≤(x+y)≤1) layers. 17. The method of claim 16, wherein forming the peripheral layer comprises
forming a mask pattern covering a recessed area on the barrier layer;
forming a re-growth layer on the barrier layer exposed by the mask pattern; and
A method of manufacturing a semiconductor device comprising removing the mask pattern. 19. The method of claim 18, wherein the regrowth layer
A method of manufacturing a semiconductor device by forming at least one of a regrowth barrier layer, an ohmic contact layer, and a stacked structure thereof. 20. The method of claim 19, wherein the regrowth barrier layer
A method of manufacturing a semiconductor device formed of In _x Al _y Ga _1-xy N (where 0≤x≤1, 0≤y≤1, 0≤(x+y)≤1) layers. 20. The method of claim 19, wherein the ohmic contact layer
A method of manufacturing a semiconductor device formed of at least one of n-type impurity-doped AlGaN, GaN, and a stacked structure thereof. 22. The method of claim 21, wherein the n-type impurity is
Method for manufacturing a semiconductor device containing Si. 22. The method of claim 21, wherein the n-type impurity is
A method of manufacturing a semiconductor device doped at a concentration of 10 ¹⁹ /cm ³ or more. 16. The method of claim 15, wherein forming the peripheral layer comprises
forming an ohmic contact layer on the entire surface of the channel layer;
forming a mask pattern exposing the recess region on the ohmic contact layer; and
and etching the ohmic contact layer using the mask pattern as an etching mask to expose the channel layer. 25. The method of claim 24, wherein the ohmic contact layer
A method of manufacturing a semiconductor device formed of GaN doped with an n-type impurity at a concentration of 10 ¹⁹ /cm ³ or higher. 25. The method of claim 24, wherein forming the intermediate layer
forming a regrowth barrier layer for forming the two-dimensional electron gas channel on the channel layer exposed by the mask pattern; and
A method of manufacturing a semiconductor device comprising removing the mask pattern. 27. The method of claim 26, wherein the regrowth barrier layer
A method of manufacturing a semiconductor device formed of In _x Al _y Ga _1-xy N (where 0≤x≤1, 0≤y≤1, 0≤(x+y)≤1) layers.

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